1 /* ===-- clear_cache.c - Implement __clear_cache ---------------------------=== 2 * 3 * The LLVM Compiler Infrastructure 4 * 5 * This file is dual licensed under the MIT and the University of Illinois Open 6 * Source Licenses. See LICENSE.TXT for details. 7 * 8 * ===----------------------------------------------------------------------=== 9 */ 10 11 #include "int_lib.h" 12 #include <stddef.h> 13 14 #if __APPLE__ 15 #include <libkern/OSCacheControl.h> 16 #endif 17 #if (defined(__FreeBSD__) || defined(__Bitrig__)) && defined(__arm__) 18 #include <sys/types.h> 19 #include <machine/sysarch.h> 20 #endif 21 22 #if defined(__NetBSD__) && defined(__arm__) 23 #include <machine/sysarch.h> 24 #endif 25 26 #if defined(__mips__) 27 #include <sys/cachectl.h> 28 #include <sys/syscall.h> 29 #include <unistd.h> 30 #if defined(__ANDROID__) && defined(__LP64__) 31 /* 32 * clear_mips_cache - Invalidates instruction cache for Mips. 33 */ 34 static void clear_mips_cache(const void* Addr, size_t Size) { 35 asm volatile ( 36 ".set push\n" 37 ".set noreorder\n" 38 ".set noat\n" 39 "beq %[Size], $zero, 20f\n" /* If size == 0, branch around. */ 40 "nop\n" 41 "daddu %[Size], %[Addr], %[Size]\n" /* Calculate end address + 1 */ 42 "rdhwr $v0, $1\n" /* Get step size for SYNCI. 43 $1 is $HW_SYNCI_Step */ 44 "beq $v0, $zero, 20f\n" /* If no caches require 45 synchronization, branch 46 around. */ 47 "nop\n" 48 "10:\n" 49 "synci 0(%[Addr])\n" /* Synchronize all caches around 50 address. */ 51 "daddu %[Addr], %[Addr], $v0\n" /* Add step size. */ 52 "sltu $at, %[Addr], %[Size]\n" /* Compare current with end 53 address. */ 54 "bne $at, $zero, 10b\n" /* Branch if more to do. */ 55 "nop\n" 56 "sync\n" /* Clear memory hazards. */ 57 "20:\n" 58 "bal 30f\n" 59 "nop\n" 60 "30:\n" 61 "daddiu $ra, $ra, 12\n" /* $ra has a value of $pc here. 62 Add offset of 12 to point to the 63 instruction after the last nop. 64 */ 65 "jr.hb $ra\n" /* Return, clearing instruction 66 hazards. */ 67 "nop\n" 68 ".set pop\n" 69 : [Addr] "+r"(Addr), [Size] "+r"(Size) 70 :: "at", "ra", "v0", "memory" 71 ); 72 } 73 #endif 74 #endif 75 76 #if defined(__ANDROID__) && defined(__arm__) 77 #include <asm/unistd.h> 78 #endif 79 80 /* 81 * The compiler generates calls to __clear_cache() when creating 82 * trampoline functions on the stack for use with nested functions. 83 * It is expected to invalidate the instruction cache for the 84 * specified range. 85 */ 86 87 void __clear_cache(void *start, void *end) { 88 #if __i386__ || __x86_64__ 89 /* 90 * Intel processors have a unified instruction and data cache 91 * so there is nothing to do 92 */ 93 #elif defined(__arm__) && !defined(__APPLE__) 94 #if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__Bitrig__) 95 struct arm_sync_icache_args arg; 96 97 arg.addr = (uintptr_t)start; 98 arg.len = (uintptr_t)end - (uintptr_t)start; 99 100 sysarch(ARM_SYNC_ICACHE, &arg); 101 #elif defined(__ANDROID__) 102 register int start_reg __asm("r0") = (int) (intptr_t) start; 103 const register int end_reg __asm("r1") = (int) (intptr_t) end; 104 const register int flags __asm("r2") = 0; 105 const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush; 106 __asm __volatile("svc 0x0" : "=r"(start_reg) 107 : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags) : "r0"); 108 if (start_reg != 0) { 109 compilerrt_abort(); 110 } 111 #else 112 compilerrt_abort(); 113 #endif 114 #elif defined(__mips__) 115 const uintptr_t start_int = (uintptr_t) start; 116 const uintptr_t end_int = (uintptr_t) end; 117 #if defined(__ANDROID__) && defined(__LP64__) 118 // Call synci implementation for short address range. 119 const uintptr_t address_range_limit = 256; 120 if ((end_int - start_int) <= address_range_limit) { 121 clear_mips_cache(start, (end_int - start_int)); 122 } else { 123 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE); 124 } 125 #else 126 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE); 127 #endif 128 #elif defined(__aarch64__) && !defined(__APPLE__) 129 uint64_t xstart = (uint64_t)(uintptr_t) start; 130 uint64_t xend = (uint64_t)(uintptr_t) end; 131 uint64_t addr; 132 133 // Get Cache Type Info 134 uint64_t ctr_el0; 135 __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0)); 136 137 /* 138 * dc & ic instructions must use 64bit registers so we don't use 139 * uintptr_t in case this runs in an IPL32 environment. 140 */ 141 const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15); 142 for (addr = xstart; addr < xend; addr += dcache_line_size) 143 __asm __volatile("dc cvau, %0" :: "r"(addr)); 144 __asm __volatile("dsb ish"); 145 146 const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15); 147 for (addr = xstart; addr < xend; addr += icache_line_size) 148 __asm __volatile("ic ivau, %0" :: "r"(addr)); 149 __asm __volatile("isb sy"); 150 #else 151 #if __APPLE__ 152 /* On Darwin, sys_icache_invalidate() provides this functionality */ 153 sys_icache_invalidate(start, end-start); 154 #else 155 compilerrt_abort(); 156 #endif 157 #endif 158 } 159 160
