1 //==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Select instructions 12 //===----------------------------------------------------------------------===// 13 14 // C's ?: operator for floating-point operands. 15 def SelectF32 : SelectWrapper<FP32>; 16 def SelectF64 : SelectWrapper<FP64>; 17 def SelectF128 : SelectWrapper<FP128>; 18 19 defm CondStoreF32 : CondStores<FP32, nonvolatile_store, 20 nonvolatile_load, bdxaddr20only>; 21 defm CondStoreF64 : CondStores<FP64, nonvolatile_store, 22 nonvolatile_load, bdxaddr20only>; 23 24 //===----------------------------------------------------------------------===// 25 // Move instructions 26 //===----------------------------------------------------------------------===// 27 28 // Load zero. 29 let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in { 30 def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>; 31 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>; 32 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>; 33 } 34 35 // Moves between two floating-point registers. 36 let hasSideEffects = 0 in { 37 def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>; 38 def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>; 39 def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>; 40 } 41 42 // Moves between two floating-point registers that also set the condition 43 // codes. 44 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 45 defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>; 46 defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>; 47 defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>; 48 } 49 // Note that LTxBRCompare is not available if we have vector support, 50 // since load-and-test instructions will partially clobber the target 51 // (vector) register. 52 let Predicates = [FeatureNoVector] in { 53 defm : CompareZeroFP<LTEBRCompare, FP32>; 54 defm : CompareZeroFP<LTDBRCompare, FP64>; 55 defm : CompareZeroFP<LTXBRCompare, FP128>; 56 } 57 58 // Use a normal load-and-test for compare against zero in case of 59 // vector support (via a pseudo to simplify instruction selection). 60 let Defs = [CC], usesCustomInserter = 1 in { 61 def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>; 62 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>; 63 def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>; 64 } 65 let Predicates = [FeatureVector] in { 66 defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>; 67 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>; 68 defm : CompareZeroFP<LTXBRCompare_VecPseudo, FP128>; 69 } 70 71 // Moves between 64-bit integer and floating-point registers. 72 def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>; 73 def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>; 74 75 // fcopysign with an FP32 result. 76 let isCodeGenOnly = 1 in { 77 def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>; 78 def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>; 79 } 80 81 // The sign of an FP128 is in the high register. 82 def : Pat<(fcopysign FP32:$src1, FP128:$src2), 83 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 84 85 // fcopysign with an FP64 result. 86 let isCodeGenOnly = 1 in 87 def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>; 88 def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>; 89 90 // The sign of an FP128 is in the high register. 91 def : Pat<(fcopysign FP64:$src1, FP128:$src2), 92 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 93 94 // fcopysign with an FP128 result. Use "upper" as the high half and leave 95 // the low half as-is. 96 class CopySign128<RegisterOperand cls, dag upper> 97 : Pat<(fcopysign FP128:$src1, cls:$src2), 98 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>; 99 100 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64), 101 FP32:$src2)>; 102 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 103 FP64:$src2)>; 104 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 105 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 106 107 defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>; 108 defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>; 109 defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>; 110 111 //===----------------------------------------------------------------------===// 112 // Load instructions 113 //===----------------------------------------------------------------------===// 114 115 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 116 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>; 117 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>; 118 119 // For z13 we prefer LDE over LE to avoid partial register dependencies. 120 def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>; 121 122 // These instructions are split after register allocation, so we don't 123 // want a custom inserter. 124 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 125 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 126 [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 127 } 128 } 129 130 //===----------------------------------------------------------------------===// 131 // Store instructions 132 //===----------------------------------------------------------------------===// 133 134 let SimpleBDXStore = 1 in { 135 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>; 136 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>; 137 138 // These instructions are split after register allocation, so we don't 139 // want a custom inserter. 140 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 141 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 142 [(store FP128:$src, bdxaddr20only128:$dst)]>; 143 } 144 } 145 146 //===----------------------------------------------------------------------===// 147 // Conversion instructions 148 //===----------------------------------------------------------------------===// 149 150 // Convert floating-point values to narrower representations, rounding 151 // according to the current mode. The destination of LEXBR and LDXBR 152 // is a 128-bit value, but only the first register of the pair is used. 153 def LEDBR : UnaryRRE<"ledb", 0xB344, fround, FP32, FP64>; 154 def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>; 155 def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>; 156 157 def LEDBRA : UnaryRRF4<"ledbra", 0xB344, FP32, FP64>, 158 Requires<[FeatureFPExtension]>; 159 def LEXBRA : UnaryRRF4<"lexbra", 0xB346, FP128, FP128>, 160 Requires<[FeatureFPExtension]>; 161 def LDXBRA : UnaryRRF4<"ldxbra", 0xB345, FP128, FP128>, 162 Requires<[FeatureFPExtension]>; 163 164 def : Pat<(f32 (fround FP128:$src)), 165 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>; 166 def : Pat<(f64 (fround FP128:$src)), 167 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; 168 169 // Extend register floating-point values to wider representations. 170 def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64, FP32>; 171 def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>; 172 def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>; 173 174 // Extend memory floating-point values to wider representations. 175 def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>; 176 def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>; 177 def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>; 178 179 // Convert a signed integer register value to a floating-point one. 180 def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32, GR32>; 181 def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64, GR32>; 182 def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>; 183 184 def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32, GR64>; 185 def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>; 186 def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>; 187 188 // Convert am unsigned integer register value to a floating-point one. 189 let Predicates = [FeatureFPExtension] in { 190 def CELFBR : UnaryRRF4<"celfbr", 0xB390, FP32, GR32>; 191 def CDLFBR : UnaryRRF4<"cdlfbr", 0xB391, FP64, GR32>; 192 def CXLFBR : UnaryRRF4<"cxlfbr", 0xB392, FP128, GR32>; 193 194 def CELGBR : UnaryRRF4<"celgbr", 0xB3A0, FP32, GR64>; 195 def CDLGBR : UnaryRRF4<"cdlgbr", 0xB3A1, FP64, GR64>; 196 def CXLGBR : UnaryRRF4<"cxlgbr", 0xB3A2, FP128, GR64>; 197 198 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>; 199 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>; 200 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>; 201 202 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>; 203 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>; 204 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>; 205 } 206 207 // Convert a floating-point register value to a signed integer value, 208 // with the second operand (modifier M3) specifying the rounding mode. 209 let Defs = [CC] in { 210 def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>; 211 def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>; 212 def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>; 213 214 def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>; 215 def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>; 216 def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>; 217 } 218 219 // fp_to_sint always rounds towards zero, which is modifier value 5. 220 def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 221 def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 222 def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 223 224 def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 225 def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 226 def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 227 228 // Convert a floating-point register value to an unsigned integer value. 229 let Predicates = [FeatureFPExtension] in { 230 let Defs = [CC] in { 231 def CLFEBR : UnaryRRF4<"clfebr", 0xB39C, GR32, FP32>; 232 def CLFDBR : UnaryRRF4<"clfdbr", 0xB39D, GR32, FP64>; 233 def CLFXBR : UnaryRRF4<"clfxbr", 0xB39E, GR32, FP128>; 234 235 def CLGEBR : UnaryRRF4<"clgebr", 0xB3AC, GR64, FP32>; 236 def CLGDBR : UnaryRRF4<"clgdbr", 0xB3AD, GR64, FP64>; 237 def CLGXBR : UnaryRRF4<"clgxbr", 0xB3AE, GR64, FP128>; 238 } 239 240 def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>; 241 def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>; 242 def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>; 243 244 def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>; 245 def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>; 246 def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>; 247 } 248 249 250 //===----------------------------------------------------------------------===// 251 // Unary arithmetic 252 //===----------------------------------------------------------------------===// 253 254 // We prefer generic instructions during isel, because they do not 255 // clobber CC and therefore give the scheduler more freedom. In cases 256 // the CC is actually useful, the SystemZElimCompare pass will try to 257 // convert generic instructions into opcodes that also set CC. Note 258 // that lcdf / lpdf / lndf only affect the sign bit, and can therefore 259 // be used with fp32 as well. This could be done for fp128, in which 260 // case the operands would have to be tied. 261 262 // Negation (Load Complement). 263 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 264 def LCEBR : UnaryRRE<"lceb", 0xB303, null_frag, FP32, FP32>; 265 def LCDBR : UnaryRRE<"lcdb", 0xB313, null_frag, FP64, FP64>; 266 def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>; 267 } 268 // Generic form, which does not set CC. 269 def LCDFR : UnaryRRE<"lcdf", 0xB373, fneg, FP64, FP64>; 270 let isCodeGenOnly = 1 in 271 def LCDFR_32 : UnaryRRE<"lcdf", 0xB373, fneg, FP32, FP32>; 272 273 // Absolute value (Load Positive). 274 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 275 def LPEBR : UnaryRRE<"lpeb", 0xB300, null_frag, FP32, FP32>; 276 def LPDBR : UnaryRRE<"lpdb", 0xB310, null_frag, FP64, FP64>; 277 def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>; 278 } 279 // Generic form, which does not set CC. 280 def LPDFR : UnaryRRE<"lpdf", 0xB370, fabs, FP64, FP64>; 281 let isCodeGenOnly = 1 in 282 def LPDFR_32 : UnaryRRE<"lpdf", 0xB370, fabs, FP32, FP32>; 283 284 // Negative absolute value (Load Negative). 285 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 286 def LNEBR : UnaryRRE<"lneb", 0xB301, null_frag, FP32, FP32>; 287 def LNDBR : UnaryRRE<"lndb", 0xB311, null_frag, FP64, FP64>; 288 def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>; 289 } 290 // Generic form, which does not set CC. 291 def LNDFR : UnaryRRE<"lndf", 0xB371, fnabs, FP64, FP64>; 292 let isCodeGenOnly = 1 in 293 def LNDFR_32 : UnaryRRE<"lndf", 0xB371, fnabs, FP32, FP32>; 294 295 // Square root. 296 def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>; 297 def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>; 298 def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>; 299 300 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>; 301 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>; 302 303 // Round to an integer, with the second operand (modifier M3) specifying 304 // the rounding mode. These forms always check for inexact conditions. 305 def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>; 306 def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>; 307 def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>; 308 309 // frint rounds according to the current mode (modifier 0) and detects 310 // inexact conditions. 311 def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; 312 def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; 313 def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; 314 315 let Predicates = [FeatureFPExtension] in { 316 // Extended forms of the FIxBR instructions. M4 can be set to 4 317 // to suppress detection of inexact conditions. 318 def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>; 319 def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>; 320 def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>; 321 322 // fnearbyint is like frint but does not detect inexact conditions. 323 def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>; 324 def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>; 325 def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>; 326 327 // floor is no longer allowed to raise an inexact condition, 328 // so restrict it to the cases where the condition can be suppressed. 329 // Mode 7 is round towards -inf. 330 def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>; 331 def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>; 332 def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>; 333 334 // Same idea for ceil, where mode 6 is round towards +inf. 335 def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>; 336 def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>; 337 def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>; 338 339 // Same idea for trunc, where mode 5 is round towards zero. 340 def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>; 341 def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>; 342 def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>; 343 344 // Same idea for round, where mode 1 is round towards nearest with 345 // ties away from zero. 346 def : Pat<(frnd FP32:$src), (FIEBRA 1, FP32:$src, 4)>; 347 def : Pat<(frnd FP64:$src), (FIDBRA 1, FP64:$src, 4)>; 348 def : Pat<(frnd FP128:$src), (FIXBRA 1, FP128:$src, 4)>; 349 } 350 351 //===----------------------------------------------------------------------===// 352 // Binary arithmetic 353 //===----------------------------------------------------------------------===// 354 355 // Addition. 356 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 357 let isCommutable = 1 in { 358 def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>; 359 def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>; 360 def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>; 361 } 362 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>; 363 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>; 364 } 365 366 // Subtraction. 367 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 368 def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32, FP32>; 369 def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64, FP64>; 370 def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>; 371 372 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>; 373 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>; 374 } 375 376 // Multiplication. 377 let isCommutable = 1 in { 378 def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32, FP32>; 379 def MDBR : BinaryRRE<"mdb", 0xB31C, fmul, FP64, FP64>; 380 def MXBR : BinaryRRE<"mxb", 0xB34C, fmul, FP128, FP128>; 381 } 382 def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>; 383 def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>; 384 385 // f64 multiplication of two FP32 registers. 386 def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>; 387 def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))), 388 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 389 FP32:$src1, subreg_r32), FP32:$src2)>; 390 391 // f64 multiplication of an FP32 register and an f32 memory. 392 def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; 393 def : Pat<(fmul (f64 (fextend FP32:$src1)), 394 (f64 (extloadf32 bdxaddr12only:$addr))), 395 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32), 396 bdxaddr12only:$addr)>; 397 398 // f128 multiplication of two FP64 registers. 399 def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>; 400 def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))), 401 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 402 FP64:$src1, subreg_h64), FP64:$src2)>; 403 404 // f128 multiplication of an FP64 register and an f64 memory. 405 def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>; 406 def : Pat<(fmul (f128 (fextend FP64:$src1)), 407 (f128 (extloadf64 bdxaddr12only:$addr))), 408 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64), 409 bdxaddr12only:$addr)>; 410 411 // Fused multiply-add. 412 def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>; 413 def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>; 414 415 def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>; 416 def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>; 417 418 // Fused multiply-subtract. 419 def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>; 420 def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>; 421 422 def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>; 423 def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>; 424 425 // Division. 426 def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32, FP32>; 427 def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64, FP64>; 428 def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>; 429 430 def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>; 431 def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>; 432 433 //===----------------------------------------------------------------------===// 434 // Comparisons 435 //===----------------------------------------------------------------------===// 436 437 let Defs = [CC], CCValues = 0xF in { 438 def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32, FP32>; 439 def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64, FP64>; 440 def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>; 441 442 def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>; 443 def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>; 444 } 445 446 //===----------------------------------------------------------------------===// 447 // Peepholes 448 //===----------------------------------------------------------------------===// 449 450 def : Pat<(f32 fpimmneg0), (LCDFR_32 (LZER))>; 451 def : Pat<(f64 fpimmneg0), (LCDFR (LZDR))>; 452 def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 453
