/external/llvm/lib/Target/SystemZ/ |
SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc(); 33 if (MCID.mayLoad()) 35 if (MCID.mayStore())
|
/external/llvm/lib/Target/ARM/ |
ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 26 unsigned Opcode = MCID.getOpcode(); 43 const MCInstrDesc &MCID = MI->getDesc(); 44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
|
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
ExpandISelPseudos.cpp | 65 const MCInstrDesc &MCID = MI->getDesc(); 66 if (MCID.usesCustomInsertionHook()) {
|
ScoreboardHazardRecognizer.cpp | 118 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 119 if (MCID == NULL) { 123 unsigned idx = MCID->getSchedClass(); 176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 177 assert(MCID && "The scheduler must filter non-machineinstrs"); 178 if (DAG->TII->isZeroCost(MCID->Opcode)) 185 unsigned idx = MCID->getSchedClass();
|
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 24 if (MCID.mayStore()) 26 unsigned Opcode = MCID.getOpcode(); 46 const MCInstrDesc &MCID = MI->getDesc(); 47 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
|
Thumb1RegisterInfo.cpp | 240 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); 242 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg) 290 const MCInstrDesc &MCID = TII.get(ExtraOpc); 291 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) 359 const MCInstrDesc &MCID = TII.get(ARM::tRSB); 360 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
|
/external/swiftshader/third_party/LLVM/lib/Target/ |
TargetInstrInfo.cpp | 31 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, 33 if (OpNum >= MCID.getNumOperands()) 36 short RegClass = MCID.OpInfo[OpNum].RegClass; 37 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) 133 const MCInstrDesc &MCID = MI->getDesc(); 134 if (!MCID.isTerminator()) return false; 137 if (MCID.isBranch() && !MCID.isBarrier()) 139 if (!MCID.isPredicable())
|
/external/llvm/lib/CodeGen/ |
ScoreboardHazardRecognizer.cpp | 120 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 121 if (!MCID) { 125 unsigned idx = MCID->getSchedClass(); 176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 177 assert(MCID && "The scheduler must filter non-machineinstrs"); 178 if (DAG->TII->isZeroCost(MCID->Opcode)) 185 unsigned idx = MCID->getSchedClass();
|
ExecutionDepsFix.cpp | 516 const MCInstrDesc &MCID = MI->getDesc(); 518 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
|
/external/llvm/lib/Target/Lanai/ |
LanaiDelaySlotFiller.cpp | 231 MCInstrDesc MCID = MI->getDesc(); 232 unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands()
|
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
MSP430InstrInfo.cpp | 164 const MCInstrDesc &MCID = MI->getDesc(); 165 if (!MCID.isTerminator()) return false; 168 if (MCID.isBranch() && !MCID.isBarrier()) 170 if (!MCID.isPredicable())
|
/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
MipsDelaySlotFiller.cpp | 177 MCInstrDesc MCID = candidate->getDesc(); 180 if (MCID.mayLoad()) { 186 if (MCID.mayStore()) { 194 assert((!MCID.isCall() && !MCID.isReturn()) && 223 MCInstrDesc MCID = MI->getDesc(); 224 unsigned e = MCID.isCall() || MCID.isReturn() ? MCID.getNumOperands() : 228 if (MCID.isCall() [all...] |
MipsInstrInfo.cpp | 360 const MCInstrDesc &MCID = get(Opc); 361 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
|
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
PPCHazardRecognizers.cpp | 76 const MCInstrDesc &MCID = TII.get(Opcode); 78 isLoad = MCID.mayLoad(); 79 isStore = MCID.mayStore(); 81 uint64_t TSFlags = MCID.TSFlags;
|
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
SystemZInstrBuilder.h | 111 const MCInstrDesc &MCID = MI->getDesc(); 113 if (MCID.mayLoad()) 115 if (MCID.mayStore())
|
SystemZInstrInfo.cpp | 206 const MCInstrDesc &MCID = MI->getDesc(); 207 if (!MCID.isTerminator()) return false; 210 if (MCID.isBranch() && !MCID.isBarrier()) 212 if (!MCID.isPredicable())
|
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
X86InstrBuilder.h | 153 const MCInstrDesc &MCID = MI->getDesc(); 155 if (MCID.mayLoad()) 157 if (MCID.mayStore())
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 324 const MCInstrDesc &MCID = MIB->getDesc(); 325 bool isOptDef = IIOpNum < MCID.getNumOperands() && 326 MCID.OpInfo[IIOpNum].isOptionalDef(); 363 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; [all...] |
/external/llvm/lib/Target/Mips/ |
MipsInstrInfo.cpp | 101 const MCInstrDesc &MCID = get(Opc); 102 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
|
/external/llvm/lib/Target/NVPTX/ |
NVPTXReplaceImageHandles.cpp | 81 const MCInstrDesc &MCID = MI.getDesc(); 83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { 89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { 95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { 97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); 105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { 112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) {
|
/external/llvm/lib/Target/PowerPC/ |
PPCHazardRecognizers.cpp | 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 32 if (!MCID) 35 if (!MCID->mayLoad()) 57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 58 if (!MCID) 61 if (!MCID->isBranch()) 87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, 92 unsigned IIC = MCID->getSchedClass(); 125 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1) 149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU) [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrBuilder.h | 181 const MCInstrDesc &MCID = MI->getDesc(); 183 if (MCID.mayLoad()) 185 if (MCID.mayStore())
|
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
MachineInstr.h | 61 const MCInstrDesc *MCID; // Instruction descriptor. 93 /// MCID NULL and no operands. 103 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false); 108 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID); 113 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl, 120 const MCInstrDesc &MCID); 191 const MCInstrDesc &getDesc() const { return *MCID; } 195 int getOpcode() const { return MCID->Opcode; } 532 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
|
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 285 const MCInstrDesc &MCID = MI->getDesc(); 286 bool isOptDef = IIOpNum < MCID.getNumOperands() && 287 MCID.OpInfo[IIOpNum].isOptionalDef(); 297 assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) && 714 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 715 UsedRegs.append(MCID.getImplicitUses(), 716 MCID.getImplicitUses() + MCID.getNumImplicitUses()); [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineInstr.h | 78 const MCInstrDesc *MCID; // Instruction descriptor. 133 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl, 283 const MCInstrDesc &getDesc() const { return *MCID; } 286 unsigned getOpcode() const { return MCID->Opcode; } 418 return hasProperty(MCID::Variadic, Type); 424 return hasProperty(MCID::HasOptionalDef, Type); 430 return hasProperty(MCID::Pseudo, Type); 434 return hasProperty(MCID::Return, Type); 438 return hasProperty(MCID::Call, Type); 445 return hasProperty(MCID::Barrier, Type) [all...] |