| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
15 #include "ARM.h"
33 case ARM::LDR_PRE_IMM:
34 case ARM::LDR_PRE_REG:
35 case ARM::LDR_POST_IMM:
36 case ARM::LDR_POST_REG:
37 return ARM::LDRi12;
38 case ARM::LDRH_PRE:
39 case ARM::LDRH_POST
[all...] |
| ARMExpandPseudoInsts.cpp | 17 #define DEBUG_TYPE "arm-pseudo"
18 #include "ARM.h"
34 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
35 cl::desc("Verify machine code after expanding ARM pseudos"));
51 return "ARM pseudo instruction expansion pass";
125 { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, SingleSpc, 2, 4},
126 { ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, SingleSpc, 2, 4},
127 { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, SingleSpc, 2, 2}
[all...] |
| ARMBaseRegisterInfo.cpp | 1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
14 #include "ARM.h"
48 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
54 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
61 BasePtr(ARM::R6) {
74 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8
[all...] |
| ARMELFWriterInfo.cpp | 1 //===-- ARMELFWriterInfo.cpp - ELF Writer Info for the ARM backend --------===//
10 // This file implements ELF writer information for the ARM backend.
37 case ARM::reloc_arm_absolute:
38 case ARM::reloc_arm_relative:
39 case ARM::reloc_arm_cp_entry:
40 case ARM::reloc_arm_vfp_cp_entry:
41 case ARM::reloc_arm_machine_cp_entry:
42 case ARM::reloc_arm_jt_base:
43 case ARM::reloc_arm_pic_jt:
44 assert(0 && "unsupported ARM relocation type"); break
[all...] |
| Thumb2InstrInfo.cpp | 15 #include "ARM.h"
74 if (MBBI->getOpcode() == ARM::t2IT) {
112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
124 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
125 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
126 RC == ARM::GPRnopcRegisterClass) {
138 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)
[all...] |
| Thumb2SizeReduction.cpp | 11 #include "ARM.h"
59 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0 },
60 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1 },
61 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0 },
62 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1 }
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFeatures.h | 1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
10 // This file contains the code shared between ARM CodeGen and ARM MC
29 case ARM::tADC:
30 case ARM::tADDi3:
31 case ARM::tADDi8:
32 case ARM::tADDrr:
33 case ARM::tAND:
34 case ARM::tASRri:
35 case ARM::tASRrr
[all...] |
| ARMInstrInfo.cpp | 1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
15 #include "ARM.h"
38 NopInst.setOpcode(ARM::HINT);
43 NopInst.setOpcode(ARM::MOVr);
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
45 NopInst.addOperand(MCOperand::createReg(ARM::R0));
56 case ARM::LDR_PRE_IMM:
57 case ARM::LDR_PRE_REG:
58 case ARM::LDR_POST_IMM
[all...] |
| ARMExpandPseudoInsts.cpp | 17 #include "ARM.h"
35 #define DEBUG_TYPE "arm-pseudo"
38 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
39 cl::desc("Verify machine code after expanding ARM pseudos"));
60 return "ARM pseudo instruction expansion pass";
150 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
151 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
152 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}
[all...] |
| Thumb2SizeReduction.cpp | 10 #include "ARM.h"
64 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
65 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
66 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
67 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 }
[all...] |
| ARMBaseInstrInfo.cpp | 1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
14 #include "ARM.h"
45 #define DEBUG_TYPE "arm-instrinfo"
51 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
52 cl::desc("Enable ARM 2-addr to 3-addr conv"));
66 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
67 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-arm/ |
| discard-unwind.ld | 2 OUTPUT_ARCH(arm)
13 *(.ARM.extab*)
17 /DISCARD/ : { *(.ARM.exidx*) }
18 .ARM.attribues 0 : { *(.ARM.atttributes) }
|
| arm.ld | 2 OUTPUT_ARCH(arm)
13 *(.ARM.extab*)
17 .ARM.exidx : { *(.ARM.exidx*) }
22 .ARM.attribues 0 : { *(.ARM.atttributes) }
|
| arm-target1-abs.d | 6 # Ignore .ARM.attributes section
|
| arm-target1-rel.d | 6 # Ignore .ARM.attributes section
|
| /external/llvm/unittests/Support/ |
| TargetParserTest.cpp | 19 llvm::ARM::ID,
31 for (ARM::ArchKind AK = static_cast<ARM::ArchKind>(0);
32 AK <= ARM::ArchKind::AK_LAST;
33 AK = static_cast<ARM::ArchKind>(static_cast<unsigned>(AK) + 1))
34 EXPECT_TRUE(AK == ARM::AK_LAST ? ARM::getArchName(AK).empty()
35 : !ARM::getArchName(AK).empty());
39 for (ARM::ArchKind AK = static_cast<ARM::ArchKind>(0)
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| blx-bad.s | 1 .arm
2 .func ARM
3 ARM: nop
8 blx ARM
10 blx ARM
|
| insn-error-a.l | 2 [^:]*:4: Error: ARM register expected -- `movne r33,r9'
|
| /external/llvm/test/MC/ARM/ |
| virtexts-arm.s | 1 # RUN: llvm-mc -triple armv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-ARM
7 # CHECK-ARM: [0x71,0x00,0x40,0xe1]
8 # CHECK-ARM: [0x77,0x00,0x40,0xe1]
9 # CHECK-ARM: [0x71,0x10,0x40,0xe1]
10 # CHECK-ARM: [0x7f,0xff,0x4f,0xe1]
27 # CHECK-ARM: [0x6e,0x00,0x60,0xe1]
28 # CHECK-ARM: [0x6e,0x00,0x60,0x01]
29 # CHECK-ARM: [0x6e,0x00,0x60,0x11]
30 # CHECK-ARM: [0x6e,0x00,0x60,0x21]
31 # CHECK-ARM: [0x6e,0x00,0x60,0x31
[all...] |
| big-endian-arm-fixup.s | 8 @ARM::fixup_arm_condbl
15 @ARM::fixup_arm_uncondbl
22 @ARM::fixup_arm_blx
29 @ARM::fixup_arm_uncondbranch
36 @ARM::fixup_arm_condbranch
43 @ARM::fixup_arm_pcrel_10
50 @ARM::fixup_arm_ldst_pcrel_12
57 @ARM::fixup_arm_adr_pcrel_12
64 @ARM::fixup_arm_adr_pcrel_10_unscaled
71 @ARM::fixup_arm_movw_lo1
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| dg.exp | 3 if { [llvm_supports_target ARM] } {
|
| /toolchain/binutils/binutils-2.25/gold/testsuite/ |
| script_test_4.t | 33 /* Required by the ARM target. */
34 .ARM.extab : { *(.ARM.extab*) }
35 .ARM.exidx : { *(.ARM.exidx*) }
|
| script_test_5.t | 33 /* Required by the ARM target. */
34 .ARM.extab : { *(.ARM.extab*) }
35 .ARM.exidx : { *(.ARM.exidx*) }
|
| script_test_6.t | 34 /* Required by the ARM target. */
35 .ARM.extab : { *(.ARM.extab*) }
36 .ARM.exidx : { *(.ARM.exidx*) }
|
| script_test_7.t | 34 /* Required by the ARM target. */
35 .ARM.extab : { *(.ARM.extab*) }
36 .ARM.exidx : { *(.ARM.exidx*) }
|
