| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinInstrInfo.cpp | 92 BuildMI(&MBB, DL, get(BF::JUMPa)).addMBB(TBB);
105 BuildMI(MBB, I, DL, get(BF::MOVE), DestReg)
111 BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg)
119 BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg)
121 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
125 BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg)
133 BuildMI(MBB, I, DL, get(BF::SETEQri_not), DestReg)
138 BuildMI(MBB, I, DL, get(BF::MOVECC_nz), DestReg)
146 BuildMI(MBB, I, DL, get(BF::MOVE_ncccc), DestReg)
152 BuildMI(MBB, I, DL, get(BF::MOVE_ccncc), DestReg
[all...] |
| BlackfinFrameLowering.cpp | 69 BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
79 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
81 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
83 BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
86 BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
113 BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
|
| SparcInstrInfo.cpp | 194 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
196 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
229 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
237 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
239 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
243 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
274 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
277 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
280 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
296 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 119 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
124 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
128 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
131 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
136 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
139 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
141 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
144 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
147 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2)
150 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2
[all...] |
| SPUNopFiller.cpp | 96 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::ENOP));
105 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::LNOP));
121 BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::ENOP));
126 BuildMI(MBB, J, DebugLoc(), TII->get(SPU::LNOP));
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsFrameLowering.cpp | 128 BuildMI(MBB, I, DL, TII->get(Mips::NOAT));
129 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
130 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
165 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
169 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD))
171 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
183 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
188 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
192 BuildMI(MBB, MBBI, dl,
209 BuildMI(MBB, MBBI, dl
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaFrameLowering.cpp | 56 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29)
58 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29)
61 BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT))
82 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
85 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
87 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
95 BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ))
98 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15)
123 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
126 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15
[all...] |
| AlphaLLRP.cpp | 77 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
89 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
92 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
103 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
105 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
107 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
140 BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31)
|
| AlphaInstrInfo.cpp | 99 BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(TBB);
102 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
105 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
112 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
115 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
117 BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(FBB);
126 BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
130 BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
134 BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
150 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 10 // This file exposes a function named BuildMI, which is useful for dramatically
13 // M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
242 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
249 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
258 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
274 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
284 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
290 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg);
291 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
294 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
313 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
316 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
322 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)
[all...] |
| PPCInstrInfo.cpp | 141 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
165 BuildMI(MBB, MI, DL, get(PPC::NOP));
288 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
290 BuildMI(&MBB, DL, get(PPC::BCC))
296 BuildMI(&MBB, DL, get(PPC::BCC))
298 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
324 BuildMI(MBB, I, DL, MCID, DestReg)
327 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
339 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
347 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11))
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsLongBranch.cpp | 225 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
300 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
319 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
322 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
323 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
330 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
332 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
337 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
341 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR)
[all...] |
| MipsSEInstrInfo.cpp | 107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
128 BuildMI(MBB, I, DL, get(Mips::WRDSP))
133 BuildMI(MBB, I, DL, get(Mips::CTCMSA))
170 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
232 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
235 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
238 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
241 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
247 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
303 BuildMI(MBB, I, DL, get(Opc), DestReg
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiFrameLowering.cpp | 79 BuildMI(*MBB, MI, DL, LII.get(Lanai::ADD_I_LO), Dst)
114 BuildMI(MBB, MBBI, DL, LII.get(Lanai::SW_RI))
123 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::FP)
131 BuildMI(MBB, MBBI, DL, LII.get(Lanai::SUB_I_LO), Lanai::SP)
187 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::SP)
192 BuildMI(MBB, MBBI, DL, LII.get(Lanai::LDW_RI), Lanai::FP)
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
262 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
264 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
268 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
319 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
327 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
331 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
342 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
358 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
363 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg
[all...] |
| LeonPasses.cpp | 91 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
99 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
194 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
199 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
204 BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD))
305 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
310 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
315 BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD))
385 BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
390 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP))
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 67 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
71 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP)
99 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP)
136 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP);
157 BuildMI(MBB, MBBI, DL,
161 BuildMI(MBB, MBBI, DL,
171 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP)
200 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
221 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
249 BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ExpandPseudo.cpp | 112 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
125 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
129 BuildMI(MBB, MBBI, DL,
133 BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
152 BuildMI(MBB, MBBI, DL,
163 BuildMI(MBB, MBBI, DL,
173 MIB = BuildMI(MBB, MBBI, DL,
176 MIB = BuildMI(MBB, MBBI, DL,
184 BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
186 BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 148 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
153 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
239 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
244 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
250 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
260 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
265 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
271 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
289 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
294 BuildMI(MBB, II, dl, TII.get(NewOpcode)
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFrameLowering.cpp | 94 BuildMI(MBB, InsertAddr, DL, TII->get(WebAssembly::CONST_I32), Zero)
99 BuildMI(MBB, InsertStore, DL, TII->get(WebAssembly::STORE_I32), Drop)
144 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), Zero)
150 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::LOAD_I32),
160 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
162 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::SUB_I32),
171 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY),
202 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
207 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), SPReg)
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
156 BuildMI(MBB, MBBI, DL,
160 BuildMI(MBB, MBBI, DL,
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
199 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
|
| /external/llvm/lib/Target/AMDGPU/ |
| SILowerControlFlow.cpp | 207 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
225 BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
231 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP))
243 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
254 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
257 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
264 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
277 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
285 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_B64), Dst)
290 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC
[all...] |
| SIFrameLowering.cpp | 107 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::FLAT_SCR_LO)
114 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
119 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI)
217 BuildMI(MBB, I, DL, SMovB32, ScratchWaveOffsetReg)
235 BuildMI(MBB, I, DL, SMovB64, Rsrc01)
237 BuildMI(MBB, I, DL, SMovB64, Rsrc23)
247 BuildMI(MBB, I, DL, SMovB32, Rsrc0)
251 BuildMI(MBB, I, DL, SMovB32, Rsrc1)
255 BuildMI(MBB, I, DL, SMovB32, Rsrc2)
259 BuildMI(MBB, I, DL, SMovB32, Rsrc3
[all...] |
