1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCInstrInfo.h" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCTargetMachine.h" 19 #include "PPCHazardRecognizers.h" 20 #include "MCTargetDesc/PPCPredicates.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineMemOperand.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/PseudoSourceValue.h" 26 #include "llvm/MC/MCAsmInfo.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/ADT/STLExtras.h" 32 33 #define GET_INSTRINFO_CTOR 34 #include "PPCGenInstrInfo.inc" 35 36 namespace llvm { 37 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 38 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 39 } 40 41 using namespace llvm; 42 43 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 44 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 45 TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 46 47 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 48 /// this target when scheduling the DAG. 49 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer( 50 const TargetMachine *TM, 51 const ScheduleDAG *DAG) const { 52 // Should use subtarget info to pick the right hazard recognizer. For 53 // now, always return a PPC970 recognizer. 54 const TargetInstrInfo *TII = TM->getInstrInfo(); 55 assert(TII && "No InstrInfo?"); 56 return new PPCHazardRecognizer970(*TII); 57 } 58 59 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 60 int &FrameIndex) const { 61 switch (MI->getOpcode()) { 62 default: break; 63 case PPC::LD: 64 case PPC::LWZ: 65 case PPC::LFS: 66 case PPC::LFD: 67 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 68 MI->getOperand(2).isFI()) { 69 FrameIndex = MI->getOperand(2).getIndex(); 70 return MI->getOperand(0).getReg(); 71 } 72 break; 73 } 74 return 0; 75 } 76 77 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 78 int &FrameIndex) const { 79 switch (MI->getOpcode()) { 80 default: break; 81 case PPC::STD: 82 case PPC::STW: 83 case PPC::STFS: 84 case PPC::STFD: 85 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 86 MI->getOperand(2).isFI()) { 87 FrameIndex = MI->getOperand(2).getIndex(); 88 return MI->getOperand(0).getReg(); 89 } 90 break; 91 } 92 return 0; 93 } 94 95 // commuteInstruction - We can commute rlwimi instructions, but only if the 96 // rotate amt is zero. We also have to munge the immediates a bit. 97 MachineInstr * 98 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 99 MachineFunction &MF = *MI->getParent()->getParent(); 100 101 // Normal instructions can be commuted the obvious way. 102 if (MI->getOpcode() != PPC::RLWIMI) 103 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 104 105 // Cannot commute if it has a non-zero rotate count. 106 if (MI->getOperand(3).getImm() != 0) 107 return 0; 108 109 // If we have a zero rotate count, we have: 110 // M = mask(MB,ME) 111 // Op0 = (Op1 & ~M) | (Op2 & M) 112 // Change this to: 113 // M = mask((ME+1)&31, (MB-1)&31) 114 // Op0 = (Op2 & ~M) | (Op1 & M) 115 116 // Swap op1/op2 117 unsigned Reg0 = MI->getOperand(0).getReg(); 118 unsigned Reg1 = MI->getOperand(1).getReg(); 119 unsigned Reg2 = MI->getOperand(2).getReg(); 120 bool Reg1IsKill = MI->getOperand(1).isKill(); 121 bool Reg2IsKill = MI->getOperand(2).isKill(); 122 bool ChangeReg0 = false; 123 // If machine instrs are no longer in two-address forms, update 124 // destination register as well. 125 if (Reg0 == Reg1) { 126 // Must be two address instruction! 127 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 128 "Expecting a two-address instruction!"); 129 Reg2IsKill = false; 130 ChangeReg0 = true; 131 } 132 133 // Masks. 134 unsigned MB = MI->getOperand(4).getImm(); 135 unsigned ME = MI->getOperand(5).getImm(); 136 137 if (NewMI) { 138 // Create a new instruction. 139 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 140 bool Reg0IsDead = MI->getOperand(0).isDead(); 141 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 142 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 143 .addReg(Reg2, getKillRegState(Reg2IsKill)) 144 .addReg(Reg1, getKillRegState(Reg1IsKill)) 145 .addImm((ME+1) & 31) 146 .addImm((MB-1) & 31); 147 } 148 149 if (ChangeReg0) 150 MI->getOperand(0).setReg(Reg2); 151 MI->getOperand(2).setReg(Reg1); 152 MI->getOperand(1).setReg(Reg2); 153 MI->getOperand(2).setIsKill(Reg1IsKill); 154 MI->getOperand(1).setIsKill(Reg2IsKill); 155 156 // Swap the mask around. 157 MI->getOperand(4).setImm((ME+1) & 31); 158 MI->getOperand(5).setImm((MB-1) & 31); 159 return MI; 160 } 161 162 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 163 MachineBasicBlock::iterator MI) const { 164 DebugLoc DL; 165 BuildMI(MBB, MI, DL, get(PPC::NOP)); 166 } 167 168 169 // Branch analysis. 170 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 171 MachineBasicBlock *&FBB, 172 SmallVectorImpl<MachineOperand> &Cond, 173 bool AllowModify) const { 174 // If the block has no terminators, it just falls into the block after it. 175 MachineBasicBlock::iterator I = MBB.end(); 176 if (I == MBB.begin()) 177 return false; 178 --I; 179 while (I->isDebugValue()) { 180 if (I == MBB.begin()) 181 return false; 182 --I; 183 } 184 if (!isUnpredicatedTerminator(I)) 185 return false; 186 187 // Get the last instruction in the block. 188 MachineInstr *LastInst = I; 189 190 // If there is only one terminator instruction, process it. 191 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 192 if (LastInst->getOpcode() == PPC::B) { 193 if (!LastInst->getOperand(0).isMBB()) 194 return true; 195 TBB = LastInst->getOperand(0).getMBB(); 196 return false; 197 } else if (LastInst->getOpcode() == PPC::BCC) { 198 if (!LastInst->getOperand(2).isMBB()) 199 return true; 200 // Block ends with fall-through condbranch. 201 TBB = LastInst->getOperand(2).getMBB(); 202 Cond.push_back(LastInst->getOperand(0)); 203 Cond.push_back(LastInst->getOperand(1)); 204 return false; 205 } 206 // Otherwise, don't know what this is. 207 return true; 208 } 209 210 // Get the instruction before it if it's a terminator. 211 MachineInstr *SecondLastInst = I; 212 213 // If there are three terminators, we don't know what sort of block this is. 214 if (SecondLastInst && I != MBB.begin() && 215 isUnpredicatedTerminator(--I)) 216 return true; 217 218 // If the block ends with PPC::B and PPC:BCC, handle it. 219 if (SecondLastInst->getOpcode() == PPC::BCC && 220 LastInst->getOpcode() == PPC::B) { 221 if (!SecondLastInst->getOperand(2).isMBB() || 222 !LastInst->getOperand(0).isMBB()) 223 return true; 224 TBB = SecondLastInst->getOperand(2).getMBB(); 225 Cond.push_back(SecondLastInst->getOperand(0)); 226 Cond.push_back(SecondLastInst->getOperand(1)); 227 FBB = LastInst->getOperand(0).getMBB(); 228 return false; 229 } 230 231 // If the block ends with two PPC:Bs, handle it. The second one is not 232 // executed, so remove it. 233 if (SecondLastInst->getOpcode() == PPC::B && 234 LastInst->getOpcode() == PPC::B) { 235 if (!SecondLastInst->getOperand(0).isMBB()) 236 return true; 237 TBB = SecondLastInst->getOperand(0).getMBB(); 238 I = LastInst; 239 if (AllowModify) 240 I->eraseFromParent(); 241 return false; 242 } 243 244 // Otherwise, can't handle this. 245 return true; 246 } 247 248 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 249 MachineBasicBlock::iterator I = MBB.end(); 250 if (I == MBB.begin()) return 0; 251 --I; 252 while (I->isDebugValue()) { 253 if (I == MBB.begin()) 254 return 0; 255 --I; 256 } 257 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 258 return 0; 259 260 // Remove the branch. 261 I->eraseFromParent(); 262 263 I = MBB.end(); 264 265 if (I == MBB.begin()) return 1; 266 --I; 267 if (I->getOpcode() != PPC::BCC) 268 return 1; 269 270 // Remove the branch. 271 I->eraseFromParent(); 272 return 2; 273 } 274 275 unsigned 276 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 277 MachineBasicBlock *FBB, 278 const SmallVectorImpl<MachineOperand> &Cond, 279 DebugLoc DL) const { 280 // Shouldn't be a fall through. 281 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 282 assert((Cond.size() == 2 || Cond.size() == 0) && 283 "PPC branch conditions have two components!"); 284 285 // One-way branch. 286 if (FBB == 0) { 287 if (Cond.empty()) // Unconditional branch 288 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 289 else // Conditional branch 290 BuildMI(&MBB, DL, get(PPC::BCC)) 291 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 292 return 1; 293 } 294 295 // Two-way Conditional Branch. 296 BuildMI(&MBB, DL, get(PPC::BCC)) 297 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 298 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 299 return 2; 300 } 301 302 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 303 MachineBasicBlock::iterator I, DebugLoc DL, 304 unsigned DestReg, unsigned SrcReg, 305 bool KillSrc) const { 306 unsigned Opc; 307 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 308 Opc = PPC::OR; 309 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 310 Opc = PPC::OR8; 311 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 312 Opc = PPC::FMR; 313 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 314 Opc = PPC::MCRF; 315 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 316 Opc = PPC::VOR; 317 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 318 Opc = PPC::CROR; 319 else 320 llvm_unreachable("Impossible reg-to-reg copy"); 321 322 const MCInstrDesc &MCID = get(Opc); 323 if (MCID.getNumOperands() == 3) 324 BuildMI(MBB, I, DL, MCID, DestReg) 325 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 326 else 327 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 328 } 329 330 bool 331 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 332 unsigned SrcReg, bool isKill, 333 int FrameIdx, 334 const TargetRegisterClass *RC, 335 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 336 DebugLoc DL; 337 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { 338 if (SrcReg != PPC::LR) { 339 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 340 .addReg(SrcReg, 341 getKillRegState(isKill)), 342 FrameIdx)); 343 } else { 344 // FIXME: this spills LR immediately to memory in one step. To do this, 345 // we use R11, which we know cannot be used in the prolog/epilog. This is 346 // a hack. 347 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 348 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 349 .addReg(PPC::R11, 350 getKillRegState(isKill)), 351 FrameIdx)); 352 } 353 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { 354 if (SrcReg != PPC::LR8) { 355 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 356 .addReg(SrcReg, 357 getKillRegState(isKill)), 358 FrameIdx)); 359 } else { 360 // FIXME: this spills LR immediately to memory in one step. To do this, 361 // we use R11, which we know cannot be used in the prolog/epilog. This is 362 // a hack. 363 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 364 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 365 .addReg(PPC::X11, 366 getKillRegState(isKill)), 367 FrameIdx)); 368 } 369 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { 370 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 371 .addReg(SrcReg, 372 getKillRegState(isKill)), 373 FrameIdx)); 374 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { 375 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 376 .addReg(SrcReg, 377 getKillRegState(isKill)), 378 FrameIdx)); 379 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { 380 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 381 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 382 // FIXME (64-bit): Enable 383 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 384 .addReg(SrcReg, 385 getKillRegState(isKill)), 386 FrameIdx)); 387 return true; 388 } else { 389 // FIXME: We need a scatch reg here. The trouble with using R0 is that 390 // it's possible for the stack frame to be so big the save location is 391 // out of range of immediate offsets, necessitating another register. 392 // We hack this on Darwin by reserving R2. It's probably broken on Linux 393 // at the moment. 394 395 // We need to store the CR in the low 4-bits of the saved value. First, 396 // issue a MFCR to save all of the CRBits. 397 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 398 PPC::R2 : PPC::R0; 399 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg) 400 .addReg(SrcReg, getKillRegState(isKill))); 401 402 // If the saved register wasn't CR0, shift the bits left so that they are 403 // in CR0's slot. 404 if (SrcReg != PPC::CR0) { 405 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4; 406 // rlwinm scratch, scratch, ShiftBits, 0, 31. 407 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 408 .addReg(ScratchReg).addImm(ShiftBits) 409 .addImm(0).addImm(31)); 410 } 411 412 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 413 .addReg(ScratchReg, 414 getKillRegState(isKill)), 415 FrameIdx)); 416 } 417 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { 418 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 419 // backend currently only uses CR1EQ as an individual bit, this should 420 // not cause any bug. If we need other uses of CR bits, the following 421 // code may be invalid. 422 unsigned Reg = 0; 423 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 424 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 425 Reg = PPC::CR0; 426 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 427 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 428 Reg = PPC::CR1; 429 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 430 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 431 Reg = PPC::CR2; 432 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 433 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 434 Reg = PPC::CR3; 435 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 436 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 437 Reg = PPC::CR4; 438 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 439 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 440 Reg = PPC::CR5; 441 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 442 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 443 Reg = PPC::CR6; 444 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 445 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 446 Reg = PPC::CR7; 447 448 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 449 PPC::CRRCRegisterClass, NewMIs); 450 451 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { 452 // We don't have indexed addressing for vector loads. Emit: 453 // R0 = ADDI FI# 454 // STVX VAL, 0, R0 455 // 456 // FIXME: We use R0 here, because it isn't available for RA. 457 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 458 FrameIdx, 0, 0)); 459 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) 460 .addReg(SrcReg, getKillRegState(isKill)) 461 .addReg(PPC::R0) 462 .addReg(PPC::R0)); 463 } else { 464 llvm_unreachable("Unknown regclass!"); 465 } 466 467 return false; 468 } 469 470 void 471 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 472 MachineBasicBlock::iterator MI, 473 unsigned SrcReg, bool isKill, int FrameIdx, 474 const TargetRegisterClass *RC, 475 const TargetRegisterInfo *TRI) const { 476 MachineFunction &MF = *MBB.getParent(); 477 SmallVector<MachineInstr*, 4> NewMIs; 478 479 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) { 480 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 481 FuncInfo->setSpillsCR(); 482 } 483 484 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 485 MBB.insert(MI, NewMIs[i]); 486 487 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 488 MachineMemOperand *MMO = 489 MF.getMachineMemOperand( 490 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 491 MachineMemOperand::MOStore, 492 MFI.getObjectSize(FrameIdx), 493 MFI.getObjectAlignment(FrameIdx)); 494 NewMIs.back()->addMemOperand(MF, MMO); 495 } 496 497 void 498 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 499 unsigned DestReg, int FrameIdx, 500 const TargetRegisterClass *RC, 501 SmallVectorImpl<MachineInstr*> &NewMIs)const{ 502 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { 503 if (DestReg != PPC::LR) { 504 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 505 DestReg), FrameIdx)); 506 } else { 507 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 508 PPC::R11), FrameIdx)); 509 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 510 } 511 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { 512 if (DestReg != PPC::LR8) { 513 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 514 FrameIdx)); 515 } else { 516 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), 517 PPC::R11), FrameIdx)); 518 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11)); 519 } 520 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { 521 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 522 FrameIdx)); 523 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { 524 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 525 FrameIdx)); 526 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { 527 // FIXME: We need a scatch reg here. The trouble with using R0 is that 528 // it's possible for the stack frame to be so big the save location is 529 // out of range of immediate offsets, necessitating another register. 530 // We hack this on Darwin by reserving R2. It's probably broken on Linux 531 // at the moment. 532 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 533 PPC::R2 : PPC::R0; 534 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 535 ScratchReg), FrameIdx)); 536 537 // If the reloaded register isn't CR0, shift the bits right so that they are 538 // in the right CR's slot. 539 if (DestReg != PPC::CR0) { 540 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 541 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 542 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 543 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) 544 .addImm(31)); 545 } 546 547 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg) 548 .addReg(ScratchReg)); 549 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { 550 551 unsigned Reg = 0; 552 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 553 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 554 Reg = PPC::CR0; 555 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 556 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 557 Reg = PPC::CR1; 558 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 559 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 560 Reg = PPC::CR2; 561 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 562 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 563 Reg = PPC::CR3; 564 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 565 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 566 Reg = PPC::CR4; 567 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 568 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 569 Reg = PPC::CR5; 570 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 571 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 572 Reg = PPC::CR6; 573 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 574 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 575 Reg = PPC::CR7; 576 577 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 578 PPC::CRRCRegisterClass, NewMIs); 579 580 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { 581 // We don't have indexed addressing for vector loads. Emit: 582 // R0 = ADDI FI# 583 // Dest = LVX 0, R0 584 // 585 // FIXME: We use R0 here, because it isn't available for RA. 586 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 587 FrameIdx, 0, 0)); 588 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) 589 .addReg(PPC::R0)); 590 } else { 591 llvm_unreachable("Unknown regclass!"); 592 } 593 } 594 595 void 596 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 597 MachineBasicBlock::iterator MI, 598 unsigned DestReg, int FrameIdx, 599 const TargetRegisterClass *RC, 600 const TargetRegisterInfo *TRI) const { 601 MachineFunction &MF = *MBB.getParent(); 602 SmallVector<MachineInstr*, 4> NewMIs; 603 DebugLoc DL; 604 if (MI != MBB.end()) DL = MI->getDebugLoc(); 605 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); 606 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 607 MBB.insert(MI, NewMIs[i]); 608 609 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 610 MachineMemOperand *MMO = 611 MF.getMachineMemOperand( 612 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 613 MachineMemOperand::MOLoad, 614 MFI.getObjectSize(FrameIdx), 615 MFI.getObjectAlignment(FrameIdx)); 616 NewMIs.back()->addMemOperand(MF, MMO); 617 } 618 619 MachineInstr* 620 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 621 int FrameIx, uint64_t Offset, 622 const MDNode *MDPtr, 623 DebugLoc DL) const { 624 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 625 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 626 return &*MIB; 627 } 628 629 bool PPCInstrInfo:: 630 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 631 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 632 // Leave the CR# the same, but invert the condition. 633 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 634 return false; 635 } 636 637 /// GetInstSize - Return the number of bytes of code the specified 638 /// instruction may be. This returns the maximum number of bytes. 639 /// 640 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 641 switch (MI->getOpcode()) { 642 case PPC::INLINEASM: { // Inline Asm: Variable size. 643 const MachineFunction *MF = MI->getParent()->getParent(); 644 const char *AsmStr = MI->getOperand(0).getSymbolName(); 645 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 646 } 647 case PPC::PROLOG_LABEL: 648 case PPC::EH_LABEL: 649 case PPC::GC_LABEL: 650 case PPC::DBG_VALUE: 651 return 0; 652 default: 653 return 4; // PowerPC instructions are all 4 bytes 654 } 655 } 656
