1 /* d30v.h -- Header file for D30V opcode table 2 Copyright (C) 1997-2014 Free Software Foundation, Inc. 3 Written by Martin Hunt (hunt (at) cygnus.com), Cygnus Solutions 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 GDB, GAS, and the GNU binutils are free software; you can redistribute 8 them and/or modify them under the terms of the GNU General Public 9 License as published by the Free Software Foundation; either version 3, 10 or (at your option) any later version. 11 12 GDB, GAS, and the GNU binutils are distributed in the hope that they 13 will be useful, but WITHOUT ANY WARRANTY; without even the implied 14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15 the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING3. If not, write to the Free 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #ifndef D30V_H 23 #define D30V_H 24 25 #define NOP 0x00F00000 26 27 /* Structure to hold information about predefined registers. */ 28 struct pd_reg 29 { 30 char *name; /* name to recognize */ 31 char *pname; /* name to print for this register */ 32 int value; 33 }; 34 35 extern const struct pd_reg pre_defined_registers[]; 36 int reg_name_cnt (void); 37 38 /* the number of control registers */ 39 #define MAX_CONTROL_REG 64 40 41 /* define the format specifiers */ 42 #define FM00 0 43 #define FM01 0x80000000 44 #define FM10 0x8000000000000000LL 45 #define FM11 0x8000000080000000LL 46 47 /* define the opcode classes */ 48 #define BRA 0 49 #define LOGIC 1 50 #define IMEM 2 51 #define IALU1 4 52 #define IALU2 5 53 54 /* define the execution condition codes */ 55 #define ECC_AL 0 /* ALways (default) */ 56 #define ECC_TX 1 /* F0=True, F1=Don't care */ 57 #define ECC_FX 2 /* F0=False, F1=Don't care */ 58 #define ECC_XT 3 /* F0=Don't care, F1=True */ 59 #define ECC_XF 4 /* F0=Don't care, F1=False */ 60 #define ECC_TT 5 /* F0=True, F1=True */ 61 #define ECC_TF 6 /* F0=True, F1=False */ 62 #define ECC_RESERVED 7 /* reserved */ 63 #define ECC_MAX ECC_RESERVED 64 65 extern const char *d30v_ecc_names[]; 66 67 /* condition code table for CMP and CMPU */ 68 extern const char *d30v_cc_names[]; 69 70 /* The opcode table is an array of struct d30v_opcode. */ 71 struct d30v_opcode 72 { 73 /* The opcode name. */ 74 const char *name; 75 76 /* the opcode */ 77 int op1; /* first part, "IALU1" for example */ 78 int op2; /* the rest of the opcode */ 79 80 /* opcode format(s). These numbers correspond to entries */ 81 /* in the d30v_format_table */ 82 unsigned char format[4]; 83 84 #define SHORT_M 1 85 #define SHORT_M2 5 /* for ld2w and st2w */ 86 #define SHORT_A 9 87 #define SHORT_B1 11 88 #define SHORT_B2 12 89 #define SHORT_B2r 13 90 #define SHORT_B3 14 91 #define SHORT_B3r 16 92 #define SHORT_B3b 18 93 #define SHORT_B3br 20 94 #define SHORT_D1r 22 95 #define SHORT_D2 24 96 #define SHORT_D2r 26 97 #define SHORT_D2Br 28 98 #define SHORT_U 30 /* unary SHORT_A. ABS for example */ 99 #define SHORT_F 31 /* SHORT_A with flag registers */ 100 #define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ 101 #define SHORT_T 35 /* for trap instruction */ 102 #define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ 103 #define SHORT_CMP 38 /* special form for CMPcc */ 104 #define SHORT_CMPU 40 /* special form for CMPUcc */ 105 #define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ 106 #define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ 107 #define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ 108 #define SHORT_MODINC 48 109 #define SHORT_MODDEC 49 110 #define SHORT_C1 50 111 #define SHORT_C2 51 112 #define SHORT_UF 52 113 #define SHORT_A2 53 114 #define SHORT_NONE 55 /* no operands */ 115 #define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ 116 #define LONG 57 117 #define LONG_U 58 /* unary LONG */ 118 #define LONG_Ur 59 /* LONG pc-relative */ 119 #define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ 120 #define LONG_M 61 /* Memory long for ldb, stb */ 121 #define LONG_M2 62 /* Memory long for ld2w, st2w */ 122 #define LONG_2 63 /* LONG with 2 operands; jmptnz */ 123 #define LONG_2r 64 /* LONG with 2 operands; bratnz */ 124 #define LONG_2b 65 /* LONG_2 with modifier of 3 */ 125 #define LONG_2br 66 /* LONG_2r with modifier of 3 */ 126 #define LONG_D 67 /* for DJMPI */ 127 #define LONG_Dr 68 /* for DBRAI */ 128 #define LONG_Dbr 69 /* for repeati */ 129 130 /* the execution unit(s) used */ 131 int unit; 132 #define EITHER 0 133 #define IU 1 134 #define MU 2 135 #define EITHER_BUT_PREFER_MU 3 136 137 /* this field is used to decide if two instructions */ 138 /* can be executed in parallel */ 139 long flags_used; 140 long flags_set; 141 #define FLAG_0 (1L<<0) 142 #define FLAG_1 (1L<<1) 143 #define FLAG_2 (1L<<2) 144 #define FLAG_3 (1L<<3) 145 #define FLAG_4 (1L<<4) /* S (saturation) */ 146 #define FLAG_5 (1L<<5) /* V (overflow) */ 147 #define FLAG_6 (1L<<6) /* VA (accumulated overflow) */ 148 #define FLAG_7 (1L<<7) /* C (carry/borrow) */ 149 #define FLAG_SM (1L<<8) /* SM (stack mode) */ 150 #define FLAG_RP (1L<<9) /* RP (repeat enable) */ 151 #define FLAG_CONTROL (1L<<10) /* control registers */ 152 #define FLAG_A0 (1L<<11) /* A0 */ 153 #define FLAG_A1 (1L<<12) /* A1 */ 154 #define FLAG_JMP (1L<<13) /* instruction is a branch */ 155 #define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ 156 #define FLAG_MEM (1L<<15) /* reads/writes memory */ 157 #define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation 158 New meaning: operation cannot be 159 combined in parallel with ADD/SUBppp. */ 160 #define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ 161 #define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ 162 #define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ 163 #define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */ 164 #define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */ 165 #define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7) 166 #define FLAG_C FLAG_7 167 #define FLAG_ALL (FLAG_0 | \ 168 FLAG_1 | \ 169 FLAG_2 | \ 170 FLAG_3 | \ 171 FLAG_4 | \ 172 FLAG_5 | \ 173 FLAG_6 | \ 174 FLAG_7 | \ 175 FLAG_SM | \ 176 FLAG_RP | \ 177 FLAG_CONTROL) 178 179 int reloc_flag; 180 #define RELOC_PCREL 1 181 #define RELOC_ABS 2 182 }; 183 184 extern const struct d30v_opcode d30v_opcode_table[]; 185 extern const int d30v_num_opcodes; 186 187 /* The operands table is an array of struct d30v_operand. */ 188 struct d30v_operand 189 { 190 /* the length of the field */ 191 int length; 192 193 /* The number of significant bits in the operand. */ 194 int bits; 195 196 /* position relative to Ra */ 197 int position; 198 199 /* syntax flags. */ 200 long flags; 201 }; 202 extern const struct d30v_operand d30v_operand_table[]; 203 204 /* Values defined for the flags field of a struct d30v_operand. */ 205 206 /* this is the destination register; it will be modified */ 207 /* this is used by the optimizer */ 208 #define OPERAND_DEST (1) 209 210 /* number or symbol */ 211 #define OPERAND_NUM (2) 212 213 /* address or label */ 214 #define OPERAND_ADDR (4) 215 216 /* register */ 217 #define OPERAND_REG (8) 218 219 /* postincrement + */ 220 #define OPERAND_PLUS (0x10) 221 222 /* postdecrement - */ 223 #define OPERAND_MINUS (0x20) 224 225 /* signed number */ 226 #define OPERAND_SIGNED (0x40) 227 228 /* this operand must be shifted left by 3 */ 229 #define OPERAND_SHIFT (0x80) 230 231 /* flag register */ 232 #define OPERAND_FLAG (0x100) 233 234 /* control register */ 235 #define OPERAND_CONTROL (0x200) 236 237 /* accumulator */ 238 #define OPERAND_ACC (0x400) 239 240 /* @ */ 241 #define OPERAND_ATSIGN (0x800) 242 243 /* @( */ 244 #define OPERAND_ATPAR (0x1000) 245 246 /* predecrement mode '@-sp' */ 247 #define OPERAND_ATMINUS (0x2000) 248 249 /* this operand changes the instruction name */ 250 /* for example, CPMcc, CMPUcc */ 251 #define OPERAND_NAME (0x4000) 252 253 /* fake operand for mvtsys and mvfsys */ 254 #define OPERAND_SPECIAL (0x8000) 255 256 /* let the optimizer know that two registers are affected */ 257 #define OPERAND_2REG (0x10000) 258 259 /* This operand is pc-relative. Note that repeati can have two immediate 260 operands, one of which is pcrel, the other (the IMM6U one) is not. */ 261 #define OPERAND_PCREL (0x20000) 262 263 /* The format table is an array of struct d30v_format. */ 264 struct d30v_format 265 { 266 int form; /* SHORT_A, LONG, etc */ 267 int modifier; /* two bit modifier following opcode */ 268 unsigned char operands[5]; 269 }; 270 extern const struct d30v_format d30v_format_table[]; 271 272 273 /* an instruction is defined by an opcode and a format */ 274 /* for example, "add" has one opcode, but three different */ 275 /* formats, 2 SHORT_A forms and a LONG form. */ 276 struct d30v_insn 277 { 278 struct d30v_opcode *op; /* pointer to an entry in the opcode table */ 279 struct d30v_format *form; /* pointer to an entry in the format table */ 280 int ecc; /* execution condition code */ 281 }; 282 283 /* an expressionS only has one register type, so we fake it */ 284 /* by setting high bits to indicate type */ 285 #define REGISTER_MASK 0xFF 286 287 #endif /* D30V_H */ 288
