1 /* 2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. 3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * Neither the name of ARM nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __PLATFORM_DEF_H__ 33 #define __PLATFORM_DEF_H__ 34 35 #include <arch.h> 36 #include "../hikey_def.h" 37 38 /******************************************************************************* 39 * Platform binary types for linking 40 ******************************************************************************/ 41 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 42 #define PLATFORM_LINKER_ARCH aarch64 43 44 /******************************************************************************* 45 * Generic platform constants 46 ******************************************************************************/ 47 48 /* Size of cacheable stacks */ 49 #define PLATFORM_STACK_SIZE 0x800 50 51 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 52 53 #define LOADER_MEM_NAME "loader_mem" 54 55 #define BOOT_EMMC_NAME "l-loader.bin" 56 57 #define NORMAL_EMMC_NAME "normal emmc" 58 59 /* Trusted Boot Firmware BL2 */ 60 #define BL2_IMAGE_NAME "bl2.bin" 61 62 /* EL3 Runtime Firmware BL3-1 */ 63 #define BL31_IMAGE_NAME "bl31.bin" 64 65 /* SCP Firmware BL3-0 */ 66 #define BL30_IMAGE_NAME "bl30.bin" 67 68 /* Secure Payload BL3-2 (Trusted OS) */ 69 #define BL32_IMAGE_NAME "bl32.bin" 70 71 /* Non-Trusted Firmware BL3-3 */ 72 #define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ 73 74 /* Firmware Image Package */ 75 #define FIP_IMAGE_NAME "fip.bin" 76 77 #define PLATFORM_CACHE_LINE_SIZE 64 78 #define PLATFORM_CLUSTER_COUNT 2 79 #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 80 #define PLATFORM_CORE_COUNT 8 81 #define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ 82 PLATFORM_CORE_COUNT) 83 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 84 85 #define MAX_IO_DEVICES 3 86 #define MAX_IO_HANDLES 4 87 88 /******************************************************************************* 89 * Platform memory map related constants 90 ******************************************************************************/ 91 92 /******************************************************************************* 93 * BL1 is stored in XG2RAM0_HIRQ that is 784KB large. Could we use 8MB size? 94 * The first part is BL1_RAM, and the second part is TZRAM. The name isn't good 95 * enough. We need to update it later. 96 ******************************************************************************/ 97 #define MMC_BASE 0x00000000 98 #define MMC_SIZE 0x80000000 99 #define MMC_LOADER_BASE MMC_BASE /* boot */ 100 #define MMC_BL1_SIZE 0x00200000 101 102 #define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) 103 #define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) 104 #define BL1_XG2RAM0_OFFSET 0x1000 105 106 #define DDR_BASE 0x00000000 107 108 #define MMC_DESC_BASE (DDR_BASE + 0x0080000) 109 #define MMC_DESC_SIZE 0x00080000 110 #define MMC_DATA_BASE (MMC_DESC_BASE + MMC_DESC_SIZE) 111 #define MMC_DATA_SIZE 0x00800000 112 113 /******************************************************************************* 114 * BL1 specific defines. 115 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base 116 * addresses. 117 ******************************************************************************/ 118 #define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) 119 #define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) 120 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ 121 #define BL1_RW_SIZE (BL31_LIMIT - BL1_RW_BASE) 122 #define BL1_RW_LIMIT (BL31_LIMIT) 123 124 /******************************************************************************* 125 * BL2 specific defines. 126 ******************************************************************************/ 127 /* Set it in DDR first. If necessary, we can set them into SRAM again. */ 128 #define BL2_BASE (BL1_RW_BASE + 0x8000) /* 0xf981_8000 */ 129 #define BL2_LIMIT (BL2_BASE + 0x40000) 130 131 /******************************************************************************* 132 * BL3-1 specific defines. 133 ******************************************************************************/ 134 #define BL31_BASE (BL2_LIMIT) /* 0xf985_8000 */ 135 #define BL31_LIMIT (BL31_BASE + 0x40000) 136 137 /******************************************************************************* 138 * BL3-2 specific defines. 139 ******************************************************************************/ 140 141 /* 142 * The TSP can execute either from Trusted SRAM or Trusted DRAM. 143 */ 144 #define BL32_SRAM_BASE BL31_LIMIT 145 #define BL32_SRAM_LIMIT (BL31_LIMIT+0x00080000) /* 512K */ 146 147 #define BL32_DRAM_BASE DRAM_SEC_BASE 148 #define BL32_DRAM_LIMIT (DRAM_SEC_BASE+DRAM_SEC_SIZE) 149 150 #if (PLAT_TSP_LOCATION_ID == PLAT_TRUSTED_SRAM_ID) 151 #define TSP_SEC_MEM_BASE BL32_SRAM_BASE 152 #define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) 153 #define BL32_BASE BL32_SRAM_BASE 154 #define BL32_LIMIT BL32_SRAM_LIMIT 155 #elif (PLAT_TSP_LOCATION_ID == PLAT_TRUSTED_DRAM_ID) 156 #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 157 #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 158 #define BL32_BASE BL32_DRAM_BASE 159 #define BL32_LIMIT BL32_DRAM_LIMIT 160 #else 161 #error "Unsupported PLAT_TSP_LOCATION_ID value" 162 #endif 163 164 /******************************************************************************* 165 * BL3-0 specific defines: 166 * 167 * BL3-0 is loaded for mcu firmware, firstly load it into temperary buffer 168 * into 0x0100_0000; then BL2 will parse the sections and load then into 169 * seperated buffers as needed. 170 * 171 ******************************************************************************/ 172 #define BL30_BASE (DRAM_NS_BASE + 0x01000000) 173 #define BL30_LIMIT (DRAM_NS_BASE + 0x01100000) 174 #define BL30_SIZE (BL30_LIMIT - BL30_BASE) 175 176 /******************************************************************************* 177 * Load address of BL3-3 in the HiKey port 178 ******************************************************************************/ 179 #define NS_IMAGE_OFFSET (DRAM_BASE + 0x35000000) /* 848MB */ 180 181 /******************************************************************************* 182 * Platform specific page table and MMU setup constants 183 ******************************************************************************/ 184 #define ADDR_SPACE_SIZE (1ull << 32) 185 186 #if IMAGE_BL1 || IMAGE_BL32 187 # define MAX_XLAT_TABLES 3 188 #endif 189 190 #if IMAGE_BL2 191 # define MAX_XLAT_TABLES 4 192 #endif 193 194 #if IMAGE_BL31 195 # define MAX_XLAT_TABLES 4 196 #endif 197 198 #define MAX_MMAP_REGIONS 16 199 200 /******************************************************************************* 201 * Declarations and constants to access the mailboxes safely. Each mailbox is 202 * aligned on the biggest cache line size in the platform. This is known only 203 * to the platform as it might have a combination of integrated and external 204 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 205 * line at any cache level. They could belong to different cpus/clusters & 206 * get written while being protected by different locks causing corruption of 207 * a valid mailbox address. 208 ******************************************************************************/ 209 #define CACHE_WRITEBACK_SHIFT 6 210 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 211 212 #endif /* __PLATFORM_DEF_H__ */ 213
