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    Searched refs:VR1 (Results 1 - 4 of 4) sorted by null

  /external/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp 182 // load $vr1, FI + 4
183 // copy hi, $vr1
189 unsigned VR1 = MRI.createVirtualRegister(RC);
198 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
199 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
207 // mfhi $vr1, src
208 // store $vr1, FI + 4
214 unsigned VR1 = MRI.createVirtualRegister(RC);
221 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
222 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize)
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MipsSEISelLowering.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonGenInsert.cpp 201 bool operator() (unsigned VR1, unsigned VR2) const {
202 return operator[](VR1) < operator[](VR2);
277 bool operator() (unsigned VR1, unsigned VR2) const;
293 bool operator() (unsigned VR1, unsigned VR2) const;
303 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const {
313 if (VR1 == VR2)
316 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2);
327 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2];
331 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const {
332 if (VR1 == VR2
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  /toolchain/binutils/binutils-2.25/opcodes/
v850-opc.c 1278 #define VR1 (VECTOR5 + 1)
1281 #define VR2 (VR1 + 1)
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