| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx)
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| ARMBaseInstrInfo.h | 306 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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| MLxExpansionPass.cpp | 233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
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| ARMLoadStoreOptimizer.cpp | 359 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
748 .addReg(Base, getDefRegState(true)) // WB base register
903 .addReg(Base, getDefRegState(true)) // WB base register
906 .addReg(MO.getReg(), (isLd ? getDefRegState(true) :
[all...] |
| Thumb1FrameLowering.cpp | 355 MIB.addReg(Reg, getDefRegState(true));
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| Thumb1RegisterInfo.cpp | 78 .addReg(DestReg, getDefRegState(true), SubIdx)
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| ARMBaseRegisterInfo.cpp | 812 .addReg(DestReg, getDefRegState(true), SubIdx)
[all...] |
| ARMFrameLowering.cpp | 661 MIB.addReg(Regs[i], getDefRegState(true));
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 66 .addReg(DestReg, getDefRegState(true));
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| ARMLoadStoreOptimizer.cpp | 768 MIB.addReg(Base, getDefRegState(true))
785 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
[all...] |
| ThumbRegisterInfo.cpp | 77 .addReg(DestReg, getDefRegState(true), SubIdx)
96 .addReg(DestReg, getDefRegState(true), SubIdx)
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| ARMBaseInstrInfo.h | 411 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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| MLxExpansionPass.cpp | 301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
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| ARMBaseRegisterInfo.cpp | 423 .addReg(DestReg, getDefRegState(true), SubIdx)
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| Thumb1FrameLowering.cpp | 646 MIB.addReg(Reg, getDefRegState(true));
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| ARMFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 81 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
85 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 372 inline unsigned getDefRegState(bool B) {
397 return getDefRegState(RegOp.isDef()) |
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 246 inline unsigned getDefRegState(bool B) {
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| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 204 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiMemAluCombiner.cpp | 260 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true));
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| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 469 unsigned SrcDstRegState = getDefRegState(!IsStore);
477 .addReg(SubReg, getDefRegState(!IsStore))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 368 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FrameLowering.cpp | 166 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
[all...] |
