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      1 //===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "SparcRegisterInfo.h"
     15 #include "Sparc.h"
     16 #include "SparcMachineFunctionInfo.h"
     17 #include "SparcSubtarget.h"
     18 #include "llvm/ADT/BitVector.h"
     19 #include "llvm/ADT/STLExtras.h"
     20 #include "llvm/CodeGen/MachineFrameInfo.h"
     21 #include "llvm/CodeGen/MachineFunction.h"
     22 #include "llvm/CodeGen/MachineInstrBuilder.h"
     23 #include "llvm/IR/Type.h"
     24 #include "llvm/Support/CommandLine.h"
     25 #include "llvm/Support/ErrorHandling.h"
     26 #include "llvm/Target/TargetInstrInfo.h"
     27 
     28 using namespace llvm;
     29 
     30 #define GET_REGINFO_TARGET_DESC
     31 #include "SparcGenRegisterInfo.inc"
     32 
     33 static cl::opt<bool>
     34 ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
     35                     cl::desc("Reserve application registers (%g2-%g4)"));
     36 
     37 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
     38 
     39 const MCPhysReg*
     40 SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
     41   return CSR_SaveList;
     42 }
     43 
     44 const uint32_t *
     45 SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
     46                                         CallingConv::ID CC) const {
     47   return CSR_RegMask;
     48 }
     49 
     50 const uint32_t*
     51 SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
     52   return RTCSR_RegMask;
     53 }
     54 
     55 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     56   BitVector Reserved(getNumRegs());
     57   const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
     58   // FIXME: G1 reserved for now for large imm generation by frame code.
     59   Reserved.set(SP::G1);
     60 
     61   // G1-G4 can be used in applications.
     62   if (ReserveAppRegisters) {
     63     Reserved.set(SP::G2);
     64     Reserved.set(SP::G3);
     65     Reserved.set(SP::G4);
     66   }
     67   // G5 is not reserved in 64 bit mode.
     68   if (!Subtarget.is64Bit())
     69     Reserved.set(SP::G5);
     70 
     71   Reserved.set(SP::O6);
     72   Reserved.set(SP::I6);
     73   Reserved.set(SP::I7);
     74   Reserved.set(SP::G0);
     75   Reserved.set(SP::G6);
     76   Reserved.set(SP::G7);
     77 
     78   // Also reserve the register pair aliases covering the above
     79   // registers, with the same conditions.
     80   Reserved.set(SP::G0_G1);
     81   if (ReserveAppRegisters)
     82     Reserved.set(SP::G2_G3);
     83   if (ReserveAppRegisters || !Subtarget.is64Bit())
     84     Reserved.set(SP::G4_G5);
     85 
     86   Reserved.set(SP::O6_O7);
     87   Reserved.set(SP::I6_I7);
     88   Reserved.set(SP::G6_G7);
     89 
     90   // Unaliased double registers are not available in non-V9 targets.
     91   if (!Subtarget.isV9()) {
     92     for (unsigned n = 0; n != 16; ++n) {
     93       for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
     94         Reserved.set(*AI);
     95     }
     96   }
     97 
     98   return Reserved;
     99 }
    100 
    101 const TargetRegisterClass*
    102 SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
    103                                       unsigned Kind) const {
    104   const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
    105   return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
    106 }
    107 
    108 static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II,
    109                       MachineInstr &MI, const DebugLoc &dl,
    110                       unsigned FIOperandNum, int Offset, unsigned FramePtr) {
    111   // Replace frame index with a frame pointer reference.
    112   if (Offset >= -4096 && Offset <= 4095) {
    113     // If the offset is small enough to fit in the immediate field, directly
    114     // encode it.
    115     MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
    116     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
    117     return;
    118   }
    119 
    120   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
    121 
    122   // FIXME: it would be better to scavenge a register here instead of
    123   // reserving G1 all of the time.
    124   if (Offset >= 0) {
    125     // Emit nonnegaive immediates with sethi + or.
    126     // sethi %hi(Offset), %g1
    127     // add %g1, %fp, %g1
    128     // Insert G1+%lo(offset) into the user.
    129     BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
    130       .addImm(HI22(Offset));
    131 
    132 
    133     // Emit G1 = G1 + I6
    134     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
    135       .addReg(FramePtr);
    136     // Insert: G1+%lo(offset) into the user.
    137     MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
    138     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
    139     return;
    140   }
    141 
    142   // Emit Negative numbers with sethi + xor
    143   // sethi %hix(Offset), %g1
    144   // xor  %g1, %lox(offset), %g1
    145   // add %g1, %fp, %g1
    146   // Insert: G1 + 0 into the user.
    147   BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
    148     .addImm(HIX22(Offset));
    149   BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
    150     .addReg(SP::G1).addImm(LOX10(Offset));
    151 
    152   BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
    153     .addReg(FramePtr);
    154   // Insert: G1+%lo(offset) into the user.
    155   MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
    156   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
    157 }
    158 
    159 
    160 void
    161 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
    162                                        int SPAdj, unsigned FIOperandNum,
    163                                        RegScavenger *RS) const {
    164   assert(SPAdj == 0 && "Unexpected");
    165 
    166   MachineInstr &MI = *II;
    167   DebugLoc dl = MI.getDebugLoc();
    168   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
    169   MachineFunction &MF = *MI.getParent()->getParent();
    170   const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
    171   const SparcFrameLowering *TFI = getFrameLowering(MF);
    172 
    173   unsigned FrameReg;
    174   int Offset;
    175   Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg);
    176 
    177   Offset += MI.getOperand(FIOperandNum + 1).getImm();
    178 
    179   if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
    180     if (MI.getOpcode() == SP::STQFri) {
    181       const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
    182       unsigned SrcReg = MI.getOperand(2).getReg();
    183       unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
    184       unsigned SrcOddReg  = getSubReg(SrcReg, SP::sub_odd64);
    185       MachineInstr *StMI =
    186         BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
    187         .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
    188       replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg);
    189       MI.setDesc(TII.get(SP::STDFri));
    190       MI.getOperand(2).setReg(SrcOddReg);
    191       Offset += 8;
    192     } else if (MI.getOpcode() == SP::LDQFri) {
    193       const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
    194       unsigned DestReg     = MI.getOperand(0).getReg();
    195       unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
    196       unsigned DestOddReg  = getSubReg(DestReg, SP::sub_odd64);
    197       MachineInstr *StMI =
    198         BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
    199         .addReg(FrameReg).addImm(0);
    200       replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg);
    201 
    202       MI.setDesc(TII.get(SP::LDDFri));
    203       MI.getOperand(0).setReg(DestOddReg);
    204       Offset += 8;
    205     }
    206   }
    207 
    208   replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
    209 
    210 }
    211 
    212 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
    213   return SP::I6;
    214 }
    215 
    216 // Sparc has no architectural need for stack realignment support,
    217 // except that LLVM unfortunately currently implements overaligned
    218 // stack objects by depending upon stack realignment support.
    219 // If that ever changes, this can probably be deleted.
    220 bool SparcRegisterInfo::canRealignStack(const MachineFunction &MF) const {
    221   if (!TargetRegisterInfo::canRealignStack(MF))
    222     return false;
    223 
    224   // Sparc always has a fixed frame pointer register, so don't need to
    225   // worry about needing to reserve it. [even if we don't have a frame
    226   // pointer for our frame, it still cannot be used for other things,
    227   // or register window traps will be SADNESS.]
    228 
    229   // If there's a reserved call frame, we can use SP to access locals.
    230   if (getFrameLowering(MF)->hasReservedCallFrame(MF))
    231     return true;
    232 
    233   // Otherwise, we'd need a base pointer, but those aren't implemented
    234   // for SPARC at the moment.
    235 
    236   return false;
    237 }
    238