/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/ |
GicV3.S | 38 mrs x0, scr_el3
40 msr scr_el3, x0
67 mrs x0, scr_el3
69 msr scr_el3, x0
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/device/linaro/bootloader/arm-trusted-firmware/bl31/ |
context_mgmt.c | 136 uint32_t scr_el3; local 153 scr_el3 = read_scr(); 154 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 158 scr_el3 |= SCR_NS_BIT; 161 scr_el3 |= SCR_RW_BIT; 164 scr_el3 |= SCR_ST_BIT; 166 scr_el3 |= get_scr_el3_from_routing_model(security_state); 175 * via SCR_EL3.HCE. 195 scr_el3 |= SCR_HCE_BIT; 200 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 222 uint32_t sctlr_elx, scr_el3, cptr_el2; local 339 uint32_t scr_el3; local [all...] |
interrupt_mgmt.c | 56 * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the 57 * value of the SCR_EL3.IRQ or FIQ bit for each security state. 64 uint32_t scr_el3[2]; member in struct:intr_type_desc 102 * This function returns the cached copy of the SCR_EL3 which contains the 108 uint32_t scr_el3; local 111 scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state]; 112 scr_el3 |= intr_type_descs[INTR_TYPE_S_EL1].scr_el3[security_state]; 113 scr_el3 |= intr_type_descs[INTR_TYPE_EL3].scr_el3[security_state] [all...] |
/device/linaro/bootloader/arm-trusted-firmware/bl31/aarch64/ |
runtime_exceptions.S | 129 mrs x2, scr_el3 401 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there 409 mrs x18, scr_el3 413 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 451 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET 456 msr scr_el3, x18
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crash_reporting.S | 61 .asciz "scr_el3", "sctlr_el3", "cptr_el3", "tcr_el3",\ 280 mrs x8, scr_el3
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/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/ |
boot.S | 63 msr scr_el3, x0
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/device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch64/ |
arch_helpers.h | 198 DEFINE_SYSREG_RW_FUNCS(scr_el3)
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Common/AArch64/ |
ArmLibSupport.S | 186 msr scr_el3, x0 // Secure configuration register EL3
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