| /external/clang/test/Sema/ |
| arm_vfma.c | 6 void func(float32x2_t v2f32, float32x4_t v4f32) {
8 vfmaq_f32(v4f32, v4f32, v4f32);
11 vfmsq_f32(v4f32, v4f32, v4f32);
|
| /external/clang/test/CodeGen/ |
| vectorcall.c | 56 typedef float __attribute__((vector_size(16))) v4f32; typedef
57 struct HVA2 { v4f32 x, y; };
58 struct HVA4 { v4f32 w, x, y, z; };
64 void __vectorcall hva2(struct HVA4 a, struct HVA4 b, v4f32 c) {}
68 void __vectorcall hva3(v4f32 a, v4f32 b, v4f32 c, v4f32 d, v4f32 e, struct HVA2 f) {}
|
| x86_64-arguments.c | 159 typedef float v4f32 __attribute__((__vector_size__(16))); typedef
160 v4f32 f25(v4f32 X) {
183 v4f32 v;
|
| systemz-abi-vector.c | 32 typedef __attribute__((vector_size(16))) float v4f32; typedef
114 v4f32 pass_v4f32(v4f32 arg) { return arg; }
[all...] |
| builtins-mips-msa.c | 14 typedef float v4f32 __attribute__ ((vector_size(16))); typedef
47 v4f32 v4f32_a = (v4f32) {0.5, 1, 2, 3};
48 v4f32 v4f32_b = (v4f32) {1.5, 2, 3, 4};
49 v4f32 v4f32_r;
[all...] |
| /external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/useful-harnesses/ |
| vecoperations.c | 6 typedef float v4f32 __attribute__((ext_vector_type(4))); typedef
54 void print_v4f32(const char *str, v4f32 v) {
101 v4f32 v4f32_shuffle_1(v4f32 a) {
102 v4f32 c2 = a.yzwx;
106 v4f32 v4f32_shuffle_2(v4f32 a) {
107 v4f32 c2 = a.zwxy;
111 v4f32 v4f32_shuffle_3(v4f32 a)
[all...] |
| /prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9.x/include/ |
| msa.h | 47 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
466 extern v4i32 __builtin_msa_fcaf_w(v4f32, v4f32);
468 extern v4i32 __builtin_msa_fcor_w(v4f32, v4f32);
470 extern v4i32 __builtin_msa_fcun_w(v4f32, v4f32);
472 extern v4i32 __builtin_msa_fcune_w(v4f32, v4f32);
474 extern v4i32 __builtin_msa_fcueq_w(v4f32, v4f32)
[all...] |
| /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9.x/include/ |
| msa.h | 47 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
466 extern v4i32 __builtin_msa_fcaf_w(v4f32, v4f32);
468 extern v4i32 __builtin_msa_fcor_w(v4f32, v4f32);
470 extern v4i32 __builtin_msa_fcun_w(v4f32, v4f32);
472 extern v4i32 __builtin_msa_fcune_w(v4f32, v4f32);
474 extern v4i32 __builtin_msa_fcueq_w(v4f32, v4f32)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 85 { ISD::FP_EXTEND, MVT::v4f32, 4 }
129 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
130 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
138 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
139 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
140 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
141 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
142 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
143 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
153 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }
[all...] |
| ARMISelLowering.cpp | 471 addQRTypeForNEON(MVT::v4f32);
480 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
481 // supported for v4f32.
517 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
518 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
519 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
520 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
521 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
522 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
523 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 112 v4f32 = 57, // 4 x f32
252 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
361 case v4f32:
409 case v4f32:
488 case v4f32:
651 if (NumElements == 4) return MVT::v4f32;
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ValueTypes.h | 72 v4f32 = 29, // 4 x f32 enumerator in enum:llvm::MVT::SimpleValueType
207 case v4f32:
230 case v4f32:
276 case v4f32:
364 if (NumElements == 4) return MVT::v4f32;
497 V==MVT::v2i64 || V==MVT::v4f32 || V==MVT::v2f64);
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 432 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
468 // nodes. A v4i32/v4f32 BLENDI generates a single 'blendps'/'blendpd'.
470 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1},
492 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
508 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, // shufps + pshufd
537 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
543 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 },
600 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
611 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
673 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }
[all...] |
| X86ISelLowering.cpp | 635 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
720 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
722 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
723 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
724 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
725 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
726 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
727 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
728 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 216 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
219 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
230 // Complex: to v4f32
231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
233 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
234 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
257 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
260 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
271 // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~
[all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 519 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
520 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
521 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
522 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
524 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
529 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
530 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
533 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
534 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
545 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom)
[all...] |
| PPCTargetTransformInfo.cpp | 369 LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
373 (LT.second == MVT::v4f64 || LT.second == MVT::v4f32);
|
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| ValueTypes.cpp | 137 case MVT::v4f32: return "v4f32";
184 case MVT::v4f32: return VectorType::get(Type::getFloatTy(Context), 4);
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 189 case MVT::v4f32: return "v4f32";
267 case MVT::v4f32: return VectorType::get(Type::getFloatTy(Context), 4);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| AMDILISelLowering.cpp | 61 (int)MVT::v4f32,
89 (int)MVT::v4f32,
505 FLTTY = MVT::v4f32;
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 77 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
78 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
143 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
148 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
162 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
163 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
205 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
214 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand);
266 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
271 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 214 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
287 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
|
