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  /device/google/contexthub/firmware/lib/libc/
memcpy-armv7m.S 101 ands r3, r3, #3
218 ands r3, r0, #3
244 ands r3, r1, #3
  /external/llvm/test/CodeGen/SystemZ/
atomicrmw-and-04.ll 1 ; Test 64-bit atomic ANDs.
5 ; Check ANDs of a variable.
19 ; Check ANDs of 1, which are done using a register. (We could use RISBG
atomicrmw-and-05.ll 1 ; Test 32-bit atomic ANDs, z196 version.
atomicrmw-and-06.ll 1 ; Test 64-bit atomic ANDs, z196 version.
and-03.ll 1 ; Test 64-bit ANDs in which the second operand is variable.
99 ; Check that ANDs of spilled values can use NG rather than NGR.
  /bionic/libc/arch-arm64/generic/bionic/
memmove.S 83 ands tmp1, count, #0x30
123 ands tmp2, src, #15 /* Bytes to reach alignment. */
210 ands tmp1, count, #0x30
251 ands tmp2, tmp2, #15 /* Bytes to reach alignment. */
memcmp.S 61 ands tmp1, src1, #7
80 ands limit, limit, #7
  /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/
clzsi2.S 52 ands r0, r0, #1
ctzsi2.S 44 ands r3, r3, #1
  /external/llvm/test/CodeGen/PowerPC/
rlwimi2.ll 1 ; All of these ands and shifts should be folded into rlwimi's
rlwinm.ll 1 ; All of these ands and shifts should be folded into rlwimi's
  /external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
rlwimi2.ll 1 ; All of these ands and shifts should be folded into rlwimi's
rlwinm.ll 1 ; All of these ands and shifts should be folded into rlwimi's
  /frameworks/native/opengl/libagl/
fixed_asm.S 64 0: ands r0, r0, #0x80000000 /* keep only the sign bit */
  /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm64/
anames.go 20 "ANDS",
  /prebuilts/go/linux-x86/src/cmd/internal/obj/arm64/
anames.go 20 "ANDS",
  /system/core/libcutils/arch-arm/
memset32.S 65 ands r3, r3, #0x1C
  /art/runtime/arch/arm64/
memcmp16_arm64.S 56 ands tmp1, src1, #7
75 ands limit, limit, #7
  /bionic/libc/arch-arm/cortex-a9/bionic/
memset.S 103 ands r3, r3, #3
128 ands r3, r3, #0x1C
  /bionic/libc/arch-arm/krait/bionic/
memcpy_base.S 154 ands r2, r2, #0x3f
167 ands r2, r2, #0x0f
  /external/llvm/test/CodeGen/AArch64/
arm64-fast-isel.ll 95 define void @ands(i32* %addr) {
96 ; CHECK-LABEL: ands:
  /external/llvm/test/MC/ARM/
arm_instructions.s 25 @ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
26 ands r1,r2,r3
  /external/vixl/test/aarch32/config/
cond-rd-rn-operand-rm-a32.json 45 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
cond-rd-rn-operand-rm-shift-amount-1to31-a32.json 36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
cond-rd-rn-operand-rm-shift-amount-1to31-t32.json 40 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2

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