| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
| Omap3530.h | 34 #define PBIASLITEPWRDNZ0 BIT1
|
| Omap3530Gpio.h | 58 #define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1
60 #define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1
84 #define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1
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| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/ |
| PL180Mci.h | 73 #define MCI_POWER_UP BIT1
74 #define MCI_POWER_ON (BIT1 | BIT0)
84 #define MCI_STATUS_CMD_DATACRCFAIL BIT1
134 #define MCI_DATACTL_CARD_TO_CONT BIT1
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| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530.h | 34 #define PBIASLITEPWRDNZ0 BIT1
|
| Omap3530Gpio.h | 58 #define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1
60 #define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1
84 #define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| general_definitions.h | 18 #undef BIT1
54 #define BIT1 0x00000002U
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| ExI.c | 99 MmioOr32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), (UINT32) BIT0+BIT1+BIT2);
101 MmioAnd32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), ~((UINT32) BIT0+BIT1+BIT2)); //clear bit 0,1,2
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeUtil.h | 105 #define SOFT_RESET_CLEAR_INT BIT1
117 #define PHY_RESET_BCR BIT1
149 #define AUTO_NEGOTIATE_ADVERTISE_ALL BIT1
167 #define STOP_TX_CFG BIT1
189 #define START_TX_CFG BIT1
240 #define ALLOC_USE_FIFOS BIT1
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| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/ |
| Fdc.h | 43 #define MSR_DBB BIT1 // Drive B Busy
51 #define CCR_DRC (BIT0 | BIT1) // Data Rate select
105 #define STS0_US1 BIT1 // Unit Select1
120 #define STS1_NW BIT1 // Not Writable
135 #define STS2_BC BIT1 // Bad Cylinder
155 #define STS3_US1 BIT1 // Unit Select1
|
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/ |
| IdeData.h | 114 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1
125 #define BMIS_ERROR BIT1
304 #define IE0 BIT1
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| VirtioNet.h | 45 #define VIRTIO_NET_F_GUEST_CSUM BIT1 // guest to checksum incoming packets
95 #define VIRTIO_NET_S_ANNOUNCE BIT1
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/ |
| I2CLibPei.h | 31 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC1 BIT1 // LPSS I2C #1 Disable
45 #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable
51 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
58 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
67 #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
117 #define I2C_INTR_RX_OVER BIT1
142 #define STAT_TFNF BIT1 // TX FIFO is not full
181 #define I2C_INTR_RX_OVER BIT1
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| I2CAccess.h | 28 #define B_PCH_LPC_ACPI_BASE_EN BIT1 // Enable Bit
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/ |
| SDController.c | 196 if (ErrorCode & BIT1) {
499 }while ((TimeOut2-- > 0) && (Data & BIT1));
630 Data &= ~ (BIT5 | BIT1 | BIT2);
631 Data |= BIT1; // Enable block count always
634 Data |= (BIT5 | BIT1 | BIT2);
636 Data |= (BIT5 | BIT1);
669 Data = (CommandIndex << 8) | BIT1 | BIT4| BIT3;
675 Data = (CommandIndex << 8) | BIT0 | BIT1 | BIT4| BIT3;
686 Data = (CommandIndex << 8) | BIT1;
750 if ((Data & BIT1) == BIT1) {
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/ |
| SP805Watchdog.h | 40 #define SP805_WDOG_CTRL_RESEN BIT1
|
| /device/linaro/bootloader/edk2/DuetPkg/PciBusNoEnumerationDxe/ |
| PciPowerManagement.c | 86 PowerManagementCSR &= ~(BIT8 | BIT1 | BIT0);
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/ |
| UhciReg.h | 50 #define USBPORTSC_CSC BIT1 // Connect Status Change
71 #define USBCMD_HCRESET BIT1 // Host reset
83 #define USBSTS_ERROR BIT1 // Interrupt due to error
95 #define USBTD_BITSTUFF BIT1 // Bit stuff error
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| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Library/PlatformBootManagerLib/ |
| PlatformBootManager.h | 47 #define CONSOLE_IN BIT1
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/ |
| QuarkNcSocId.h | 239 #define SMM_READ_OPEN (BIT1) // SMM Reads OPEN
330 #define B_CFG_STICKY_RW_HMB_VIOLATION BIT1
397 #define B_QNC_SMBUS_DERR (BIT1) // Device Error
497 #define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer
512 #define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer
545 #define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)
568 #define B_QNC_LPC_BIOS_CNTL_BLE (BIT1)
616 #define B_RST_CNT_WARM_RST (BIT1) // Warm reset
654 #define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/ |
| I2CRegs.h | 64 #define I2C_INTR_RX_OVER BIT1
89 #define STAT_TFNF BIT1 // TX FIFO is not full
124 #define I2C_INTR_RX_OVER BIT1
128 #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/ |
| Lan91xDxeHw.h | 76 #define TCR_LOOP BIT1
91 #define EPHSR_SNGLCOL BIT1
106 #define RCR_PRMS BIT1
138 #define CTR_RELOAD BIT1
184 #define IST_TX BIT1
193 #define MGMT_MDI BIT1
256 #define PHYSTS_JABBER BIT1 // Jabber condition detected
|
| /frameworks/base/core/tests/coretests/src/android/graphics/drawable/ |
| IconTest.java | 169 final Bitmap bit1 = ((BitmapDrawable) getContext().getDrawable(R.drawable.landscape)) local
173 bit1.compress(Bitmap.CompressFormat.PNG, 100,
185 if (!equalBitmaps(bit1, test1)) {
186 findBitmapDifferences(bit1, test1);
193 final Bitmap bit1 = ((BitmapDrawable) getContext().getDrawable(R.drawable.landscape)) local
197 bit1.compress(Bitmap.CompressFormat.PNG, 100,
222 if (!equalBitmaps(bit1, test1)) {
223 findBitmapDifferences(bit1, test1);
255 final Icon bit1 = Icon.createWithBitmap(originalbits); local
256 imgs.add(bit1);
[all...] |
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| I2cRegs.h | 50 #define B_I2C_REG_CON_SPEED (BIT2+BIT1) // standard mode (01) or fast mode (10)
53 #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) // Master Target Address bits
69 #define I2C_REG_RAW_INTR_STAT_RX_OVER (BIT1) // Raw Interrupt Status Register RX Overflow signal status.
88 #define B_I2C_REG_TXFLR (BIT3+BIT2+BIT1+BIT0) // Transmit FIFO Level Register bits
90 #define B_I2C_REG_RXFLR (BIT3+BIT2+BIT1+BIT0) // Receive FIFO Level Register bits
|
| /device/linaro/bootloader/edk2/MdePkg/Include/Guid/ |
| Cper.h | 40 #define EFI_ERROR_RECORD_HEADER_TIME_STAMP_VALID BIT1
144 #define EFI_ERROR_SECTION_FRU_STRING_VALID BIT1
151 #define EFI_ERROR_SECTION_FLAGS_CONTAINMENT_WARNING BIT1
227 #define EFI_GENERIC_ERROR_PROC_ISA_VALID BIT1
281 #define EFI_GENERIC_ERROR_PROC_FLAGS_PRECISE_IP BIT1
341 #define EFI_CACHE_CHECK_OPERATION_VALID BIT1
394 #define EFI_TLB_CHECK_OPERATION_VALID BIT1
445 #define EFI_BUS_CHECK_OPERATION_VALID BIT1
520 #define EFI_MS_CHECK_CONTEXT_CORRUPT_VALID BIT1
568 #define EFI_IA32_X64_ERROR_PROC_TARGET_ADDR_VALID BIT1
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsSata.h | 76 #define B_PCH_SATA_COMMAND_MSE BIT1 // Memory Space Enable
95 #define B_PCH_SATA_PI_REGISTER_PNC BIT1 // Primary Mode Native Capable
145 #define B_PCH_SATA_ABAR_TP (BIT2 | BIT1) // Type
165 #define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) // Power State
198 #define B_PCH_SATA_PCS_PORT1_EN BIT1 // Port 1 Enabled
207 #define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 // Port 1 Implemented
|
