| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsELFStreamer.cpp | 26 const MCOperand &Op = Inst.getOperand(OpIndex);
28 if (!Op.isReg())
31 unsigned Reg = Op.getReg();
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelDAGToDAG.cpp | 59 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
98 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
104 OutOps.push_back(Op);
|
| /external/llvm/lib/Transforms/ObjCARC/ |
| DependencyAnalysis.cpp | 59 const Value *Op = *I;
60 if (IsPotentialRetainableObjPtr(Op, *PA.getAA()) &&
61 PA.related(Ptr, Op, DL))
106 const Value *Op = *OI;
107 if (IsPotentialRetainableObjPtr(Op, *PA.getAA()) &&
108 PA.related(Ptr, Op, DL))
115 const Value *Op = GetUnderlyingObjCPtr(SI->getPointerOperand(), DL);
118 return IsPotentialRetainableObjPtr(Op, *PA.getAA()) &&
119 PA.related(Op, Ptr, DL);
125 const Value *Op = *OI
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXISelLowering.h | 44 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
46 virtual SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 413 // 3-op Variable Permute (VPERMT2).
417 // 3-op Variable Permute overwriting the index (VPERMI2).
718 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
746 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
775 void computeKnownBitsForTargetNode(const SDValue Op,
782 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
806 void LowerAsmOperandForConstraint(SDValue Op,
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| Reassociate.cpp | 51 Value *Op;
52 ValueEntry(unsigned R, Value *O) : Rank(R), Op(O) {}
65 << *Ops[0].Op->getType() << '\t';
68 WriteAsOperand(dbgs(), Ops[i].Op, false, M);
118 Instruction *Op = dyn_cast<Instruction>(V);
119 if (!Op || !isa<BinaryOperator>(Op))
122 Value *LHS = Op->getOperand(0), *RHS = Op->getOperand(1);
124 ValueRankMap.erase(Op);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 146 SDValue BitConvertToInteger(SDValue Op);
147 SDValue BitConvertVectorToIntegerVector(SDValue Op);
148 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
170 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
171 void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT,
178 /// GetPromotedInteger - Given a processed operand Op which was promoted to a
180 /// promoted value corresponding to the original type are exactly equal to Op.
184 /// For example, if Op is an i16 and was promoted to an i32, then this method
185 /// returns an i32, the lower 16 bits of which coincide with Op, and the upper
187 SDValue GetPromotedInteger(SDValue Op) {
[all...] |
| TargetLowering.cpp | 638 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
640 switch (Op) {
[all...] |
| LegalizeTypes.cpp | 476 SDValue Op = OrigOp;
478 AnalyzeNewValue(Op); // Op may morph.
480 if (Op.getNode()->getNodeId() == Processed)
485 NewOps.push_back(Op);
486 } else if (Op != OrigOp) {
489 NewOps.push_back(Op);
732 void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
734 TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
738 SDValue &OpEntry = PromotedIntegers[Op];
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 92 SDValue Op(Node, ResNo);
94 VRBaseMap.erase(Op);
95 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
125 SDValue Op = User->getOperand(i);
126 if (Op.getNode() != Node || Op.getResNo() != ResNo)
128 MVT VT = Node->getSimpleValueType(Op.getResNo());
181 SDValue Op(Node, ResNo);
183 VRBaseMap.erase(Op);
184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second
[all...] |
| /development/samples/ApiDemos/src/com/example/android/apis/graphics/ |
| Clipping.java | 75 canvas.clipRect(30, 30, 70, 70, Region.Op.DIFFERENCE);
84 canvas.clipPath(mPath, Region.Op.REPLACE);
91 canvas.clipRect(40, 40, 100, 100, Region.Op.UNION);
98 canvas.clipRect(40, 40, 100, 100, Region.Op.XOR);
105 canvas.clipRect(40, 40, 100, 100, Region.Op.REVERSE_DIFFERENCE);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 78 static MachineOperand earlyUseOperand(MachineOperand Op) {
79 if (Op.isReg())
80 Op.setIsKill(false);
81 return Op;
432 // structure, but VAEND is a no-op.
728 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
735 if (auto *C = dyn_cast<ConstantSDNode>(Op))
737 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
738 Op.getValueType()));
742 if (auto *C = dyn_cast<ConstantSDNode>(Op))
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 60 << *Ops[0].Op->getType() << '\t';
63 Ops[i].Op->printAsOperand(dbgs(), false, M);
259 Neg->setOperand(1, Constant::getNullValue(Ty)); // Drop use of op.
279 /// The existing weight LHS represents the computation X op X op ... op X where
280 /// X occurs LHS times. The combined weight represents X op X op ... op X with
281 /// X occurring LHS + RHS times. If op is "Xor" for example then the combine
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 259 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
280 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
546 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
565 void computeKnownBitsForTargetNode(const SDValue Op,
619 void LowerAsmOperandForConstraint(SDValue Op,
760 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/ |
| value.go | 20 // The operation that computes this value. See op.go.
21 Op Op
54 // OpAddcq int64 1 amd64 op: v = arg[0] + constant
65 if opcodeTable[v.Op].auxType != auxInt8 {
66 v.Fatalf("op %s doesn't have an int8 aux field", v.Op)
72 if opcodeTable[v.Op].auxType != auxInt16 {
73 v.Fatalf("op %s doesn't have an int16 aux field", v.Op)
[all...] |
| rewriteS390X.go | 10 switch v.Op {
[all...] |
| /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/ |
| value.go | 20 // The operation that computes this value. See op.go.
21 Op Op
54 // OpAddcq int64 1 amd64 op: v = arg[0] + constant
65 if opcodeTable[v.Op].auxType != auxInt8 {
66 v.Fatalf("op %s doesn't have an int8 aux field", v.Op)
72 if opcodeTable[v.Op].auxType != auxInt16 {
73 v.Fatalf("op %s doesn't have an int16 aux field", v.Op)
[all...] |
| /external/llvm/lib/IR/ |
| ConstantsContext.h | 42 : ConstantExpr(Ty, Opcode, &Op<0>(), 1) {
43 Op<0>() = C;
60 : ConstantExpr(C1->getType(), Opcode, &Op<0>(), 2) {
61 Op<0>() = C1;
62 Op<1>() = C2;
80 : ConstantExpr(C2->getType(), Instruction::Select, &Op<0>(), 3) {
81 Op<0>() = C1;
82 Op<1>() = C2;
83 Op<2>() = C3;
102 Instruction::ExtractElement, &Op<0>(), 2)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelLowering.h | 98 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| ConstantsContext.h | 40 : ConstantExpr(Ty, Opcode, &Op<0>(), 1) {
41 Op<0>() = C;
57 : ConstantExpr(C1->getType(), Opcode, &Op<0>(), 2) {
58 Op<0>() = C1;
59 Op<1>() = C2;
76 : ConstantExpr(C2->getType(), Instruction::Select, &Op<0>(), 3) {
77 Op<0>() = C1;
78 Op<1>() = C2;
79 Op<2>() = C3;
97 Instruction::ExtractElement, &Op<0>(), 2)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 156 // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP.
201 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
202 switch (Op.getOpcode())
204 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
205 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
206 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
207 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
208 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
209 case ISD::LOAD: return LowerLOAD(Op, DAG);
210 case ISD::STORE: return LowerSTORE(Op, DAG)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 179 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
181 switch (Op.getOpcode()) {
184 case ISD::SRA: return LowerShifts(Op, DAG);
185 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
186 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
187 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
188 case ISD::SETCC: return LowerSETCC(Op, DAG);
189 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
190 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
191 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG)
[all...] |
| /prebuilts/go/darwin-x86/src/regexp/syntax/ |
| simplify.go | 18 switch re.Op {
39 return simplify1(re.Op, re.Flags, sub, re)
45 return &Regexp{Op: OpEmptyMatch}
64 nre := &Regexp{Op: OpConcat}
87 prefix = &Regexp{Op: OpConcat}
98 nre2 := &Regexp{Op: OpConcat}
113 return &Regexp{Op: OpNoMatch}
123 // Regexp{Op: op, Flags: flags, Sub: {sub}}
134 func simplify1(op Op, flags Flags, sub, re *Regexp) *Regexp
[all...] |
