| /external/regex-re2/re2/ |
| prefilter.h | 23 enum Op {
31 explicit Prefilter(Op op);
34 Op op() { return op_; } function in class:re2::Prefilter
69 static Prefilter* AndOr(Op op, Prefilter* a, Prefilter* b);
82 Op op_;
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreISelLowering.h | 87 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/Target/AVR/ |
| AVRISelLowering.h | 77 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
89 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
111 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
118 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/eigen/unsupported/Eigen/src/Skyline/ |
| SkylineUtil.h | 27 #define EIGEN_SKYLINE_INHERIT_ASSIGNMENT_OPERATOR(Derived, Op) \
29 EIGEN_STRONG_INLINE Derived& operator Op(const Eigen::SkylineMatrixBase<OtherDerived>& other) \
31 return Base::operator Op(other.derived()); \
33 EIGEN_STRONG_INLINE Derived& operator Op(const Derived& other) \
35 return Base::operator Op(other); \
38 #define EIGEN_SKYLINE_INHERIT_SCALAR_ASSIGNMENT_OPERATOR(Derived, Op) \
40 EIGEN_STRONG_INLINE Derived& operator Op(const Other& scalar) \
42 return Base::operator Op(scalar); \
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 235 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
248 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
277 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
444 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
475 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
476 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/CodeGen/ |
| MIRPrinter.cpp | 121 void printTargetFlags(const MachineOperand &Op);
122 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
125 void print(const MachineMemOperand &Op);
593 for (const auto *Op : MI.memoperands()) {
596 print(*Op);
690 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
691 if (!Op.getTargetFlags())
694 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
696 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
750 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 272 // isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
273 // be zero. Op is expected to be a target specific node. Used by DAG
278 const SDValue Op,
287 switch (Op.getOpcode()) {
291 Op.getOperand(1),
297 Op.getOperand(0),
317 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const
319 EVT OVT = Op.getValueType();
322 DST = LowerSDIV64(Op, DAG);
324 DST = LowerSDIV32(Op, DAG)
[all...] |
| R600ISelLowering.cpp | 245 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
247 switch (Op.getOpcode()) {
248 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
249 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
250 case ISD::ROTL: return LowerROTL(Op, DAG);
251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
252 case ISD::SETCC: return LowerSETCC(Op, DAG);
254 SDValue Chain = Op.getOperand(0);
256 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue()
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 58 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
342 auto Op = make_unique<SparcOperand>(k_Token);
343 Op->Tok.Data = Str.data();
344 Op->Tok.Length = Str.size();
345 Op->StartLoc = S;
346 Op->EndLoc = S;
347 return Op;
352 auto Op = make_unique<SparcOperand>(k_Register);
353 Op->Reg.RegNum = RegNum;
354 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/ |
| PTXInstPrinter.cpp | 114 const MCOperand &Op = MI->getOperand(OpNo);
115 if (Op.isImm()) {
116 O << Op.getImm();
117 } else if (Op.isFPImm()) {
118 double Imm = Op.getFPImm();
129 assert(Op.isExpr() && "unknown operand kind in printOperand");
130 const MCExpr *Expr = Op.getExpr();
135 O << *Op.getExpr();
152 const MCOperand &Op = MI->getOperand(OpNo);
153 assert (Op.isImm() && "Rounding modes must be immediate values")
[all...] |
| /external/eigen/unsupported/Eigen/CXX11/src/Tensor/ |
| TensorScan.h | 17 template <typename Op, typename XprType>
18 struct traits<TensorScanOp<Op, XprType> >
29 template<typename Op, typename XprType>
30 struct eval<TensorScanOp<Op, XprType>, Eigen::Dense>
32 typedef const TensorScanOp<Op, XprType>& type;
35 template<typename Op, typename XprType>
36 struct nested<TensorScanOp<Op, XprType>, 1,
37 typename eval<TensorScanOp<Op, XprType> >::type>
39 typedef TensorScanOp<Op, XprType> type;
48 template <typename Op, typename XprType
[all...] |
| TensorReduction.h | 24 template<typename Op, typename Dims, typename XprType,template <class> class MakePointer_ >
25 struct traits<TensorReductionOp<Op, Dims, XprType, MakePointer_> >
43 template<typename Op, typename Dims, typename XprType, template <class> class MakePointer_>
44 struct eval<TensorReductionOp<Op, Dims, XprType, MakePointer_>, Eigen::Dense>
46 typedef const TensorReductionOp<Op, Dims, XprType, MakePointer_>& type;
49 template<typename Op, typename Dims, typename XprType, template <class> class MakePointer_>
50 struct nested<TensorReductionOp<Op, Dims, XprType, MakePointer_>, 1, typename eval<TensorReductionOp<Op, Dims, XprType, MakePointer_> >::type>
52 typedef TensorReductionOp<Op, Dims, XprType, MakePointer_> type;
129 template <int DimIndex, typename Self, typename Op>
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 40 // Add pseudo op to model memcpy for struct byval.
236 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
318 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
322 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
347 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
506 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
527 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
528 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
529 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
530 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG
[all...] |
| /external/llvm/include/llvm/Bitcode/ |
| BitstreamWriter.h | 261 /// record. This is a no-op, since the abbrev specifies the literal to use.
263 void EmitAbbreviatedLiteral(const BitCodeAbbrevOp &Op, uintty V) {
264 assert(Op.isLiteral() && "Not a literal");
267 assert(V == Op.getLiteralValue() &&
274 void EmitAbbreviatedField(const BitCodeAbbrevOp &Op, uintty V) {
275 assert(!Op.isLiteral() && "Literals should use EmitAbbreviatedLiteral!");
278 switch (Op.getEncoding()) {
281 if (Op.getEncodingData())
282 Emit((unsigned)V, (unsigned)Op.getEncodingData());
285 if (Op.getEncodingData()
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 58 bool isSrcOp(X86Operand &Op);
62 bool isDstOp(X86Operand &Op);
373 bool X86ATTAsmParser::isSrcOp(X86Operand &Op) {
376 return (Op.isMem() &&
377 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
378 isa<MCConstantExpr>(Op.Mem.Disp) &&
379 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
380 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0)
[all...] |
| /external/skia/src/gpu/ |
| GrDrawOpTest.cpp | 15 #define DRAW_OP_TEST_EXTERN(Op) \
16 extern std::unique_ptr<GrMeshDrawOp> Op##__Test(SkRandom*, GrContext* context);
18 #define DRAW_OP_TEST_ENTRY(Op) Op##__Test
|
| /external/skia/src/gpu/glsl/ |
| GrGLSLBlend.h | 25 const char* dstColor, const char* outColor, SkRegion::Op regionOp);
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86AsmPrinter.h | 70 void printSSECC(const MachineInstr *MI, unsigned Op, raw_ostream &O);
71 void printMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
73 void printLeaMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
76 void printPICLabel(const MachineInstr *MI, unsigned Op, raw_ostream &O);
|
| X86InstrInfo.h | 109 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
110 if (MI->getOperand(Op).isFI()) return true;
111 return Op+4 <= MI->getNumOperands() &&
112 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
113 MI->getOperand(Op+2).isReg() &&
114 (MI->getOperand(Op+3).isImm() ||
115 MI->getOperand(Op+3).isGlobal() ||
116 MI->getOperand(Op+3).isCPI() ||
117 MI->getOperand(Op+3).isJTI())
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 80 const MCOperand &Op = MI->getOperand(OpNo);
81 if (Op.isReg()) {
82 printRegName(O, Op.getReg());
86 if (Op.isImm()) {
87 O << Op.getImm();
91 assert(Op.isExpr() && "unknown operand kind in printOperand");
92 O << *Op.getExpr();
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.h | 285 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
295 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
330 virtual void LowerAsmOperandForConstraint(SDValue Op,
386 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
387 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
388 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
389 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
390 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
391 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
392 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| MCDwarf.h | 240 MCCFIInstruction(OpType Op, MCSymbol *L)
241 : Operation(Op), Label(L) {
242 assert(Op == Remember || Op == Restore);
244 MCCFIInstruction(OpType Op, MCSymbol *L, unsigned Register)
245 : Operation(Op), Label(L), Destination(Register) {
246 assert(Op == SameValue);
252 MCCFIInstruction(OpType Op, MCSymbol *L, const MachineLocation &D,
254 : Operation(Op), Label(L), Destination(D), Source(S) {
255 assert(Op == RelMove)
[all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| DivZeroChecker.cpp | 50 BinaryOperator::Opcode Op = B->getOpcode();
51 if (Op != BO_Div &&
52 Op != BO_Rem &&
53 Op != BO_DivAssign &&
54 Op != BO_RemAssign)
|
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/ |
| loopbce.go | 49 switch b.Control.Op {
61 if ind.Op != OpPhi {
67 if n := ind.Args[0]; n.Op == OpAdd64 && (n.Args[0] == ind || n.Args[1] == ind) {
69 } else if n := ind.Args[1]; n.Op == OpAdd64 && (n.Args[0] == ind || n.Args[1] == ind) {
87 if inc.Op != OpConst64 || inc.AuxInt <= 0 {
122 if w, c := dropAdd64(max); (w.Op == OpStringLen || w.Op == OpSliceLen) && 0 >= c && -c >= 0 {
130 if min.Op == OpConst64 && max.Op == OpConst64 {
141 if min.Op == OpConst64
[all...] |
