| /external/llvm/lib/Target/AMDGPU/ |
| SIInsertWaits.cpp | 320 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_NOP))
412 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
495 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_NOP)).addImm(0);
573 BuildMI(MBB, I, I->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64),
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| SILoadStoreOptimizer.cpp | 235 = BuildMI(*MBB, I, DL, Read2Desc, DestReg)
249 MachineInstr *Copy0 = BuildMI(*MBB, I, DL, CopyDesc)
252 MachineInstr *Copy1 = BuildMI(*MBB, I, DL, CopyDesc)
334 = BuildMI(*MBB, I, DL, Write2Desc)
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| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 157 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
159 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
161 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
171 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
173 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
186 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
188 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
189 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
215 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
[all...] |
| MipsSEISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPeephole.cpp | 113 BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),
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| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyCFGStackify.cpp | 380 BuildMI(*Header, InsertPos, DebugLoc(), TII.get(WebAssembly::BLOCK));
387 BuildMI(MBB, InsertPos, DebugLoc(), TII.get(WebAssembly::END_BLOCK));
425 BuildMI(MBB, InsertPos, DebugLoc(), TII.get(WebAssembly::LOOP));
428 MachineInstr *End = BuildMI(*AfterLoop, AfterLoop->begin(), DebugLoc(),
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| /external/llvm/lib/Target/X86/ |
| X86FixupLEAs.cpp | 120 BuildMI(*MF, MI.getDebugLoc(),
289 BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
379 NewMI = BuildMI(*MF, MI.getDebugLoc(), TII->get(addrr_opcode))
389 NewMI = BuildMI(*MF, MI.getDebugLoc(), TII->get(addri_opcode))
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| X86FixupBWInsts.cpp | 229 BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
264 BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
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| SIAssignInterpRegs.cpp | 130 BuildMI(MF->front(), MF->front().begin(), DebugLoc(),
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 320 BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
321 BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi);
322 BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
327 BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 86 BuildMI(MBB, MBBI, DL, TII.get(Opc), SystemZ::R15D)
130 BuildMI(MBB, MBBI, DL, TII.get(SystemZ::MOV64rr), SystemZ::R11D)
265 BuildMI(MBB, MI, DL, TII.get((LowReg == HighReg ?
330 BuildMI(MBB, MI, DL, TII.get((LowReg == HighReg ?
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 224 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
358 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
451 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
532 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ANDXri), AArch64::SP)
626 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
633 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
[all...] |
| AArch64BranchRelaxation.cpp | 239 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::B)).addMBB(NewBB);
440 MachineInstrBuilder MIB = BuildMI(
450 BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB);
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonEarlyIfConv.cpp | 720 MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, TII->get(COpc))
738 BuildMI(*ToB, At, DL, D)
812 BuildMI(*FP.SplitB, MuxAt, DL, D, MuxR)
873 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, TII->get(Hexagon::J2_jump))
879 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, TII->get(Hexagon::J2_jumpt))
888 MachineInstrBuilder MIB = BuildMI(*FP.SplitB, FP.SplitB->end(), DL, D);
899 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, TII->get(Hexagon::J2_jump))
[all...] |
| HexagonOptAddrMode.cpp | 319 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
329 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
345 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
376 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
385 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
398 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
457 BuildMI(*BB, InsertPt, UseMI->getDebugLoc(), HII->get(NewOpCode));
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| HexagonNewValueJump.cpp | 644 NewMI = BuildMI(*MBB, jmpPos, dl,
655 NewMI = BuildMI(*MBB, jmpPos, dl,
661 NewMI = BuildMI(*MBB, jmpPos, dl,
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| HexagonStoreWidening.cpp | 441 MachineInstr *StI = BuildMI(*MF, DL, StD)
452 MachineInstr *TfrI = BuildMI(*MF, DL, TfrD, VReg)
463 MachineInstr *StI = BuildMI(*MF, DL, StD)
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 114 BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(SP::NOP));
121 BuildMI(MBB, ++J, I->getDebugLoc(),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | 414 BuildMI(BB, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
743 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
745 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB)
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 537 BuildMI(BB, DL, TII.get(BPF::JSGT_rr))
543 BuildMI(BB, DL, TII.get(BPF::JUGT_rr))
549 BuildMI(BB, DL, TII.get(BPF::JSGE_rr))
555 BuildMI(BB, DL, TII.get(BPF::JUGE_rr))
561 BuildMI(BB, DL, TII.get(BPF::JEQ_rr))
567 BuildMI(BB, DL, TII.get(BPF::JNE_rr))
588 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg())
|
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 131 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
149 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
158 BuildMI(MBB, ++J, MI->getDebugLoc(),
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| PHIElimination.cpp | 214 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
230 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
316 BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
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