Home | History | Annotate | Download | only in Mips 
      1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #define DEBUG_TYPE "mips-reg-info"
     15 
     16 #include "Mips.h"
     17 #include "MipsSubtarget.h"
     18 #include "MipsRegisterInfo.h"
     19 #include "MipsMachineFunction.h"
     20 #include "llvm/Constants.h"
     21 #include "llvm/Type.h"
     22 #include "llvm/Function.h"
     23 #include "llvm/CodeGen/ValueTypes.h"
     24 #include "llvm/CodeGen/MachineInstrBuilder.h"
     25 #include "llvm/CodeGen/MachineFunction.h"
     26 #include "llvm/CodeGen/MachineFrameInfo.h"
     27 #include "llvm/Target/TargetFrameLowering.h"
     28 #include "llvm/Target/TargetMachine.h"
     29 #include "llvm/Target/TargetOptions.h"
     30 #include "llvm/Target/TargetInstrInfo.h"
     31 #include "llvm/Support/CommandLine.h"
     32 #include "llvm/Support/Debug.h"
     33 #include "llvm/Support/ErrorHandling.h"
     34 #include "llvm/Support/raw_ostream.h"
     35 #include "llvm/ADT/BitVector.h"
     36 #include "llvm/ADT/STLExtras.h"
     37 #include "llvm/Analysis/DebugInfo.h"
     38 
     39 #define GET_REGINFO_TARGET_DESC
     40 #include "MipsGenRegisterInfo.inc"
     41 
     42 using namespace llvm;
     43 
     44 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
     45                                    const TargetInstrInfo &tii)
     46   : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
     47 
     48 /// getRegisterNumbering - Given the enum value for some register, e.g.
     49 /// Mips::RA, return the number that it corresponds to (e.g. 31).
     50 unsigned MipsRegisterInfo::
     51 getRegisterNumbering(unsigned RegEnum)
     52 {
     53   switch (RegEnum) {
     54   case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64:
     55   case Mips::D0:
     56     return 0;
     57   case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64:
     58     return 1;
     59   case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64:
     60   case Mips::D1:
     61     return 2;
     62   case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64:
     63     return 3;
     64   case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64:
     65   case Mips::D2:
     66     return 4;
     67   case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64:
     68     return 5;
     69   case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64:
     70   case Mips::D3:
     71     return 6;
     72   case Mips::A3: case Mips::A3_64: case Mips::F7: case Mips::D7_64:
     73     return 7;
     74   case Mips::T0: case Mips::T0_64: case Mips::F8: case Mips::D8_64:
     75   case Mips::D4:
     76     return 8;
     77   case Mips::T1: case Mips::T1_64: case Mips::F9: case Mips::D9_64:
     78     return 9;
     79   case Mips::T2: case Mips::T2_64: case Mips::F10: case Mips::D10_64:
     80   case Mips::D5:
     81     return 10;
     82   case Mips::T3: case Mips::T3_64: case Mips::F11: case Mips::D11_64:
     83     return 11;
     84   case Mips::T4: case Mips::T4_64: case Mips::F12: case Mips::D12_64:
     85   case Mips::D6:
     86     return 12;
     87   case Mips::T5: case Mips::T5_64: case Mips::F13: case Mips::D13_64:
     88     return 13;
     89   case Mips::T6: case Mips::T6_64: case Mips::F14: case Mips::D14_64:
     90   case Mips::D7:
     91     return 14;
     92   case Mips::T7: case Mips::T7_64: case Mips::F15: case Mips::D15_64:
     93     return 15;
     94   case Mips::S0: case Mips::S0_64: case Mips::F16: case Mips::D16_64:
     95   case Mips::D8:
     96     return 16;
     97   case Mips::S1: case Mips::S1_64: case Mips::F17: case Mips::D17_64:
     98     return 17;
     99   case Mips::S2: case Mips::S2_64: case Mips::F18: case Mips::D18_64:
    100   case Mips::D9:
    101     return 18;
    102   case Mips::S3: case Mips::S3_64: case Mips::F19: case Mips::D19_64:
    103     return 19;
    104   case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64:
    105   case Mips::D10:
    106     return 20;
    107   case Mips::S5: case Mips::S5_64: case Mips::F21: case Mips::D21_64:
    108     return 21;
    109   case Mips::S6: case Mips::S6_64: case Mips::F22: case Mips::D22_64:
    110   case Mips::D11:
    111     return 22;
    112   case Mips::S7: case Mips::S7_64: case Mips::F23: case Mips::D23_64:
    113     return 23;
    114   case Mips::T8: case Mips::T8_64: case Mips::F24: case Mips::D24_64:
    115   case Mips::D12:
    116     return 24;
    117   case Mips::T9: case Mips::T9_64: case Mips::F25: case Mips::D25_64:
    118     return 25;
    119   case Mips::K0: case Mips::K0_64: case Mips::F26: case Mips::D26_64:
    120   case Mips::D13:
    121     return 26;
    122   case Mips::K1: case Mips::K1_64: case Mips::F27: case Mips::D27_64:
    123     return 27;
    124   case Mips::GP: case Mips::GP_64: case Mips::F28: case Mips::D28_64:
    125   case Mips::D14:
    126     return 28;
    127   case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64:
    128     return 29;
    129   case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64:
    130   case Mips::D15:
    131     return 30;
    132   case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
    133     return 31;
    134   default: llvm_unreachable("Unknown register number!");
    135   }
    136   return 0; // Not reached
    137 }
    138 
    139 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
    140 
    141 //===----------------------------------------------------------------------===//
    142 // Callee Saved Registers methods
    143 //===----------------------------------------------------------------------===//
    144 
    145 /// Mips Callee Saved Registers
    146 const unsigned* MipsRegisterInfo::
    147 getCalleeSavedRegs(const MachineFunction *MF) const
    148 {
    149   // Mips callee-save register range is $16-$23, $f20-$f30
    150   static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
    151     Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26,
    152     Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20,
    153     Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
    154     Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
    155   };
    156 
    157   static const unsigned Mips32CalleeSavedRegs[] = {
    158     Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10,
    159     Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
    160     Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
    161   };
    162 
    163   static const unsigned N32CalleeSavedRegs[] = {
    164     Mips::D31_64, Mips::D29_64, Mips::D27_64, Mips::D25_64, Mips::D23_64,
    165     Mips::D21_64,
    166     Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
    167     Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
    168     Mips::S0_64, 0
    169   };
    170 
    171   static const unsigned N64CalleeSavedRegs[] = {
    172     Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64,
    173     Mips::D26_64, Mips::D25_64, Mips::D24_64,
    174     Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
    175     Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
    176     Mips::S0_64, 0
    177   };
    178 
    179   if (Subtarget.isSingleFloat())
    180     return SingleFloatOnlyCalleeSavedRegs;
    181   else if (!Subtarget.hasMips64())
    182     return Mips32CalleeSavedRegs;
    183   else if (Subtarget.isABI_N32())
    184     return N32CalleeSavedRegs;
    185 
    186   assert(Subtarget.isABI_N64());
    187   return N64CalleeSavedRegs;
    188 }
    189 
    190 BitVector MipsRegisterInfo::
    191 getReservedRegs(const MachineFunction &MF) const {
    192   static const unsigned ReservedCPURegs[] = {
    193     Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
    194     Mips::GP, Mips::SP, Mips::FP, Mips::RA, 0
    195   };
    196 
    197   static const unsigned ReservedCPU64Regs[] = {
    198     Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
    199     Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 0
    200   };
    201 
    202   BitVector Reserved(getNumRegs());
    203   typedef TargetRegisterClass::iterator RegIter;
    204 
    205   for (const unsigned *Reg = ReservedCPURegs; *Reg; ++Reg)
    206     Reserved.set(*Reg);
    207 
    208   if (Subtarget.hasMips64()) {
    209     for (const unsigned *Reg = ReservedCPU64Regs; *Reg; ++Reg)
    210       Reserved.set(*Reg);
    211 
    212     // Reserve all registers in AFGR64.
    213     for (RegIter Reg = Mips::AFGR64RegisterClass->begin();
    214          Reg != Mips::AFGR64RegisterClass->end(); ++Reg)
    215       Reserved.set(*Reg);
    216   }
    217   else {
    218     // Reserve all registers in CPU64Regs & FGR64.
    219     for (RegIter Reg = Mips::CPU64RegsRegisterClass->begin();
    220          Reg != Mips::CPU64RegsRegisterClass->end(); ++Reg)
    221       Reserved.set(*Reg);
    222 
    223     for (RegIter Reg = Mips::FGR64RegisterClass->begin();
    224          Reg != Mips::FGR64RegisterClass->end(); ++Reg)
    225       Reserved.set(*Reg);
    226   }
    227 
    228   return Reserved;
    229 }
    230 
    231 // This function eliminate ADJCALLSTACKDOWN,
    232 // ADJCALLSTACKUP pseudo instructions
    233 void MipsRegisterInfo::
    234 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
    235                               MachineBasicBlock::iterator I) const {
    236   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
    237   MBB.erase(I);
    238 }
    239 
    240 // FrameIndex represent objects inside a abstract stack.
    241 // We must replace FrameIndex with an stack/frame pointer
    242 // direct reference.
    243 void MipsRegisterInfo::
    244 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
    245                     RegScavenger *RS) const {
    246   MachineInstr &MI = *II;
    247   MachineFunction &MF = *MI.getParent()->getParent();
    248   MachineFrameInfo *MFI = MF.getFrameInfo();
    249   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
    250 
    251   unsigned i = 0;
    252   while (!MI.getOperand(i).isFI()) {
    253     ++i;
    254     assert(i < MI.getNumOperands() &&
    255            "Instr doesn't have FrameIndex operand!");
    256   }
    257 
    258   DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
    259         errs() << "<--------->\n" << MI);
    260 
    261   int FrameIndex = MI.getOperand(i).getIndex();
    262   int stackSize  = MF.getFrameInfo()->getStackSize();
    263   int spOffset   = MF.getFrameInfo()->getObjectOffset(FrameIndex);
    264 
    265   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
    266                << "spOffset   : " << spOffset << "\n"
    267                << "stackSize  : " << stackSize << "\n");
    268 
    269   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
    270   int MinCSFI = 0;
    271   int MaxCSFI = -1;
    272 
    273   if (CSI.size()) {
    274     MinCSFI = CSI[0].getFrameIdx();
    275     MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
    276   }
    277 
    278   // The following stack frame objects are always referenced relative to $sp:
    279   //  1. Outgoing arguments.
    280   //  2. Pointer to dynamically allocated stack space.
    281   //  3. Locations for callee-saved registers.
    282   // Everything else is referenced relative to whatever register
    283   // getFrameRegister() returns.
    284   unsigned FrameReg;
    285 
    286   if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
    287       (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
    288     FrameReg = Mips::SP;
    289   else
    290     FrameReg = getFrameRegister(MF);
    291 
    292   // Calculate final offset.
    293   // - There is no need to change the offset if the frame object is one of the
    294   //   following: an outgoing argument, pointer to a dynamically allocated
    295   //   stack space or a $gp restore location,
    296   // - If the frame object is any of the following, its offset must be adjusted
    297   //   by adding the size of the stack:
    298   //   incoming argument, callee-saved register location or local variable.
    299   int Offset;
    300 
    301   if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
    302       MipsFI->isDynAllocFI(FrameIndex))
    303     Offset = spOffset;
    304   else
    305     Offset = spOffset + stackSize;
    306 
    307   Offset    += MI.getOperand(i+1).getImm();
    308 
    309   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
    310 
    311   // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
    312   // field.
    313   if (!MI.isDebugValue() && (Offset >= 0x8000 || Offset < -0x8000)) {
    314     MachineBasicBlock &MBB = *MI.getParent();
    315     DebugLoc DL = II->getDebugLoc();
    316     int ImmHi = (((unsigned)Offset & 0xffff0000) >> 16) +
    317                 ((Offset & 0x8000) != 0);
    318 
    319     // FIXME: change this when mips goes MC".
    320     BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
    321     BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi);
    322     BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
    323                                                        .addReg(Mips::AT);
    324     FrameReg = Mips::AT;
    325     Offset = (short)(Offset & 0xffff);
    326 
    327     BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
    328   }
    329 
    330   MI.getOperand(i).ChangeToRegister(FrameReg, false);
    331   MI.getOperand(i+1).ChangeToImmediate(Offset);
    332 }
    333 
    334 unsigned MipsRegisterInfo::
    335 getFrameRegister(const MachineFunction &MF) const {
    336   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    337 
    338   return TFI->hasFP(MF) ? Mips::FP : Mips::SP;
    339 }
    340 
    341 unsigned MipsRegisterInfo::
    342 getEHExceptionRegister() const {
    343   llvm_unreachable("What is the exception register");
    344   return 0;
    345 }
    346 
    347 unsigned MipsRegisterInfo::
    348 getEHHandlerRegister() const {
    349   llvm_unreachable("What is the exception handler register");
    350   return 0;
    351 }
    352