| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 39 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
68 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
97 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
| Thumb2RegisterInfo.cpp | 48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 97 BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg);
98 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg);
110 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
70 BuildMI(MBB, I, dl, TII.get(Opcode))
136 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
143 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
162 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
178 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
185 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
190 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
226 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
265 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 386 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
390 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
394 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
411 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
416 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
422 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
426 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
436 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
441 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
447 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1
[all...] |
| PPCFastISel.cpp | 444 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
558 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
582 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
683 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
694 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
715 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
789 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
898 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
901 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 39 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
55 BuildMI(MBB, I, DL, get(BPF::STD))
73 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0);
144 BuildMI(&MBB, DL, get(BPF::JMP)).addMBB(TBB);
|
| /external/llvm/lib/Target/Mips/ |
| Mips16FrameLowering.cpp | 61 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
76 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
81 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
99 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
|
| Mips16InstrInfo.cpp | 82 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
104 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
123 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
204 MIB = BuildMI(MBB, I, DL, get(Opc));
247 MIB = BuildMI(MBB, I, DL, get(Opc));
272 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
274 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
276 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
279 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
385 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 134 BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
169 addFrameReference(BuildMI(MBB, MI, DL, get(opc))
204 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
368 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
374 MIB = BuildMI(&MBB, DL, get(SPU::BR));
382 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
388 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
392 MIB = BuildMI(MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
402 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
403 MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 272 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
277 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
296 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
349 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
358 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
420 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
585 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
588 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
593 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
598 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg
[all...] |
| X86FastISel.cpp | 490 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
517 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
641 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, Desc);
675 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
779 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), LoadReg);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 53 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
57 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
80 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
84 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
276 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
282 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
287 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 53 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
57 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
82 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
85 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
278 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
284 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
289 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
|
| MSP430RegisterInfo.cpp | 123 New = BuildMI(MF, Old->getDebugLoc(),
132 New = BuildMI(MF, Old->getDebugLoc(),
151 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
209 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
212 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitDouble.cpp | 552 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc));
607 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first)
610 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second)
616 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
620 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
634 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR)
677 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
679 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
698 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
701 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second
[all...] |
| HexagonCopyToCombine.cpp | 631 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::CONST64_Int_Real),
645 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
652 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
661 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
668 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
677 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
683 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
691 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
698 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
709 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FrameLowering.cpp | 165 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
655 BuildMI(MBB, MBBI, DL,
697 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
704 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
725 BuildMI(MBB, MBBI, DL,
733 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
750 BuildMI(MBB, MBBI, DL,
777 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
834 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 82 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
97 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
112 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
145 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WAITCNT))
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
164 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp)
170 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32))
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
194 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_MOV_F32))
207 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMPX_LE_F32_e32)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 208 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
508 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
543 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
557 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
562 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
566 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
570 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
574 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
594 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
618 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 126 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
138 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
201 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
229 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
240 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
247 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
254 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
272 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
296 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
368 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)
[all...] |
| /external/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.cpp | 185 MachineInstr *New = BuildMI(MBB, std::next(II), dl, TII.get(Opcode), DstReg)
211 BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
213 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
219 BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
225 New = BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiRegisterInfo.cpp | 187 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::MOVHI), Reg)
189 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::OR_I_LO), Reg)
194 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::ADD_I_LO), Reg)
200 BuildMI(*MI.getParent(), II, DL,
237 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 64 BuildMI(MBB, I, DL, get(Op), DestReg)
245 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
247 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
253 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
254 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 298 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
302 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
304 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
307 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
382 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
387 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
391 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
395 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
404 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
409 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)
[all...] |
