| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 382 .addReg(Reg2, getKillRegState(Reg2IsKill))
383 .addReg(Reg1, getKillRegState(Reg1IsKill))
890 getKillRegState(KillSrc);
[all...] |
| PPCRegisterInfo.cpp | 417 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
425 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
442 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
450 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
510 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
597 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
687 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
[all...] |
| PPCFrameLowering.cpp | 854 .addReg(TempReg, getKillRegState(true))
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
135 .addReg(SrcReg, getKillRegState(KillSrc));
176 MIB.addReg(SrcReg, getKillRegState(KillSrc));
247 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
580 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
581 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
591 unsigned KillSrc = getKillRegState(Src.isKill());
|
| Mips16InstrInfo.cpp | 88 MIB.addReg(SrcReg, getKillRegState(KillSrc));
104 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 337 .addReg(SrcReg, getKillRegState(KillSrc))
349 .addReg(SrcReg, getKillRegState(KillSrc));
372 .addReg(SrcReg, getKillRegState(isKill))
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 348 ResultReg).addReg(ZeroReg, getKillRegState(true));
386 .addReg(TmpReg, getKillRegState(true));
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 89 .addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0);
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 345 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
356 .addReg(Base, getKillRegState(BaseKill))
360 | getKillRegState(Regs[i].second));
749 .addReg(Base, getKillRegState(BaseKill))
904 .addReg(Base, getKillRegState(isLd ? BaseKill : false))
907 getKillRegState(MO.isKill())));
938 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
944 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
[all...] |
| ARMBaseInstrInfo.cpp | 635 .addReg(SrcReg, getKillRegState(KillSrc))));
656 MIB.addReg(SrcReg, getKillRegState(KillSrc));
658 MIB.addReg(SrcReg, getKillRegState(KillSrc));
676 .addReg(Src, getKillRegState(KillSrc))
677 .addReg(Src, getKillRegState(KillSrc)));
723 .addReg(SrcReg, getKillRegState(isKill))
727 .addReg(SrcReg, getKillRegState(isKill))
735 .addReg(SrcReg, getKillRegState(isKill))
745 .addReg(SrcReg, getKillRegState(isKill))
749 .addReg(SrcReg, getKillRegState(isKill)
[all...] |
| ARMExpandPseudoInsts.cpp | 578 getKillRegState(MO.isKill()));
[all...] |
| Thumb2InstrInfo.cpp | 116 .addReg(SrcReg, getKillRegState(KillSrc)));
139 .addReg(SrcReg, getKillRegState(isKill))
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 471 SOffsetRegState |= getKillRegState(Scavenged);
473 SrcDstRegState |= getKillRegState(IsKill);
523 unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill);
535 .addReg(SubReg, getKillRegState(IsKill))
555 SuperKillState |= getKillRegState(IsKill);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 378 inline unsigned getKillRegState(bool B) {
399 getKillRegState(RegOp.isKill()) |
|
| /external/llvm/lib/Target/AVR/ |
| AVRInstrInfo.cpp | 60 .addReg(SrcReg, getKillRegState(KillSrc));
133 .addReg(SrcReg, getKillRegState(isKill))
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonStoreWidening.cpp | 442 .addReg(MR.getReg(), getKillRegState(MR.isKill()))
464 .addReg(MR.getReg(), getKillRegState(MR.isKill()))
|
| HexagonCopyToCombine.cpp | 735 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
782 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
831 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
832 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 135 .addReg(SrcReg, getKillRegState(KillSrc));
170 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 65 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 252 inline unsigned getKillRegState(bool B) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 568 getKillRegState(MO.isKill()));
626 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
[all...] |
| ARMBaseInstrInfo.cpp | 695 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
713 MIB.addReg(SrcReg, getKillRegState(KillSrc));
729 .addReg(SrcReg, getKillRegState(KillSrc))));
750 MIB.addReg(SrcReg, getKillRegState(KillSrc));
752 MIB.addReg(SrcReg, getKillRegState(KillSrc));
882 .addReg(SrcReg, getKillRegState(isKill))
886 .addReg(SrcReg, getKillRegState(isKill))
894 .addReg(SrcReg, getKillRegState(isKill))
899 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
910 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 215 .addReg(SrcReg, getKillRegState(KillSrc));
221 .addReg(SrcReg, getKillRegState(KillSrc))
697 .addReg(SrcReg, getKillRegState(KillSrc));
711 .addReg(SrcReg, getKillRegState(isKill)),
829 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
862 .addReg(Src.getReg(), getKillRegState(Src.isKill()),
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.cpp | 46 .addReg(SourceRegister, getKillRegState(KillSource))
64 .addReg(SourceRegister, getKillRegState(IsKill))
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 162 MIB.addReg(SrcReg, getKillRegState(KillSrc));
186 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
|
