| /external/valgrind/VEX/priv/ |
| host_amd64_isel.c | 185 static void addInstr ( ISelEnv* env, AMD64Instr* instr )
331 addInstr(env,
339 addInstr(env,
351 addInstr( env, AMD64Instr_Push(AMD64RMI_Imm( (UInt)uimm64 )) );
354 addInstr( env, AMD64Instr_Imm64(uimm64, tmp) );
355 addInstr( env, AMD64Instr_Push(AMD64RMI_Reg(tmp)) );
552 addInstr (that is, commit to) any instructions until we're
579 addInstr(env, fastinstrs[i]);
602 addInstr(env, mk_iMOVsd_RR( hregAMD64_RSP(), r_vecRetAddr ));
607 addInstr(env, mk_iMOVsd_RR( hregAMD64_RSP(), r_vecRetAddr ))
[all...] |
| host_x86_isel.c | 209 static void addInstr ( ISelEnv* env, X86Instr* instr )
311 addInstr(env,
318 addInstr(env,
352 addInstr(env, X86Instr_Push(X86RMI_Reg(r_vecRetAddr)));
356 addInstr(env, X86Instr_Push(X86RMI_Reg(hregX86_EBP())));
362 addInstr(env, X86Instr_Push(iselIntExpr_RMI(env, arg)));
368 addInstr(env, X86Instr_Push(X86RMI_Reg(rHi)));
369 addInstr(env, X86Instr_Push(X86RMI_Reg(rLo)));
390 addInstr(env, X86Instr_Call( cc, (Addr)cee->addr,
529 addInstr(env, mk_iMOVsd_RR( hregX86_ESP(), r_vecRetAddr ))
[all...] |
| host_s390_isel.c | 174 addInstr(ISelEnv *env, s390_insn *insn)
584 addInstr(env, s390_insn_move(sizeof(ULong), tmpregs[argreg],
611 addInstr(env, s390_insn_move(size, finalreg, tmpregs[i]));
638 addInstr(env, s390_insn_helper_call(cc, target, n_args,
683 addInstr(env, s390_insn_load_immediate(4, mode, 4));
684 addInstr(env, s390_insn_alu(4, S390_ALU_SUB, mode, s390_opnd_reg(ir)));
685 addInstr(env, s390_insn_alu(4, S390_ALU_AND, mode, s390_opnd_imm(3)));
687 addInstr(env, s390_insn_set_fpc_bfprm(4, mode));
761 addInstr(env, s390_insn_move(4, mode, ir));
762 addInstr(env, s390_insn_alu(4, S390_ALU_LSH, mode, s390_opnd_imm(1)))
[all...] |
| host_arm_isel.c | 145 static void addInstr ( ISelEnv* env, ARMInstr* instr )
296 addInstr(env, ARMInstr_Imm32(rTmp, DEFAULT_FPSCR));
297 addInstr(env, ARMInstr_FPSCR(True/*toFPSCR*/, rTmp));
334 addInstr(env, ARMInstr_Shift(ARMsh_SHL, tL, irrm, ARMRI5_I5(1)));
335 addInstr(env, ARMInstr_Shift(ARMsh_SHR, tR, irrm, ARMRI5_I5(1)));
336 addInstr(env, ARMInstr_Alu(ARMalu_AND, tL, tL, ARMRI84_I84(2,0)));
337 addInstr(env, ARMInstr_Alu(ARMalu_AND, tR, tR, ARMRI84_I84(1,0)));
338 addInstr(env, ARMInstr_Alu(ARMalu_OR, t3, tL, ARMRI84_R(tR)));
339 addInstr(env, ARMInstr_Shift(ARMsh_SHL, t3, t3, ARMRI5_I5(22)));
340 addInstr(env, ARMInstr_FPSCR(True/*toFPSCR*/, t3))
[all...] |
| host_mips_isel.c | 160 static void addInstr(ISelEnv * env, MIPSInstr * instr)
198 addInstr(env, MIPSInstr_Alu(Malu_DADD, sp, sp, MIPSRH_Imm(True,
201 addInstr(env, MIPSInstr_Alu(Malu_ADD, sp, sp, MIPSRH_Imm(True,
210 addInstr(env, MIPSInstr_Alu(Malu_DSUB, sp, sp,
213 addInstr(env, MIPSInstr_Alu(Malu_SUB, sp, sp,
290 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, irrm,
292 addInstr(env, MIPSInstr_Alu(Malu_XOR, tmp, irrm, MIPSRH_Reg(tmp)));
293 addInstr(env, MIPSInstr_Alu(Malu_AND, irrm, tmp, MIPSRH_Imm(False, 3)));
295 addInstr(env, MIPSInstr_MfFCSR(fcsr_old));
300 addInstr(env, MIPSInstr_Store(4, am_addr, fcsr_old, mode64))
[all...] |
| host_ppc_isel.c | 333 static void addInstr ( ISelEnv* env, PPCInstr* instr )
527 addInstr(env, PPCInstr_Alu( Palu_ADD, sp, sp,
535 addInstr(env, PPCInstr_Alu( Palu_SUB, sp, sp,
549 addInstr(env, mk_iMOVds_RR(r, StackFramePtr(env->mode64)));
551 addInstr(env, PPCInstr_Alu( Palu_ADD, r, r,
554 addInstr(env,
556 addInstr(env, PPCInstr_Alu(Palu_AND, r,r, PPCRH_Reg(align16)));
578 addInstr(env, PPCInstr_Store( 4, am_addr0, r_srcHi, env->mode64 ));
579 addInstr(env, PPCInstr_Store( 4, am_addr1, r_srcLo, env->mode64 ));
582 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, am_addr0))
[all...] |
| host_arm64_isel.c | 132 static void addInstr ( ISelEnv* env, ARM64Instr* instr )
266 addInstr(env, ARM64Instr_Arith(r, hregARM64_X21(),
282 addInstr(env, ARM64Instr_Logic(dst, src, mask, ARM64lo_AND));
292 addInstr(env, ARM64Instr_Shift(dst, src, n48, ARM64sh_SHL));
293 addInstr(env, ARM64Instr_Shift(dst, dst, n48, ARM64sh_SAR));
303 addInstr(env, ARM64Instr_Shift(dst, src, n48, ARM64sh_SHL));
304 addInstr(env, ARM64Instr_Shift(dst, dst, n48, ARM64sh_SHR));
314 addInstr(env, ARM64Instr_Shift(dst, src, n32, ARM64sh_SHL));
315 addInstr(env, ARM64Instr_Shift(dst, dst, n32, ARM64sh_SAR));
325 addInstr(env, ARM64Instr_Shift(dst, src, n56, ARM64sh_SHL))
[all...] |
| host_tilegx_isel.c | 126 static void addInstr ( ISelEnv * env, TILEGXInstr * instr )
308 addInstr(env, mk_iMOVds_RR(argregs[argreg],
348 addInstr(env, mk_iMOVds_RR(argregs[i], tmpregs[i]));
356 addInstr(env, TILEGXInstr_CallAlways(cc, target, argiregs));
358 addInstr(env, TILEGXInstr_Call(cc, target, argiregs, src));
472 addInstr(env, TILEGXInstr_Load(toUChar(sizeofIRType(ty)),
546 addInstr(env, TILEGXInstr_Alu(aluOp, r_dst, r_srcL, ri_srcR));
603 addInstr(env, TILEGXInstr_Shft(shftOp, False/*64bit shift */,
606 addInstr(env, TILEGXInstr_Shft(shftOp, True /*32bit shift */,
693 addInstr(env, TILEGXInstr_Cmp(syned, size32, dst, r1, r2, cc))
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 18 void MipsAnalyzeImmediate::AddInstr(InstSeqLs &SeqLs, const Inst &I) {
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
45 AddInstr(SeqLs, Inst(SLL, Shamt));
58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
|
| MipsAnalyzeImmediate.h | 32 /// AddInstr - Add I to all instruction sequences in SeqLs.
33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 291 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
307 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
|
| PPCFrameLowering.cpp | 666 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
679 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | [all...] |
