1 //===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file declares the targeting of the RegisterBankInfo class for AArch64. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H 15 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H 16 17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 18 19 namespace llvm { 20 21 class TargetRegisterInfo; 22 23 namespace AArch64 { 24 enum { 25 GPRRegBankID = 0, /// General Purpose Registers: W, X. 26 FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q. 27 CCRRegBankID = 2, /// Conditional register: NZCV. 28 NumRegisterBanks 29 }; 30 } // End AArch64 namespace. 31 32 /// This class provides the information for the target register banks. 33 class AArch64RegisterBankInfo : public RegisterBankInfo { 34 /// See RegisterBankInfo::applyMapping. 35 void applyMappingImpl(const OperandsMapper &OpdMapper) const override; 36 37 public: 38 AArch64RegisterBankInfo(const TargetRegisterInfo &TRI); 39 /// Get the cost of a copy from \p B to \p A, or put differently, 40 /// get the cost of A = COPY B. Since register banks may cover 41 /// different size, \p Size specifies what will be the size in bits 42 /// that will be copied around. 43 /// 44 /// \note Since this is a copy, both registers have the same size. 45 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 46 unsigned Size) const override; 47 48 /// Get a register bank that covers \p RC. 49 /// 50 /// \pre \p RC is a user-defined register class (as opposed as one 51 /// generated by TableGen). 52 /// 53 /// \note The mapping RC -> RegBank could be built while adding the 54 /// coverage for the register banks. However, we do not do it, because, 55 /// at least for now, we only need this information for register classes 56 /// that are used in the description of instruction. In other words, 57 /// there are just a handful of them and we do not want to waste space. 58 /// 59 /// \todo This should be TableGen'ed. 60 const RegisterBank & 61 getRegBankFromRegClass(const TargetRegisterClass &RC) const override; 62 63 /// Get the alternative mappings for \p MI. 64 /// Alternative in the sense different from getInstrMapping. 65 InstructionMappings 66 getInstrAlternativeMappings(const MachineInstr &MI) const override; 67 }; 68 } // End llvm namespace. 69 #endif 70
