1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This is the top level entry point for the PowerPC target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // Get the target-independent interfaces which we are implementing. 15 // 16 include "llvm/Target/Target.td" 17 18 //===----------------------------------------------------------------------===// 19 // PowerPC Subtarget features. 20 // 21 22 //===----------------------------------------------------------------------===// 23 // CPU Directives // 24 //===----------------------------------------------------------------------===// 25 26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; 27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; 28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; 29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; 33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; 34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; 35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; 36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; 37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; 38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", 39 "PPC::DIR_E500mc", "">; 40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", 41 "PPC::DIR_E5500", "">; 42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; 43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; 44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; 45 def DirectivePwr5x 46 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">; 47 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; 48 def DirectivePwr6x 49 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; 50 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; 51 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">; 52 def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">; 53 54 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 55 "Enable 64-bit instructions">; 56 def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 57 "Use software emulation for floating point">; 58 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 59 "Enable 64-bit registers usage for ppc32 [beta]">; 60 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 61 "Use condition-register bits individually">; 62 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 63 "Enable Altivec instructions">; 64 def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 65 "Enable SPE instructions">; 66 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 67 "Enable the MFOCRF instruction">; 68 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 69 "Enable the fsqrt instruction">; 70 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 71 "Enable the fcpsgn instruction">; 72 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 73 "Enable the fre instruction">; 74 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 75 "Enable the fres instruction">; 76 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 77 "Enable the frsqrte instruction">; 78 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 79 "Enable the frsqrtes instruction">; 80 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 81 "Assume higher precision reciprocal estimates">; 82 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 83 "Enable the stfiwx instruction">; 84 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 85 "Enable the lfiwax instruction">; 86 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 87 "Enable the fri[mnpz] instructions">; 88 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 89 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">; 90 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 91 "Enable the isel instruction">; 92 def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 93 "Enable the bpermd instruction">; 94 def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 95 "Enable extended divide instructions">; 96 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 97 "Enable the ldbrx instruction">; 98 def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 99 "Enable the cmpb instruction">; 100 def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 101 "Enable icbt instruction">; 102 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 103 "Enable Book E instructions", 104 [FeatureICBT]>; 105 def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 106 "Has only the msync instruction instead of sync", 107 [FeatureBookE]>; 108 def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 109 "Enable E500/E500mc instructions">; 110 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 111 "Enable PPC 4xx instructions">; 112 def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 113 "Enable PPC 6xx instructions">; 114 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 115 "Enable QPX instructions">; 116 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 117 "Enable VSX instructions", 118 [FeatureAltivec]>; 119 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 120 "Enable POWER8 Altivec instructions", 121 [FeatureAltivec]>; 122 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 123 "Enable POWER8 Crypto instructions", 124 [FeatureP8Altivec]>; 125 def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 126 "Enable POWER8 vector instructions", 127 [FeatureVSX, FeatureP8Altivec]>; 128 def FeatureDirectMove : 129 SubtargetFeature<"direct-move", "HasDirectMove", "true", 130 "Enable Power8 direct move instructions", 131 [FeatureVSX]>; 132 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 133 "HasPartwordAtomics", "true", 134 "Enable l[bh]arx and st[bh]cx.">; 135 def FeatureInvariantFunctionDescriptors : 136 SubtargetFeature<"invariant-function-descriptors", 137 "HasInvariantFunctionDescriptors", "true", 138 "Assume function descriptors are invariant">; 139 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 140 "Enable Hardware Transactional Memory instructions">; 141 def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 142 "Implement mftb using the mfspr instruction">; 143 def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 144 "Target supports add/load integer fusion.">; 145 def FeatureFloat128 : 146 SubtargetFeature<"float128", "HasFloat128", "true", 147 "Enable the __float128 data type for IEEE-754R Binary128.", 148 [FeatureVSX]>; 149 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 150 "POPCNTD_Fast", 151 "Enable the popcnt[dw] instructions">; 152 // Note that for the a2/a2q processor models we should not use popcnt[dw] by 153 // default. These processors do support the instructions, but they're 154 // microcoded, and the software emulation is about twice as fast. 155 def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 156 "POPCNTD_Slow", 157 "Has slow popcnt[dw] instructions">; 158 159 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 160 "Treat vector data stream cache control instructions as deprecated">; 161 162 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 163 "true", 164 "Enable instructions added in ISA 3.0.">; 165 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 166 "Enable POWER9 Altivec instructions", 167 [FeatureISA3_0, FeatureP8Altivec]>; 168 def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 169 "Enable POWER9 vector instructions", 170 [FeatureISA3_0, FeatureP8Vector, 171 FeatureP9Altivec]>; 172 173 // Since new processors generally contain a superset of features of those that 174 // came before them, the idea is to make implementations of new processors 175 // less error prone and easier to read. 176 // Namely: 177 // list<SubtargetFeature> Power8FeatureList = ... 178 // list<SubtargetFeature> FutureProcessorSpecificFeatureList = 179 // [ features that Power8 does not support ] 180 // list<SubtargetFeature> FutureProcessorFeatureList = 181 // !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList) 182 183 // Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as 184 // well as providing a single point of definition if the feature set will be 185 // used elsewhere. 186 def ProcessorFeatures { 187 list<SubtargetFeature> Power7FeatureList = 188 [DirectivePwr7, FeatureAltivec, FeatureVSX, 189 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 190 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 191 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 192 FeatureFPRND, FeatureFPCVT, FeatureISEL, 193 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, 194 Feature64Bit /*, Feature64BitRegs */, 195 FeatureBPERMD, FeatureExtDiv, 196 FeatureMFTB, DeprecatedDST]; 197 list<SubtargetFeature> Power8SpecificFeatures = 198 [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto, 199 FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic, 200 FeatureFusion]; 201 list<SubtargetFeature> Power8FeatureList = 202 !listconcat(Power7FeatureList, Power8SpecificFeatures); 203 list<SubtargetFeature> Power9SpecificFeatures = 204 [FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0]; 205 list<SubtargetFeature> Power9FeatureList = 206 !listconcat(Power8FeatureList, Power9SpecificFeatures); 207 } 208 209 // Note: Future features to add when support is extended to more 210 // recent ISA levels: 211 // 212 // DFP p6, p6x, p7 decimal floating-point instructions 213 // POPCNTB p5 through p7 popcntb and related instructions 214 215 //===----------------------------------------------------------------------===// 216 // Classes used for relation maps. 217 //===----------------------------------------------------------------------===// 218 // RecFormRel - Filter class used to relate non-record-form instructions with 219 // their record-form variants. 220 class RecFormRel; 221 222 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 223 // FMA instruction forms with their corresponding factor-killing forms. 224 class AltVSXFMARel { 225 bit IsVSXFMAAlt = 0; 226 } 227 228 //===----------------------------------------------------------------------===// 229 // Relation Map Definitions. 230 //===----------------------------------------------------------------------===// 231 232 def getRecordFormOpcode : InstrMapping { 233 let FilterClass = "RecFormRel"; 234 // Instructions with the same BaseName and Interpretation64Bit values 235 // form a row. 236 let RowFields = ["BaseName", "Interpretation64Bit"]; 237 // Instructions with the same RC value form a column. 238 let ColFields = ["RC"]; 239 // The key column are the non-record-form instructions. 240 let KeyCol = ["0"]; 241 // Value columns RC=1 242 let ValueCols = [["1"]]; 243 } 244 245 def getNonRecordFormOpcode : InstrMapping { 246 let FilterClass = "RecFormRel"; 247 // Instructions with the same BaseName and Interpretation64Bit values 248 // form a row. 249 let RowFields = ["BaseName", "Interpretation64Bit"]; 250 // Instructions with the same RC value form a column. 251 let ColFields = ["RC"]; 252 // The key column are the record-form instructions. 253 let KeyCol = ["1"]; 254 // Value columns are RC=0 255 let ValueCols = [["0"]]; 256 } 257 258 def getAltVSXFMAOpcode : InstrMapping { 259 let FilterClass = "AltVSXFMARel"; 260 // Instructions with the same BaseName and Interpretation64Bit values 261 // form a row. 262 let RowFields = ["BaseName"]; 263 // Instructions with the same RC value form a column. 264 let ColFields = ["IsVSXFMAAlt"]; 265 // The key column are the (default) addend-killing instructions. 266 let KeyCol = ["0"]; 267 // Value columns IsVSXFMAAlt=1 268 let ValueCols = [["1"]]; 269 } 270 271 //===----------------------------------------------------------------------===// 272 // Register File Description 273 //===----------------------------------------------------------------------===// 274 275 include "PPCRegisterInfo.td" 276 include "PPCSchedule.td" 277 include "PPCInstrInfo.td" 278 279 //===----------------------------------------------------------------------===// 280 // PowerPC processors supported. 281 // 282 283 def : Processor<"generic", G3Itineraries, [Directive32, FeatureMFTB]>; 284 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 285 FeatureFRES, FeatureFRSQRTE, 286 FeatureICBT, FeatureBookE, 287 FeatureMSYNC, FeatureMFTB]>; 288 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 289 FeatureFRES, FeatureFRSQRTE, 290 FeatureICBT, FeatureBookE, 291 FeatureMSYNC, FeatureMFTB]>; 292 def : Processor<"601", G3Itineraries, [Directive601]>; 293 def : Processor<"602", G3Itineraries, [Directive602, 294 FeatureMFTB]>; 295 def : Processor<"603", G3Itineraries, [Directive603, 296 FeatureFRES, FeatureFRSQRTE, 297 FeatureMFTB]>; 298 def : Processor<"603e", G3Itineraries, [Directive603, 299 FeatureFRES, FeatureFRSQRTE, 300 FeatureMFTB]>; 301 def : Processor<"603ev", G3Itineraries, [Directive603, 302 FeatureFRES, FeatureFRSQRTE, 303 FeatureMFTB]>; 304 def : Processor<"604", G3Itineraries, [Directive604, 305 FeatureFRES, FeatureFRSQRTE, 306 FeatureMFTB]>; 307 def : Processor<"604e", G3Itineraries, [Directive604, 308 FeatureFRES, FeatureFRSQRTE, 309 FeatureMFTB]>; 310 def : Processor<"620", G3Itineraries, [Directive620, 311 FeatureFRES, FeatureFRSQRTE, 312 FeatureMFTB]>; 313 def : Processor<"750", G4Itineraries, [Directive750, 314 FeatureFRES, FeatureFRSQRTE, 315 FeatureMFTB]>; 316 def : Processor<"g3", G3Itineraries, [Directive750, 317 FeatureFRES, FeatureFRSQRTE, 318 FeatureMFTB]>; 319 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 320 FeatureFRES, FeatureFRSQRTE, 321 FeatureMFTB]>; 322 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 323 FeatureFRES, FeatureFRSQRTE, 324 FeatureMFTB]>; 325 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 326 FeatureFRES, FeatureFRSQRTE, 327 FeatureMFTB]>; 328 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 329 FeatureFRES, FeatureFRSQRTE, 330 FeatureMFTB]>; 331 332 def : ProcessorModel<"970", G5Model, 333 [Directive970, FeatureAltivec, 334 FeatureMFOCRF, FeatureFSqrt, 335 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 336 Feature64Bit /*, Feature64BitRegs */, 337 FeatureMFTB]>; 338 def : ProcessorModel<"g5", G5Model, 339 [Directive970, FeatureAltivec, 340 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 341 FeatureFRES, FeatureFRSQRTE, 342 Feature64Bit /*, Feature64BitRegs */, 343 FeatureMFTB, DeprecatedDST]>; 344 def : ProcessorModel<"e500mc", PPCE500mcModel, 345 [DirectiveE500mc, 346 FeatureSTFIWX, FeatureICBT, FeatureBookE, 347 FeatureISEL, FeatureMFTB]>; 348 def : ProcessorModel<"e5500", PPCE5500Model, 349 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 350 FeatureSTFIWX, FeatureICBT, FeatureBookE, 351 FeatureISEL, FeatureMFTB]>; 352 def : ProcessorModel<"a2", PPCA2Model, 353 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 354 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 355 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 356 FeatureSTFIWX, FeatureLFIWAX, 357 FeatureFPRND, FeatureFPCVT, FeatureISEL, 358 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 359 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 360 def : ProcessorModel<"a2q", PPCA2Model, 361 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 362 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 363 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 364 FeatureSTFIWX, FeatureLFIWAX, 365 FeatureFPRND, FeatureFPCVT, FeatureISEL, 366 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 367 Feature64Bit /*, Feature64BitRegs */, FeatureQPX, 368 FeatureMFTB]>; 369 def : ProcessorModel<"pwr3", G5Model, 370 [DirectivePwr3, FeatureAltivec, 371 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 372 FeatureSTFIWX, Feature64Bit]>; 373 def : ProcessorModel<"pwr4", G5Model, 374 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 375 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 376 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 377 def : ProcessorModel<"pwr5", G5Model, 378 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 379 FeatureFSqrt, FeatureFRE, FeatureFRES, 380 FeatureFRSQRTE, FeatureFRSQRTES, 381 FeatureSTFIWX, Feature64Bit, 382 FeatureMFTB, DeprecatedDST]>; 383 def : ProcessorModel<"pwr5x", G5Model, 384 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 385 FeatureFSqrt, FeatureFRE, FeatureFRES, 386 FeatureFRSQRTE, FeatureFRSQRTES, 387 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 388 FeatureMFTB, DeprecatedDST]>; 389 def : ProcessorModel<"pwr6", G5Model, 390 [DirectivePwr6, FeatureAltivec, 391 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 392 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 393 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 394 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 395 FeatureMFTB, DeprecatedDST]>; 396 def : ProcessorModel<"pwr6x", G5Model, 397 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 398 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 399 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 400 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 401 FeatureFPRND, Feature64Bit, 402 FeatureMFTB, DeprecatedDST]>; 403 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>; 404 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>; 405 // FIXME: Same as P8 until the POWER9 scheduling info is available 406 def : ProcessorModel<"pwr9", P8Model, ProcessorFeatures.Power9FeatureList>; 407 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>; 408 def : ProcessorModel<"ppc64", G5Model, 409 [Directive64, FeatureAltivec, 410 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 411 FeatureFRSQRTE, FeatureSTFIWX, 412 Feature64Bit /*, Feature64BitRegs */, 413 FeatureMFTB]>; 414 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>; 415 416 //===----------------------------------------------------------------------===// 417 // Calling Conventions 418 //===----------------------------------------------------------------------===// 419 420 include "PPCCallingConv.td" 421 422 def PPCInstrInfo : InstrInfo { 423 let isLittleEndianEncoding = 1; 424 425 // FIXME: Unset this when no longer needed! 426 let decodePositionallyEncodedOperands = 1; 427 428 let noNamedPositionallyEncodedOperands = 1; 429 } 430 431 def PPCAsmParser : AsmParser { 432 let ShouldEmitMatchRegisterName = 0; 433 } 434 435 def PPCAsmParserVariant : AsmParserVariant { 436 int Variant = 0; 437 438 // We do not use hard coded registers in asm strings. However, some 439 // InstAlias definitions use immediate literals. Set RegisterPrefix 440 // so that those are not misinterpreted as registers. 441 string RegisterPrefix = "%"; 442 string BreakCharacters = "."; 443 } 444 445 def PPC : Target { 446 // Information about the instructions. 447 let InstructionSet = PPCInstrInfo; 448 449 let AssemblyParsers = [PPCAsmParser]; 450 let AssemblyParserVariants = [PPCAsmParserVariant]; 451 } 452
