1 /* tc-m32c.c -- Assembler for the Renesas M32C. 2 Copyright (C) 2005-2014 Free Software Foundation, Inc. 3 Contributed by RedHat. 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to 19 the Free Software Foundation, 59 Temple Place - Suite 330, 20 Boston, MA 02111-1307, USA. */ 21 22 #include "as.h" 23 #include "subsegs.h" 24 #include "symcat.h" 25 #include "opcodes/m32c-desc.h" 26 #include "opcodes/m32c-opc.h" 27 #include "cgen.h" 28 #include "elf/common.h" 29 #include "elf/m32c.h" 30 #include "libbfd.h" 31 #include "safe-ctype.h" 32 33 /* Structure to hold all of the different components 34 describing an individual instruction. */ 35 typedef struct 36 { 37 const CGEN_INSN * insn; 38 const CGEN_INSN * orig_insn; 39 CGEN_FIELDS fields; 40 #if CGEN_INT_INSN_P 41 CGEN_INSN_INT buffer [1]; 42 #define INSN_VALUE(buf) (*(buf)) 43 #else 44 unsigned char buffer [CGEN_MAX_INSN_SIZE]; 45 #define INSN_VALUE(buf) (buf) 46 #endif 47 char * addr; 48 fragS * frag; 49 int num_fixups; 50 fixS * fixups [GAS_CGEN_MAX_FIXUPS]; 51 int indices [MAX_OPERAND_INSTANCES]; 52 } 53 m32c_insn; 54 55 #define rl_for(_insn) (CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE (&((_insn).insn->base->attrs))) 56 #define relaxable(_insn) (CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (&((_insn).insn->base->attrs))) 57 58 const char comment_chars[] = ";"; 59 const char line_comment_chars[] = "#"; 60 const char line_separator_chars[] = "|"; 61 const char EXP_CHARS[] = "eE"; 62 const char FLT_CHARS[] = "dD"; 63 64 #define M32C_SHORTOPTS "" 66 const char * md_shortopts = M32C_SHORTOPTS; 67 68 /* assembler options */ 69 #define OPTION_CPU_M16C (OPTION_MD_BASE) 70 #define OPTION_CPU_M32C (OPTION_MD_BASE + 1) 71 #define OPTION_LINKRELAX (OPTION_MD_BASE + 2) 72 #define OPTION_H_TICK_HEX (OPTION_MD_BASE + 3) 73 74 struct option md_longopts[] = 75 { 76 { "m16c", no_argument, NULL, OPTION_CPU_M16C }, 77 { "m32c", no_argument, NULL, OPTION_CPU_M32C }, 78 { "relax", no_argument, NULL, OPTION_LINKRELAX }, 79 { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, 80 {NULL, no_argument, NULL, 0} 81 }; 82 size_t md_longopts_size = sizeof (md_longopts); 83 84 /* Default machine */ 85 86 #define DEFAULT_MACHINE bfd_mach_m16c 87 #define DEFAULT_FLAGS EF_M32C_CPU_M16C 88 89 static unsigned long m32c_mach = bfd_mach_m16c; 90 static int cpu_mach = (1 << MACH_M16C); 91 static int insn_size; 92 static int m32c_relax = 0; 93 94 /* Flags to set in the elf header */ 95 static flagword m32c_flags = DEFAULT_FLAGS; 96 97 static char default_isa = 1 << (7 - ISA_M16C); 98 static CGEN_BITSET m32c_isa = {1, & default_isa}; 99 100 static void 101 set_isa (enum isa_attr isa_num) 102 { 103 cgen_bitset_set (& m32c_isa, isa_num); 104 } 105 106 static void s_bss (int); 107 108 int 109 md_parse_option (int c, char * arg ATTRIBUTE_UNUSED) 110 { 111 switch (c) 112 { 113 case OPTION_CPU_M16C: 114 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M16C; 115 m32c_mach = bfd_mach_m16c; 116 cpu_mach = (1 << MACH_M16C); 117 set_isa (ISA_M16C); 118 break; 119 120 case OPTION_CPU_M32C: 121 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M32C; 122 m32c_mach = bfd_mach_m32c; 123 cpu_mach = (1 << MACH_M32C); 124 set_isa (ISA_M32C); 125 break; 126 127 case OPTION_LINKRELAX: 128 m32c_relax = 1; 129 break; 130 131 case OPTION_H_TICK_HEX: 132 enable_h_tick_hex = 1; 133 break; 134 135 default: 136 return 0; 137 } 138 return 1; 139 } 140 141 void 142 md_show_usage (FILE * stream) 143 { 144 fprintf (stream, _(" M32C specific command line options:\n")); 145 } 146 147 static void 148 s_bss (int ignore ATTRIBUTE_UNUSED) 149 { 150 int temp; 151 152 temp = get_absolute_expression (); 153 subseg_set (bss_section, (subsegT) temp); 154 demand_empty_rest_of_line (); 155 } 156 157 /* The target specific pseudo-ops which we support. */ 158 const pseudo_typeS md_pseudo_table[] = 159 { 160 { "bss", s_bss, 0}, 161 { "3byte", cons, 3 }, 162 { "word", cons, 4 }, 163 { NULL, NULL, 0 } 164 }; 165 166 167 void 169 md_begin (void) 170 { 171 /* Initialize the `cgen' interface. */ 172 173 /* Set the machine number and endian. */ 174 gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach, 175 CGEN_CPU_OPEN_ENDIAN, 176 CGEN_ENDIAN_BIG, 177 CGEN_CPU_OPEN_ISAS, & m32c_isa, 178 CGEN_CPU_OPEN_END); 179 180 m32c_cgen_init_asm (gas_cgen_cpu_desc); 181 182 /* This is a callback from cgen to gas to parse operands. */ 183 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); 184 185 /* Set the ELF flags if desired. */ 186 if (m32c_flags) 187 bfd_set_private_flags (stdoutput, m32c_flags); 188 189 /* Set the machine type */ 190 bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach); 191 192 insn_size = 0; 193 } 194 195 void 196 m32c_md_end (void) 197 { 198 int i, n_nops; 199 200 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) 201 { 202 /* Pad with nops for objdump. */ 203 n_nops = (32 - ((insn_size) % 32)) / 8; 204 for (i = 1; i <= n_nops; i++) 205 md_assemble ("nop"); 206 } 207 } 208 209 void 210 m32c_start_line_hook (void) 211 { 212 #if 0 /* not necessary....handled in the .cpu file */ 213 char *s = input_line_pointer; 214 char *sg; 215 216 for (s = input_line_pointer ; s && s[0] != '\n'; s++) 217 { 218 if (s[0] == ':') 219 { 220 /* Remove :g suffix. Squeeze out blanks. */ 221 if (s[1] == 'g') 222 { 223 for (sg = s - 1; sg && sg >= input_line_pointer; sg--) 224 { 225 sg[2] = sg[0]; 226 } 227 sg[1] = ' '; 228 sg[2] = ' '; 229 input_line_pointer += 2; 230 } 231 } 232 } 233 #endif 234 } 235 236 /* Process [[indirect-operands]] in instruction str. */ 237 238 static bfd_boolean 239 m32c_indirect_operand (char *str) 240 { 241 char *new_str; 242 char *s; 243 char *ns; 244 int ns_len; 245 char *ns_end; 246 enum indirect_type {none, relative, absolute} ; 247 enum indirect_type indirection [3] = { none, none, none }; 248 int brace_n [3] = { 0, 0, 0 }; 249 int operand; 250 251 s = str; 252 operand = 1; 253 for (s = str; *s; s++) 254 { 255 if (s[0] == ',') 256 operand = 2; 257 /* [abs] where abs is not a0 or a1 */ 258 if (s[1] == '[' && ! (s[2] == 'a' && (s[3] == '0' || s[3] == '1')) 259 && (ISBLANK (s[0]) || s[0] == ',')) 260 indirection[operand] = absolute; 261 if (s[0] == ']' && s[1] == ']') 262 indirection[operand] = relative; 263 if (s[0] == '[' && s[1] == '[') 264 indirection[operand] = relative; 265 } 266 267 if (indirection[1] == none && indirection[2] == none) 268 return FALSE; 269 270 operand = 1; 271 ns_len = strlen (str); 272 new_str = (char*) xmalloc (ns_len); 273 ns = new_str; 274 ns_end = ns + ns_len; 275 276 for (s = str; *s; s++) 277 { 278 if (s[0] == ',') 279 operand = 2; 280 281 if (s[0] == '[' && ! brace_n[operand]) 282 { 283 brace_n[operand] += 1; 284 /* Squeeze [[ to [ if this is an indirect operand. */ 285 if (indirection[operand] != none) 286 continue; 287 } 288 289 else if (s[0] == '[' && brace_n[operand]) 290 { 291 brace_n[operand] += 1; 292 } 293 else if (s[0] == ']' && s[1] == ']' && indirection[operand] == relative) 294 { 295 s += 1; /* skip one ]. */ 296 brace_n[operand] -= 2; /* allow for 2 [. */ 297 } 298 else if (s[0] == ']' && indirection[operand] == absolute) 299 { 300 brace_n[operand] -= 1; 301 continue; /* skip closing ]. */ 302 } 303 else if (s[0] == ']') 304 { 305 brace_n[operand] -= 1; 306 } 307 *ns = s[0]; 308 ns += 1; 309 if (ns >= ns_end) 310 return FALSE; 311 if (s[0] == 0) 312 break; 313 } 314 *ns = '\0'; 315 for (operand = 1; operand <= 2; operand++) 316 if (brace_n[operand]) 317 { 318 fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]); 319 } 320 321 if (indirection[1] != none && indirection[2] != none) 322 md_assemble ("src-dest-indirect"); 323 else if (indirection[1] != none) 324 md_assemble ("src-indirect"); 325 else if (indirection[2] != none) 326 md_assemble ("dest-indirect"); 327 328 md_assemble (new_str); 329 free (new_str); 330 return TRUE; 331 } 332 333 void 334 md_assemble (char * str) 335 { 336 static int last_insn_had_delay_slot = 0; 337 m32c_insn insn; 338 char * errmsg; 339 finished_insnS results; 340 int rl_type; 341 342 if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str)) 343 return; 344 345 /* Initialize GAS's cgen interface for a new instruction. */ 346 gas_cgen_init_parse (); 347 348 insn.insn = m32c_cgen_assemble_insn 349 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); 350 351 if (!insn.insn) 352 { 353 as_bad ("%s", errmsg); 354 return; 355 } 356 357 results.num_fixups = 0; 358 /* Doesn't really matter what we pass for RELAX_P here. */ 359 gas_cgen_finish_insn (insn.insn, insn.buffer, 360 CGEN_FIELDS_BITSIZE (& insn.fields), 1, &results); 361 362 last_insn_had_delay_slot 363 = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT); 364 (void) last_insn_had_delay_slot; 365 insn_size = CGEN_INSN_BITSIZE(insn.insn); 366 367 rl_type = rl_for (insn); 368 369 /* We have to mark all the jumps, because we need to adjust them 370 when we delete bytes, but we only need to mark the displacements 371 if they're symbolic - if they're not, we've already picked the 372 shortest opcode by now. The linker, however, will still have to 373 check any operands to see if they're the displacement type, since 374 we don't know (nor record) *which* operands are relaxable. */ 375 if (m32c_relax 376 && rl_type != RL_TYPE_NONE 377 && (rl_type == RL_TYPE_JUMP || results.num_fixups) 378 && !relaxable (insn)) 379 { 380 int reloc = 0; 381 int addend = results.num_fixups + 16 * insn_size/8; 382 383 switch (rl_for (insn)) 384 { 385 case RL_TYPE_JUMP: reloc = BFD_RELOC_M32C_RL_JUMP; break; 386 case RL_TYPE_1ADDR: reloc = BFD_RELOC_M32C_RL_1ADDR; break; 387 case RL_TYPE_2ADDR: reloc = BFD_RELOC_M32C_RL_2ADDR; break; 388 } 389 if (insn.insn->base->num == M32C_INSN_JMP16_S 390 || insn.insn->base->num == M32C_INSN_JMP32_S) 391 addend = 0x10; 392 393 fix_new (results.frag, 394 results.addr - results.frag->fr_literal, 395 0, abs_section_sym, addend, 0, 396 reloc); 397 } 398 } 399 400 /* The syntax in the manual says constants begin with '#'. 401 We just ignore it. */ 402 403 void 404 md_operand (expressionS * exp) 405 { 406 /* In case of a syntax error, escape back to try next syntax combo. */ 407 if (exp->X_op == O_absent) 408 gas_cgen_md_operand (exp); 409 } 410 411 valueT 412 md_section_align (segT segment, valueT size) 413 { 414 int align = bfd_get_section_alignment (stdoutput, segment); 415 return ((size + (1 << align) - 1) & (-1 << align)); 416 } 417 418 symbolS * 419 md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 420 { 421 return 0; 422 } 423 424 const relax_typeS md_relax_table[] = 426 { 427 /* The fields are: 428 1) most positive reach of this state, 429 2) most negative reach of this state, 430 3) how many bytes this mode will have in the variable part of the frag 431 4) which index into the table to try if we can't fit into this one. */ 432 433 /* 0 */ { 0, 0, 0, 0 }, /* unused */ 434 /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */ 435 436 /* 2 */ { 127, -128, 2, 3 }, /* jcnd16_5.b */ 437 /* 3 */ { 32767, -32768, 5, 4 }, /* jcnd16_5.w */ 438 /* 4 */ { 0, 0, 6, 0 }, /* jcnd16_5.a */ 439 440 /* 5 */ { 127, -128, 2, 6 }, /* jcnd16.b */ 441 /* 6 */ { 32767, -32768, 5, 7 }, /* jcnd16.w */ 442 /* 7 */ { 0, 0, 6, 0 }, /* jcnd16.a */ 443 444 /* 8 */ { 8, 1, 1, 9 }, /* jmp16.s */ 445 /* 9 */ { 127, -128, 2, 10 }, /* jmp16.b */ 446 /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */ 447 /* 11 */ { 0, 0, 4, 0 }, /* jmp16.a */ 448 449 /* 12 */ { 127, -128, 2, 13 }, /* jcnd32.b */ 450 /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */ 451 /* 14 */ { 0, 0, 6, 0 }, /* jcnd32.a */ 452 453 /* 15 */ { 8, 1, 1, 16 }, /* jmp32.s */ 454 /* 16 */ { 127, -128, 2, 17 }, /* jmp32.b */ 455 /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */ 456 /* 18 */ { 0, 0, 4, 0 }, /* jmp32.a */ 457 458 /* 19 */ { 32767, -32768, 3, 20 }, /* jsr16.w */ 459 /* 20 */ { 0, 0, 4, 0 }, /* jsr16.a */ 460 /* 21 */ { 32767, -32768, 3, 11 }, /* jsr32.w */ 461 /* 22 */ { 0, 0, 4, 0 }, /* jsr32.a */ 462 463 /* 23 */ { 0, 0, 3, 0 }, /* adjnz pc8 */ 464 /* 24 */ { 0, 0, 4, 0 }, /* adjnz disp8 pc8 */ 465 /* 25 */ { 0, 0, 5, 0 }, /* adjnz disp16 pc8 */ 466 /* 26 */ { 0, 0, 6, 0 } /* adjnz disp24 pc8 */ 467 }; 468 469 enum { 470 M32C_MACRO_JCND16_5_W, 471 M32C_MACRO_JCND16_5_A, 472 M32C_MACRO_JCND16_W, 473 M32C_MACRO_JCND16_A, 474 M32C_MACRO_JCND32_W, 475 M32C_MACRO_JCND32_A, 476 /* the digit is the array index of the pcrel byte */ 477 M32C_MACRO_ADJNZ_2, 478 M32C_MACRO_ADJNZ_3, 479 M32C_MACRO_ADJNZ_4, 480 M32C_MACRO_ADJNZ_5, 481 } M32C_Macros; 482 483 static struct { 484 int insn; 485 int bytes; 486 int insn_for_extern; 487 int pcrel_aim_offset; 488 } subtype_mappings[] = { 489 /* 0 */ { 0, 0, 0, 0 }, 490 /* 1 */ { 0, 0, 0, 0 }, 491 492 /* 2 */ { M32C_INSN_JCND16_5, 2, -M32C_MACRO_JCND16_5_A, 1 }, 493 /* 3 */ { -M32C_MACRO_JCND16_5_W, 5, -M32C_MACRO_JCND16_5_A, 4 }, 494 /* 4 */ { -M32C_MACRO_JCND16_5_A, 6, -M32C_MACRO_JCND16_5_A, 0 }, 495 496 /* 5 */ { M32C_INSN_JCND16, 3, -M32C_MACRO_JCND16_A, 1 }, 497 /* 6 */ { -M32C_MACRO_JCND16_W, 6, -M32C_MACRO_JCND16_A, 4 }, 498 /* 7 */ { -M32C_MACRO_JCND16_A, 7, -M32C_MACRO_JCND16_A, 0 }, 499 500 /* 8 */ { M32C_INSN_JMP16_S, 1, M32C_INSN_JMP16_A, 0 }, 501 /* 9 */ { M32C_INSN_JMP16_B, 2, M32C_INSN_JMP16_A, 1 }, 502 /* 10 */ { M32C_INSN_JMP16_W, 3, M32C_INSN_JMP16_A, 2 }, 503 /* 11 */ { M32C_INSN_JMP16_A, 4, M32C_INSN_JMP16_A, 0 }, 504 505 /* 12 */ { M32C_INSN_JCND32, 2, -M32C_MACRO_JCND32_A, 1 }, 506 /* 13 */ { -M32C_MACRO_JCND32_W, 5, -M32C_MACRO_JCND32_A, 4 }, 507 /* 14 */ { -M32C_MACRO_JCND32_A, 6, -M32C_MACRO_JCND32_A, 0 }, 508 509 /* 15 */ { M32C_INSN_JMP32_S, 1, M32C_INSN_JMP32_A, 0 }, 510 /* 16 */ { M32C_INSN_JMP32_B, 2, M32C_INSN_JMP32_A, 1 }, 511 /* 17 */ { M32C_INSN_JMP32_W, 3, M32C_INSN_JMP32_A, 2 }, 512 /* 18 */ { M32C_INSN_JMP32_A, 4, M32C_INSN_JMP32_A, 0 }, 513 514 /* 19 */ { M32C_INSN_JSR16_W, 3, M32C_INSN_JSR16_A, 2 }, 515 /* 20 */ { M32C_INSN_JSR16_A, 4, M32C_INSN_JSR16_A, 0 }, 516 /* 21 */ { M32C_INSN_JSR32_W, 3, M32C_INSN_JSR32_A, 2 }, 517 /* 22 */ { M32C_INSN_JSR32_A, 4, M32C_INSN_JSR32_A, 0 }, 518 519 /* 23 */ { -M32C_MACRO_ADJNZ_2, 3, -M32C_MACRO_ADJNZ_2, 0 }, 520 /* 24 */ { -M32C_MACRO_ADJNZ_3, 4, -M32C_MACRO_ADJNZ_3, 0 }, 521 /* 25 */ { -M32C_MACRO_ADJNZ_4, 5, -M32C_MACRO_ADJNZ_4, 0 }, 522 /* 26 */ { -M32C_MACRO_ADJNZ_5, 6, -M32C_MACRO_ADJNZ_5, 0 } 523 }; 524 #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0])) 525 526 void 527 m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state) 528 { 529 symbolS *symbolP = fragP->fr_symbol; 530 if (symbolP && !S_IS_DEFINED (symbolP)) 531 *aim = 0; 532 /* Adjust for m32c pcrel not being relative to the next opcode. */ 533 *aim += subtype_mappings[this_state].pcrel_aim_offset; 534 } 535 536 static int 537 insn_to_subtype (int inum, const CGEN_INSN *insn) 538 { 539 unsigned int i; 540 541 if (insn 542 && (strncmp (insn->base->mnemonic, "adjnz", 5) == 0 543 || strncmp (insn->base->mnemonic, "sbjnz", 5) == 0)) 544 { 545 i = 23 + insn->base->bitsize/8 - 3; 546 /*printf("mapping %d used for %s\n", i, insn->base->mnemonic);*/ 547 return i; 548 } 549 550 for (i=0; i<NUM_MAPPINGS; i++) 551 if (inum == subtype_mappings[i].insn) 552 { 553 /*printf("mapping %d used\n", i);*/ 554 return i; 555 } 556 abort (); 557 } 558 559 /* Return an initial guess of the length by which a fragment must grow to 560 hold a branch to reach its destination. 561 Also updates fr_type/fr_subtype as necessary. 562 563 Called just before doing relaxation. 564 Any symbol that is now undefined will not become defined. 565 The guess for fr_var is ACTUALLY the growth beyond fr_fix. 566 Whatever we do to grow fr_fix or fr_var contributes to our returned value. 567 Although it may not be explicit in the frag, pretend fr_var starts with a 568 0 value. */ 569 570 int 571 md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED) 572 { 573 int where = fragP->fr_opcode - fragP->fr_literal; 574 575 if (fragP->fr_subtype == 1) 576 fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num, fragP->fr_cgen.insn); 577 578 if (S_GET_SEGMENT (fragP->fr_symbol) != segment) 579 { 580 int new_insn; 581 582 new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern; 583 fragP->fr_subtype = insn_to_subtype (new_insn, 0); 584 } 585 586 if (fragP->fr_cgen.insn->base 587 && fragP->fr_cgen.insn->base->num 588 != subtype_mappings[fragP->fr_subtype].insn 589 && subtype_mappings[fragP->fr_subtype].insn > 0) 590 { 591 int new_insn= subtype_mappings[fragP->fr_subtype].insn; 592 if (new_insn >= 0) 593 { 594 fragP->fr_cgen.insn = (fragP->fr_cgen.insn 595 - fragP->fr_cgen.insn->base->num 596 + new_insn); 597 } 598 } 599 600 return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where); 601 } 602 603 /* *fragP has been relaxed to its final size, and now needs to have 604 the bytes inside it modified to conform to the new size. 605 606 Called after relaxation is finished. 607 fragP->fr_type == rs_machine_dependent. 608 fragP->fr_subtype is the subtype of what the address relaxed to. */ 609 610 static int 611 target_address_for (fragS *frag) 612 { 613 int rv = frag->fr_offset; 614 symbolS *sym = frag->fr_symbol; 615 616 if (sym) 617 rv += S_GET_VALUE (sym); 618 619 /*printf("target_address_for returns %d\n", rv);*/ 620 return rv; 621 } 622 623 void 624 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, 625 segT sec ATTRIBUTE_UNUSED, 626 fragS * fragP ATTRIBUTE_UNUSED) 627 { 628 int addend; 629 int operand; 630 int where = fragP->fr_opcode - fragP->fr_literal; 631 int rl_where = fragP->fr_opcode - fragP->fr_literal; 632 unsigned char *op = (unsigned char *)fragP->fr_opcode; 633 int rl_addend = 0; 634 635 addend = target_address_for (fragP) - (fragP->fr_address + where); 636 637 fragP->fr_fix = where + subtype_mappings[fragP->fr_subtype].bytes; 638 639 switch (subtype_mappings[fragP->fr_subtype].insn) 640 { 641 case M32C_INSN_JCND16_5: 642 op[1] = addend - 1; 643 operand = M32C_OPERAND_LAB_8_8; 644 rl_addend = 0x21; 645 break; 646 647 case -M32C_MACRO_JCND16_5_W: 648 op[0] ^= 0x04; 649 op[1] = 4; 650 op[2] = 0xf4; 651 op[3] = addend - 3; 652 op[4] = (addend - 3) >> 8; 653 operand = M32C_OPERAND_LAB_8_16; 654 where += 2; 655 rl_addend = 0x51; 656 break; 657 658 case -M32C_MACRO_JCND16_5_A: 659 op[0] ^= 0x04; 660 op[1] = 5; 661 op[2] = 0xfc; 662 operand = M32C_OPERAND_LAB_8_24; 663 where += 2; 664 rl_addend = 0x61; 665 break; 666 667 668 case M32C_INSN_JCND16: 669 op[2] = addend - 2; 670 operand = M32C_OPERAND_LAB_16_8; 671 rl_addend = 0x31; 672 break; 673 674 case -M32C_MACRO_JCND16_W: 675 op[1] ^= 0x04; 676 op[2] = 4; 677 op[3] = 0xf4; 678 op[4] = addend - 4; 679 op[5] = (addend - 4) >> 8; 680 operand = M32C_OPERAND_LAB_8_16; 681 where += 3; 682 rl_addend = 0x61; 683 break; 684 685 case -M32C_MACRO_JCND16_A: 686 op[1] ^= 0x04; 687 op[2] = 5; 688 op[3] = 0xfc; 689 operand = M32C_OPERAND_LAB_8_24; 690 where += 3; 691 rl_addend = 0x71; 692 break; 693 694 case M32C_INSN_JMP16_S: 695 op[0] = 0x60 | ((addend-2) & 0x07); 696 operand = M32C_OPERAND_LAB_5_3; 697 rl_addend = 0x10; 698 break; 699 700 case M32C_INSN_JMP16_B: 701 op[0] = 0xfe; 702 op[1] = addend - 1; 703 operand = M32C_OPERAND_LAB_8_8; 704 rl_addend = 0x21; 705 break; 706 707 case M32C_INSN_JMP16_W: 708 op[0] = 0xf4; 709 op[1] = addend - 1; 710 op[2] = (addend - 1) >> 8; 711 operand = M32C_OPERAND_LAB_8_16; 712 rl_addend = 0x31; 713 break; 714 715 case M32C_INSN_JMP16_A: 716 op[0] = 0xfc; 717 op[1] = 0; 718 op[2] = 0; 719 op[3] = 0; 720 operand = M32C_OPERAND_LAB_8_24; 721 rl_addend = 0x41; 722 break; 723 724 case M32C_INSN_JCND32: 725 op[1] = addend - 1; 726 operand = M32C_OPERAND_LAB_8_8; 727 rl_addend = 0x21; 728 break; 729 730 case -M32C_MACRO_JCND32_W: 731 op[0] ^= 0x40; 732 op[1] = 4; 733 op[2] = 0xce; 734 op[3] = addend - 3; 735 op[4] = (addend - 3) >> 8; 736 operand = M32C_OPERAND_LAB_8_16; 737 where += 2; 738 rl_addend = 0x51; 739 break; 740 741 case -M32C_MACRO_JCND32_A: 742 op[0] ^= 0x40; 743 op[1] = 5; 744 op[2] = 0xcc; 745 operand = M32C_OPERAND_LAB_8_24; 746 where += 2; 747 rl_addend = 0x61; 748 break; 749 750 case M32C_INSN_JMP32_S: 751 addend = ((addend-2) & 0x07); 752 op[0] = 0x4a | (addend & 0x01) | ((addend << 3) & 0x30); 753 operand = M32C_OPERAND_LAB32_JMP_S; 754 rl_addend = 0x10; 755 break; 756 757 case M32C_INSN_JMP32_B: 758 op[0] = 0xbb; 759 op[1] = addend - 1; 760 operand = M32C_OPERAND_LAB_8_8; 761 rl_addend = 0x21; 762 break; 763 764 case M32C_INSN_JMP32_W: 765 op[0] = 0xce; 766 op[1] = addend - 1; 767 op[2] = (addend - 1) >> 8; 768 operand = M32C_OPERAND_LAB_8_16; 769 rl_addend = 0x31; 770 break; 771 772 case M32C_INSN_JMP32_A: 773 op[0] = 0xcc; 774 op[1] = 0; 775 op[2] = 0; 776 op[3] = 0; 777 operand = M32C_OPERAND_LAB_8_24; 778 rl_addend = 0x41; 779 break; 780 781 782 case M32C_INSN_JSR16_W: 783 op[0] = 0xf5; 784 op[1] = addend - 1; 785 op[2] = (addend - 1) >> 8; 786 operand = M32C_OPERAND_LAB_8_16; 787 rl_addend = 0x31; 788 break; 789 790 case M32C_INSN_JSR16_A: 791 op[0] = 0xfd; 792 op[1] = 0; 793 op[2] = 0; 794 op[3] = 0; 795 operand = M32C_OPERAND_LAB_8_24; 796 rl_addend = 0x41; 797 break; 798 799 case M32C_INSN_JSR32_W: 800 op[0] = 0xcf; 801 op[1] = addend - 1; 802 op[2] = (addend - 1) >> 8; 803 operand = M32C_OPERAND_LAB_8_16; 804 rl_addend = 0x31; 805 break; 806 807 case M32C_INSN_JSR32_A: 808 op[0] = 0xcd; 809 op[1] = 0; 810 op[2] = 0; 811 op[3] = 0; 812 operand = M32C_OPERAND_LAB_8_24; 813 rl_addend = 0x41; 814 break; 815 816 case -M32C_MACRO_ADJNZ_2: 817 rl_addend = 0x31; 818 op[2] = addend - 2; 819 operand = M32C_OPERAND_LAB_16_8; 820 break; 821 case -M32C_MACRO_ADJNZ_3: 822 rl_addend = 0x41; 823 op[3] = addend - 2; 824 operand = M32C_OPERAND_LAB_24_8; 825 break; 826 case -M32C_MACRO_ADJNZ_4: 827 rl_addend = 0x51; 828 op[4] = addend - 2; 829 operand = M32C_OPERAND_LAB_32_8; 830 break; 831 case -M32C_MACRO_ADJNZ_5: 832 rl_addend = 0x61; 833 op[5] = addend - 2; 834 operand = M32C_OPERAND_LAB_40_8; 835 break; 836 837 default: 838 printf("\nHey! Need more opcode converters! missing: %d %s\n\n", 839 fragP->fr_subtype, 840 fragP->fr_cgen.insn->base->name); 841 abort(); 842 } 843 844 if (m32c_relax) 845 { 846 if (operand != M32C_OPERAND_LAB_8_24) 847 fragP->fr_offset = (fragP->fr_address + where); 848 849 fix_new (fragP, 850 rl_where, 851 0, abs_section_sym, rl_addend, 0, 852 BFD_RELOC_M32C_RL_JUMP); 853 } 854 855 if (S_GET_SEGMENT (fragP->fr_symbol) != sec 856 || operand == M32C_OPERAND_LAB_8_24 857 || (m32c_relax && (operand != M32C_OPERAND_LAB_5_3 858 && operand != M32C_OPERAND_LAB32_JMP_S))) 859 { 860 gas_assert (fragP->fr_cgen.insn != 0); 861 gas_cgen_record_fixup (fragP, 862 where, 863 fragP->fr_cgen.insn, 864 (fragP->fr_fix - where) * 8, 865 cgen_operand_lookup_by_num (gas_cgen_cpu_desc, 866 operand), 867 fragP->fr_cgen.opinfo, 868 fragP->fr_symbol, 869 fragP->fr_offset); 870 } 871 } 872 873 /* Functions concerning relocs. */ 875 876 /* The location from which a PC relative jump should be calculated, 877 given a PC relative reloc. */ 878 879 long 880 md_pcrel_from_section (fixS * fixP, segT sec) 881 { 882 if (fixP->fx_addsy != (symbolS *) NULL 883 && (! S_IS_DEFINED (fixP->fx_addsy) 884 || S_GET_SEGMENT (fixP->fx_addsy) != sec)) 885 /* The symbol is undefined (or is defined but not in this section). 886 Let the linker figure it out. */ 887 return 0; 888 889 return (fixP->fx_frag->fr_address + fixP->fx_where); 890 } 891 892 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. 893 Returns BFD_RELOC_NONE if no reloc type can be found. 894 *FIXP may be modified if desired. */ 895 896 bfd_reloc_code_real_type 897 md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, 898 const CGEN_OPERAND * operand, 899 fixS * fixP ATTRIBUTE_UNUSED) 900 { 901 static const struct op_reloc { 902 /* A CGEN operand type that can be a relocatable expression. */ 903 CGEN_OPERAND_TYPE operand; 904 905 /* The appropriate BFD reloc type to use for that. */ 906 bfd_reloc_code_real_type reloc; 907 908 /* The offset from the start of the instruction to the field to be 909 relocated, in bytes. */ 910 int offset; 911 } op_reloc_table[] = { 912 913 /* PC-REL relocs for 8-bit fields. */ 914 { M32C_OPERAND_LAB_8_8, BFD_RELOC_8_PCREL, 1 }, 915 { M32C_OPERAND_LAB_16_8, BFD_RELOC_8_PCREL, 2 }, 916 { M32C_OPERAND_LAB_24_8, BFD_RELOC_8_PCREL, 3 }, 917 { M32C_OPERAND_LAB_32_8, BFD_RELOC_8_PCREL, 4 }, 918 { M32C_OPERAND_LAB_40_8, BFD_RELOC_8_PCREL, 5 }, 919 920 /* PC-REL relocs for 16-bit fields. */ 921 { M32C_OPERAND_LAB_8_16, BFD_RELOC_16_PCREL, 1 }, 922 923 /* Absolute relocs for 8-bit fields. */ 924 { M32C_OPERAND_IMM_8_QI, BFD_RELOC_8, 1 }, 925 { M32C_OPERAND_IMM_16_QI, BFD_RELOC_8, 2 }, 926 { M32C_OPERAND_IMM_24_QI, BFD_RELOC_8, 3 }, 927 { M32C_OPERAND_IMM_32_QI, BFD_RELOC_8, 4 }, 928 { M32C_OPERAND_IMM_40_QI, BFD_RELOC_8, 5 }, 929 { M32C_OPERAND_IMM_48_QI, BFD_RELOC_8, 6 }, 930 { M32C_OPERAND_IMM_56_QI, BFD_RELOC_8, 7 }, 931 { M32C_OPERAND_DSP_8_S8, BFD_RELOC_8, 1 }, 932 { M32C_OPERAND_DSP_16_S8, BFD_RELOC_8, 2 }, 933 { M32C_OPERAND_DSP_24_S8, BFD_RELOC_8, 3 }, 934 { M32C_OPERAND_DSP_32_S8, BFD_RELOC_8, 4 }, 935 { M32C_OPERAND_DSP_40_S8, BFD_RELOC_8, 5 }, 936 { M32C_OPERAND_DSP_48_S8, BFD_RELOC_8, 6 }, 937 { M32C_OPERAND_DSP_8_U8, BFD_RELOC_8, 1 }, 938 { M32C_OPERAND_DSP_16_U8, BFD_RELOC_8, 2 }, 939 { M32C_OPERAND_DSP_24_U8, BFD_RELOC_8, 3 }, 940 { M32C_OPERAND_DSP_32_U8, BFD_RELOC_8, 4 }, 941 { M32C_OPERAND_DSP_40_U8, BFD_RELOC_8, 5 }, 942 { M32C_OPERAND_DSP_48_U8, BFD_RELOC_8, 6 }, 943 { M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, BFD_RELOC_8, 2 }, 944 { M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, BFD_RELOC_8, 2 }, 945 { M32C_OPERAND_BITBASE32_24_S11_PREFIXED, BFD_RELOC_8, 3 }, 946 { M32C_OPERAND_BITBASE32_24_U11_PREFIXED, BFD_RELOC_8, 3 }, 947 948 /* Absolute relocs for 16-bit fields. */ 949 { M32C_OPERAND_IMM_8_HI, BFD_RELOC_16, 1 }, 950 { M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 }, 951 { M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 }, 952 { M32C_OPERAND_IMM_32_HI, BFD_RELOC_16, 4 }, 953 { M32C_OPERAND_IMM_40_HI, BFD_RELOC_16, 5 }, 954 { M32C_OPERAND_IMM_48_HI, BFD_RELOC_16, 6 }, 955 { M32C_OPERAND_IMM_56_HI, BFD_RELOC_16, 7 }, 956 { M32C_OPERAND_IMM_64_HI, BFD_RELOC_16, 8 }, 957 { M32C_OPERAND_DSP_16_S16, BFD_RELOC_16, 2 }, 958 { M32C_OPERAND_DSP_24_S16, BFD_RELOC_16, 3 }, 959 { M32C_OPERAND_DSP_32_S16, BFD_RELOC_16, 4 }, 960 { M32C_OPERAND_DSP_40_S16, BFD_RELOC_16, 5 }, 961 { M32C_OPERAND_DSP_8_U16, BFD_RELOC_16, 1 }, 962 { M32C_OPERAND_DSP_16_U16, BFD_RELOC_16, 2 }, 963 { M32C_OPERAND_DSP_24_U16, BFD_RELOC_16, 3 }, 964 { M32C_OPERAND_DSP_32_U16, BFD_RELOC_16, 4 }, 965 { M32C_OPERAND_DSP_40_U16, BFD_RELOC_16, 5 }, 966 { M32C_OPERAND_DSP_48_U16, BFD_RELOC_16, 6 }, 967 { M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, BFD_RELOC_16, 2 }, 968 { M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, BFD_RELOC_16, 2 }, 969 { M32C_OPERAND_BITBASE32_24_S19_PREFIXED, BFD_RELOC_16, 3 }, 970 { M32C_OPERAND_BITBASE32_24_U19_PREFIXED, BFD_RELOC_16, 3 }, 971 972 /* Absolute relocs for 24-bit fields. */ 973 { M32C_OPERAND_LAB_8_24, BFD_RELOC_24, 1 }, 974 { M32C_OPERAND_DSP_8_S24, BFD_RELOC_24, 1 }, 975 { M32C_OPERAND_DSP_8_U24, BFD_RELOC_24, 1 }, 976 { M32C_OPERAND_DSP_16_U24, BFD_RELOC_24, 2 }, 977 { M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 }, 978 { M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 }, 979 { M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 }, 980 { M32C_OPERAND_DSP_48_U24, BFD_RELOC_24, 6 }, 981 { M32C_OPERAND_DSP_16_U20, BFD_RELOC_24, 2 }, 982 { M32C_OPERAND_DSP_24_U20, BFD_RELOC_24, 3 }, 983 { M32C_OPERAND_DSP_32_U20, BFD_RELOC_24, 4 }, 984 { M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, BFD_RELOC_24, 2 }, 985 { M32C_OPERAND_BITBASE32_24_U27_PREFIXED, BFD_RELOC_24, 3 }, 986 987 /* Absolute relocs for 32-bit fields. */ 988 { M32C_OPERAND_IMM_16_SI, BFD_RELOC_32, 2 }, 989 { M32C_OPERAND_IMM_24_SI, BFD_RELOC_32, 3 }, 990 { M32C_OPERAND_IMM_32_SI, BFD_RELOC_32, 4 }, 991 { M32C_OPERAND_IMM_40_SI, BFD_RELOC_32, 5 }, 992 993 }; 994 995 int i; 996 997 for (i = ARRAY_SIZE (op_reloc_table); --i >= 0; ) 998 { 999 const struct op_reloc *or = &op_reloc_table[i]; 1000 1001 if (or->operand == operand->type) 1002 { 1003 fixP->fx_where += or->offset; 1004 fixP->fx_size -= or->offset; 1005 1006 if (fixP->fx_cgen.opinfo 1007 && fixP->fx_cgen.opinfo != BFD_RELOC_NONE) 1008 return fixP->fx_cgen.opinfo; 1009 1010 return or->reloc; 1011 } 1012 } 1013 1014 fprintf 1015 (stderr, 1016 "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %s\n", 1017 operand->name); 1018 1019 return BFD_RELOC_NONE; 1020 } 1021 1022 void 1023 m32c_cons_fix_new (fragS * frag, 1024 int where, 1025 int size, 1026 expressionS *exp, 1027 bfd_reloc_code_real_type type) 1028 { 1029 switch (size) 1030 { 1031 case 1: 1032 type = BFD_RELOC_8; 1033 break; 1034 case 2: 1035 type = BFD_RELOC_16; 1036 break; 1037 case 3: 1038 type = BFD_RELOC_24; 1039 break; 1040 case 4: 1041 default: 1042 type = BFD_RELOC_32; 1043 break; 1044 case 8: 1045 type = BFD_RELOC_64; 1046 break; 1047 } 1048 1049 fix_new_exp (frag, where, (int) size, exp, 0, type); 1050 } 1051 1052 void 1053 m32c_apply_fix (struct fix *f, valueT *t, segT s) 1054 { 1055 if (f->fx_r_type == BFD_RELOC_M32C_RL_JUMP 1056 || f->fx_r_type == BFD_RELOC_M32C_RL_1ADDR 1057 || f->fx_r_type == BFD_RELOC_M32C_RL_2ADDR) 1058 return; 1059 gas_cgen_md_apply_fix (f, t, s); 1060 } 1061 1062 arelent * 1063 tc_gen_reloc (asection *sec, fixS *fx) 1064 { 1065 if (fx->fx_r_type == BFD_RELOC_M32C_RL_JUMP 1066 || fx->fx_r_type == BFD_RELOC_M32C_RL_1ADDR 1067 || fx->fx_r_type == BFD_RELOC_M32C_RL_2ADDR) 1068 { 1069 arelent * reloc; 1070 1071 reloc = xmalloc (sizeof (* reloc)); 1072 1073 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 1074 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy); 1075 reloc->address = fx->fx_frag->fr_address + fx->fx_where; 1076 reloc->howto = bfd_reloc_type_lookup (stdoutput, fx->fx_r_type); 1077 reloc->addend = fx->fx_offset; 1078 return reloc; 1079 1080 } 1081 return gas_cgen_tc_gen_reloc (sec, fx); 1082 } 1083 1084 /* See whether we need to force a relocation into the output file. 1085 This is used to force out switch and PC relative relocations when 1086 relaxing. */ 1087 1088 int 1089 m32c_force_relocation (fixS * fixp) 1090 { 1091 int reloc = fixp->fx_r_type; 1092 1093 if (reloc > (int)BFD_RELOC_UNUSED) 1094 { 1095 reloc -= (int)BFD_RELOC_UNUSED; 1096 switch (reloc) 1097 { 1098 case M32C_OPERAND_DSP_32_S16: 1099 case M32C_OPERAND_DSP_32_U16: 1100 case M32C_OPERAND_IMM_32_HI: 1101 case M32C_OPERAND_DSP_16_S16: 1102 case M32C_OPERAND_DSP_16_U16: 1103 case M32C_OPERAND_IMM_16_HI: 1104 case M32C_OPERAND_DSP_24_S16: 1105 case M32C_OPERAND_DSP_24_U16: 1106 case M32C_OPERAND_IMM_24_HI: 1107 return 1; 1108 1109 /* If we're doing linker relaxing, we need to keep all the 1110 pc-relative jumps in case we need to fix them due to 1111 deleted bytes between the jump and its destination. */ 1112 case M32C_OPERAND_LAB_8_8: 1113 case M32C_OPERAND_LAB_8_16: 1114 case M32C_OPERAND_LAB_8_24: 1115 case M32C_OPERAND_LAB_16_8: 1116 case M32C_OPERAND_LAB_24_8: 1117 case M32C_OPERAND_LAB_32_8: 1118 case M32C_OPERAND_LAB_40_8: 1119 if (m32c_relax) 1120 return 1; 1121 default: 1122 break; 1123 } 1124 } 1125 else 1126 { 1127 switch (fixp->fx_r_type) 1128 { 1129 case BFD_RELOC_16: 1130 return 1; 1131 1132 case BFD_RELOC_M32C_RL_JUMP: 1133 case BFD_RELOC_M32C_RL_1ADDR: 1134 case BFD_RELOC_M32C_RL_2ADDR: 1135 case BFD_RELOC_8_PCREL: 1136 case BFD_RELOC_16_PCREL: 1137 if (m32c_relax) 1138 return 1; 1139 default: 1140 break; 1141 } 1142 } 1143 1144 return generic_force_reloc (fixp); 1145 } 1146 1147 /* Write a value out to the object file, using the appropriate endianness. */ 1149 1150 void 1151 md_number_to_chars (char * buf, valueT val, int n) 1152 { 1153 number_to_chars_littleendian (buf, val, n); 1154 } 1155 1156 /* Turn a string in input_line_pointer into a floating point constant of type 1157 type, and store the appropriate bytes in *litP. The number of LITTLENUMS 1158 emitted is stored in *sizeP . An error message is returned, or NULL on OK. */ 1159 1160 /* Equal to MAX_PRECISION in atof-ieee.c. */ 1161 #define MAX_LITTLENUMS 6 1162 1163 char * 1164 md_atof (int type, char * litP, int * sizeP) 1165 { 1166 return ieee_md_atof (type, litP, sizeP, TRUE); 1167 } 1168 1169 bfd_boolean 1170 m32c_fix_adjustable (fixS * fixP) 1171 { 1172 int reloc; 1173 if (fixP->fx_addsy == NULL) 1174 return 1; 1175 1176 /* We need the symbol name for the VTABLE entries. */ 1177 reloc = fixP->fx_r_type; 1178 if (reloc > (int)BFD_RELOC_UNUSED) 1179 { 1180 reloc -= (int)BFD_RELOC_UNUSED; 1181 switch (reloc) 1182 { 1183 case M32C_OPERAND_DSP_32_S16: 1184 case M32C_OPERAND_DSP_32_U16: 1185 case M32C_OPERAND_IMM_32_HI: 1186 case M32C_OPERAND_DSP_16_S16: 1187 case M32C_OPERAND_DSP_16_U16: 1188 case M32C_OPERAND_IMM_16_HI: 1189 case M32C_OPERAND_DSP_24_S16: 1190 case M32C_OPERAND_DSP_24_U16: 1191 case M32C_OPERAND_IMM_24_HI: 1192 return 0; 1193 } 1194 } 1195 else 1196 { 1197 if (fixP->fx_r_type == BFD_RELOC_16) 1198 return 0; 1199 } 1200 1201 /* Do not adjust relocations involving symbols in merged sections. 1202 1203 A reloc patching in the value of some symbol S plus some addend A 1204 can be produced in different ways: 1205 1206 1) It might simply be a reference to the data at S + A. Clearly, 1207 if linker merging shift that data around, the value patched in 1208 by the reloc needs to be adjusted accordingly. 1209 1210 2) Or, it might be a reference to S, with A added in as a constant 1211 bias. For example, given code like this: 1212 1213 static int S[100]; 1214 1215 ... S[i - 8] ... 1216 1217 it would be reasonable for the compiler to rearrange the array 1218 reference to something like: 1219 1220 ... (S-8)[i] ... 1221 1222 and emit assembly code that refers to S - (8 * sizeof (int)), 1223 so the subtraction is done entirely at compile-time. In this 1224 case, the reloc's addend A would be -(8 * sizeof (int)), and 1225 shifting around code or data at S + A should not affect the 1226 reloc: the reloc isn't referring to that code or data at all. 1227 1228 The linker has no way of knowing which case it has in hand. So, 1229 to disambiguate, we have the linker always treat reloc addends as 1230 in case 2): they're constants that should be simply added to the 1231 symbol value, just like the reloc says. And we express case 1) 1232 in different way: we have the compiler place a label at the real 1233 target, and reference that label with an addend of zero. (The 1234 compiler is unlikely to reference code using a label plus an 1235 offset anyway, since it doesn't know the sizes of the 1236 instructions.) 1237 1238 The simplification being done by gas/write.c:adjust_reloc_syms, 1239 however, turns the explicit-label usage into the label-plus- 1240 offset usage, re-introducing the ambiguity the compiler avoided. 1241 So we need to disable that simplification for symbols referring 1242 to merged data. 1243 1244 This only affects object size a little bit. */ 1245 if (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) 1246 return 0; 1247 1248 if (m32c_relax) 1249 return 0; 1250 1251 return 1; 1252 } 1253 1254 /* Worker function for m32c_is_colon_insn(). */ 1255 static char 1256 restore_colon (int advance_i_l_p_by) 1257 { 1258 char c; 1259 1260 /* Restore the colon, and advance input_line_pointer to 1261 the end of the new symbol. */ 1262 * input_line_pointer = ':'; 1263 input_line_pointer += advance_i_l_p_by; 1264 c = * input_line_pointer; 1265 * input_line_pointer = 0; 1266 1267 return c; 1268 } 1269 1270 /* Determines if the symbol starting at START and ending in 1271 a colon that was at the location pointed to by INPUT_LINE_POINTER 1272 (but which has now been replaced bu a NUL) is in fact an 1273 :Z, :S, :Q, or :G suffix. 1274 If it is, then it restores the colon, advances INPUT_LINE_POINTER 1275 to the real end of the instruction/symbol, and returns the character 1276 that really terminated the symbol. Otherwise it returns 0. */ 1277 char 1278 m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED) 1279 { 1280 char * i_l_p = input_line_pointer; 1281 1282 /* Check to see if the text following the colon is 'G' */ 1283 if (TOLOWER (i_l_p[1]) == 'g' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) 1284 return restore_colon (2); 1285 1286 /* Check to see if the text following the colon is 'Q' */ 1287 if (TOLOWER (i_l_p[1]) == 'q' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) 1288 return restore_colon (2); 1289 1290 /* Check to see if the text following the colon is 'S' */ 1291 if (TOLOWER (i_l_p[1]) == 's' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) 1292 return restore_colon (2); 1293 1294 /* Check to see if the text following the colon is 'Z' */ 1295 if (TOLOWER (i_l_p[1]) == 'z' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) 1296 return restore_colon (2); 1297 1298 return 0; 1299 } 1300
