/external/llvm/lib/Target/X86/ |
X86CallingConv.h | 53 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; 54 static const unsigned NumRegs = sizeof(RegList)/sizeof(RegList[0]); 72 if (unsigned Reg = State.AllocateReg(RegList)) { 88 unsigned FirstFree = State.getFirstUnallocated(RegList); 93 It.convertToReg(State.AllocateReg(RegList[FirstFree++]));
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMCallingConv.h | 32 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 35 if (unsigned Reg = State.AllocateReg(RegList, 4)) 50 if (unsigned Reg = State.AllocateReg(RegList, 4))
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ARMAsmPrinter.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64CallingConvention.h | 89 ArrayRef<MCPhysReg> RegList; 91 RegList = XRegList; 93 RegList = HRegList; 95 RegList = SRegList; 97 RegList = DRegList; 99 RegList = QRegList; 115 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size()); 127 for (auto Reg : RegList)
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/external/swiftshader/third_party/LLVM/utils/TableGen/ |
CallingConvEmitter.cpp | 94 ListInit *RegList = Action->getValueAsListInit("RegList"); 95 if (RegList->getSize() == 1) { 97 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; 99 O << IndentStr << "static const unsigned RegList" << ++Counter 102 for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) { 104 O << getQualifiedName(RegList->getElementAsRecord(i)); 107 O << IndentStr << "if (unsigned Reg = State.AllocateReg(RegList" 108 << Counter << ", " << RegList->getSize() << ")) {\n"; 115 ListInit *RegList = Action->getValueAsListInit("RegList") [all...] |
CodeGenRegisters.cpp | 712 std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases"); 713 for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) { 714 CodeGenRegister *Reg2 = getReg(RegList[i2]);
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/external/vixl/src/aarch64/ |
operands-aarch64.h | 35 typedef uint64_t RegList; 36 static const int kRegListSizeInBits = sizeof(RegList) * 8; 80 RegList GetBit() const { 81 VIXL_ASSERT(code_ < (sizeof(RegList) * 8)); 82 return IsValid() ? (static_cast<RegList>(1) << code_) : 0; 84 VIXL_DEPRECATED("GetBit", RegList Bit() const) { return GetBit(); } 531 CPURegList(CPURegister::RegisterType type, unsigned size, RegList list) 637 RegList GetList() const { 641 VIXL_DEPRECATED("GetList", RegList list() const) { return GetList(); } 643 void SetList(RegList new_list) [all...] |
/external/llvm/utils/TableGen/ |
CallingConvEmitter.cpp | 113 ListInit *RegList = Action->getValueAsListInit("RegList"); 114 if (RegList->size() == 1) { 116 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; 118 O << IndentStr << "static const MCPhysReg RegList" << ++Counter 121 for (unsigned i = 0, e = RegList->size(); i != e; ++i) { 123 O << getQualifiedName(RegList->getElementAsRecord(i)); 126 O << IndentStr << "if (unsigned Reg = State.AllocateReg(RegList" 134 ListInit *RegList = Action->getValueAsListInit("RegList"); [all...] |
/external/llvm/lib/CodeGen/ |
MachineCopyPropagation.cpp | 35 typedef SmallVector<unsigned, 4> RegList; 36 typedef DenseMap<unsigned, RegList> SourceMap; 86 static void removeRegsFromMap(Reg2MIMap &Map, const RegList &Regs, 247 RegList &DestList = SrcMap[Src];
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/external/llvm/lib/Target/ARM/ |
ARMCallingConv.h | 31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 34 if (unsigned Reg = State.AllocateReg(RegList)) 49 if (unsigned Reg = State.AllocateReg(RegList)) 206 ArrayRef<MCPhysReg> RegList; 209 RegList = RRegList; 210 unsigned RegIdx = State.getFirstUnallocated(RegList); 215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) 216 State.AllocateReg(RegList[RegIdx++]); 221 RegList = SRegList; 224 RegList = DRegList [all...] |
ARMBaseRegisterInfo.cpp | 64 const MCPhysReg *RegList = 98 return RegList;
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ARMAsmPrinter.cpp | [all...] |
ARMBaseInstrInfo.cpp | [all...] |
/art/compiler/utils/arm/ |
constants_arm.h | 128 typedef uint16_t RegList;
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/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 278 static const MCPhysReg RegList[] = { 281 static const unsigned NbRegs = array_lengthof(RegList); 323 unsigned Reg = State.AllocateReg(RegList); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
SparcISelLowering.cpp | 54 static const unsigned RegList[] = { 58 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 69 if (unsigned Reg = State.AllocateReg(RegList, 6)) [all...] |
/prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
inst.go | 77 // Endian, Imm, Mem, PCRel, Reg, RegList, RegShift, RegShiftReg. 278 // A RegList is a register list. 280 type RegList uint16 282 func (RegList) IsArg() {} 284 func (r RegList) String() string {
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/prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
inst.go | 77 // Endian, Imm, Mem, PCRel, Reg, RegList, RegShift, RegShiftReg. 278 // A RegList is a register list. 280 type RegList uint16 282 func (RegList) IsArg() {} 284 func (r RegList) String() string {
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/external/v8/src/ |
frames.h | 16 typedef uint64_t RegList; 18 typedef uint32_t RegList; 22 int NumRegs(RegList list); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | 276 static const MCPhysReg RegList[] = { 280 if (unsigned Reg = State.AllocateReg(RegList)) { [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 56 static const MCPhysReg RegList[] = { 60 if (unsigned Reg = State.AllocateReg(RegList)) { 71 if (unsigned Reg = State.AllocateReg(RegList)) 84 static const MCPhysReg RegList[] = { 89 if (unsigned Reg = State.AllocateReg(RegList)) 95 if (unsigned Reg = State.AllocateReg(RegList)) [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |
/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | 629 struct RegListOp RegList; [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |