1 /* 2 * Copyright (C) 2009 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 18 #define ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 19 20 #include <stdint.h> 21 22 #include <iosfwd> 23 24 #include "arch/arm/registers_arm.h" 25 #include "base/casts.h" 26 #include "base/logging.h" 27 #include "globals.h" 28 29 namespace art { 30 namespace arm { 31 32 // Defines constants and accessor classes to assemble, disassemble and 33 // simulate ARM instructions. 34 // 35 // Section references in the code refer to the "ARM Architecture 36 // Reference Manual ARMv7-A and ARMv7-R edition", issue C.b (24 July 37 // 2012). 38 // 39 // Constants for specific fields are defined in their respective named enums. 40 // General constants are in an anonymous enum in class Instr. 41 42 // 4 bits option for the dmb instruction. 43 // Order and values follows those of the ARM Architecture Reference Manual. 44 enum DmbOptions { 45 SY = 0xf, 46 ST = 0xe, 47 ISH = 0xb, 48 ISHST = 0xa, 49 NSH = 0x7, 50 NSHST = 0x6 51 }; 52 53 enum ScaleFactor { 54 TIMES_1 = 0, 55 TIMES_2 = 1, 56 TIMES_4 = 2, 57 TIMES_8 = 3 58 }; 59 60 // Values for double-precision floating point registers. 61 enum DRegister { // private marker to avoid generate-operator-out.py from processing. 62 D0 = 0, 63 D1 = 1, 64 D2 = 2, 65 D3 = 3, 66 D4 = 4, 67 D5 = 5, 68 D6 = 6, 69 D7 = 7, 70 D8 = 8, 71 D9 = 9, 72 D10 = 10, 73 D11 = 11, 74 D12 = 12, 75 D13 = 13, 76 D14 = 14, 77 D15 = 15, 78 D16 = 16, 79 D17 = 17, 80 D18 = 18, 81 D19 = 19, 82 D20 = 20, 83 D21 = 21, 84 D22 = 22, 85 D23 = 23, 86 D24 = 24, 87 D25 = 25, 88 D26 = 26, 89 D27 = 27, 90 D28 = 28, 91 D29 = 29, 92 D30 = 30, 93 D31 = 31, 94 kNumberOfDRegisters = 32, 95 kNumberOfOverlappingDRegisters = 16, 96 kNoDRegister = -1, 97 }; 98 std::ostream& operator<<(std::ostream& os, const DRegister& rhs); 99 100 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) 101 // as defined in section A3.4 102 enum Opcode { 103 kNoOperand = -1, 104 AND = 0, // Logical AND 105 EOR = 1, // Logical Exclusive OR 106 SUB = 2, // Subtract 107 RSB = 3, // Reverse Subtract 108 ADD = 4, // Add 109 ADC = 5, // Add with Carry 110 SBC = 6, // Subtract with Carry 111 RSC = 7, // Reverse Subtract with Carry 112 TST = 8, // Test 113 TEQ = 9, // Test Equivalence 114 CMP = 10, // Compare 115 CMN = 11, // Compare Negated 116 ORR = 12, // Logical (inclusive) OR 117 MOV = 13, // Move 118 BIC = 14, // Bit Clear 119 MVN = 15, // Move Not 120 ORN = 16, // Logical OR NOT. 121 kMaxOperand = 17 122 }; 123 124 // Size (in bytes) of registers. 125 const int kRegisterSize = 4; 126 127 // List of registers used in load/store multiple. 128 typedef uint16_t RegList; 129 130 131 } // namespace arm 132 } // namespace art 133 134 #endif // ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 135
