| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 108 MI.getOperand(1).getReg(), // src0
222 unsigned Src0 = BMI->getOperand(
223 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
228 (void) Src0;
230 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
274 unsigned Src0 = MI.getOperand(
275 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
287 Src0 = TRI.getSubReg(Src0, SubRegIndex)
[all...] |
| SIShrinkInstructions.cpp | 113 // We don't need to check src0, all input types are legal, so just make sure
114 // src0 isn't using any modifiers.
138 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
139 MachineOperand &Src0 = MI.getOperand(Src0Idx);
141 // Only one literal constant is allowed per instruction, so if src0 is a
143 if (Src0.isImm() &&
144 TII->isLiteralConstant(Src0, TII->getOpSize(MI, Src0Idx)))
147 // Literal constants and SGPRs can only be used in Src0, so if Src0 is an
150 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)
[all...] |
| AMDGPUPromoteAlloca.cpp | 729 Value *Src0 = CI->getOperand(0);
730 Type *EltTy = Src0->getType()->getPointerElementType();
|
| SIInstrInfo.cpp | 889 unsigned Src0 = MI.getOperand(1).getReg();
894 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
899 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
953 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
954 MachineOperand &Src0 = MI.getOperand(Src0Idx);
955 if (!Src0.isReg())
[all...] |
| SIISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 306 unsigned Src0 = 0, SubReg0;
317 Src0 = MOSrc0->getReg();
319 // Src0 is going to be reused, thus, it cannot be killed anymore.
338 // Src0 is going to be reused, thus, it cannot be killed anymore.
349 if (!Src0) {
351 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
352 insertCopy(TII, MI, Src0, OrigSrc0, KillSrc0);
371 .addReg(Src0, getKillRegState(KillSrc0), SubReg0)
|
| AArch64FastISel.cpp | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceInstMIPS32.cpp | 165 auto *Src0 = llvm::cast<Constant>(getSrc(0));
166 if (auto *CR = llvm::dyn_cast<ConstantRelocatable>(Src0)) {
172 Src0->emit(Func);
183 const CfgNode *TargetFalse, Operand *Src0,
187 addSource(Src0);
191 const CfgNode *TargetFalse, Operand *Src0,
196 addSource(Src0);
[all...] |
| IceConverter.cpp | 346 Ice::Operand *Src0 = convertOperand(Instr, 0);
349 return Ice::InstArithmetic::create(Func.get(), Opcode, Dest, Src0, Src1);
406 Ice::Operand *Src0 = convertOperand(Instr, 0);
446 return Ice::InstIcmp::create(Func.get(), Cond, Dest, Src0, Src1);
450 Ice::Operand *Src0 = convertOperand(Instr, 0);
510 return Ice::InstFcmp::create(Func.get(), Cond, Dest, Src0, Src1);
[all...] |
| IceInstX86BaseImpl.h | 253 InstImpl<TraitsType>::InstX86Icmp::InstX86Icmp(Cfg *Func, Operand *Src0,
256 this->addSource(Src0);
261 InstImpl<TraitsType>::InstX86Ucomiss::InstX86Ucomiss(Cfg *Func, Operand *Src0,
264 this->addSource(Src0);
[all...] |
| IceTargetLowering.h | 504 Operand *Src0, Operand *Src1);
509 /// (Variable *Dest, Variable *Src0, Variable *Src1) -> Instr *.
566 auto *Src0 = thunk0();
567 return insertScalarInstruction(Res, Src0);
575 auto *Src0 = thunk0();
577 return insertScalarInstruction(Res, Src0, Src1);
585 auto *Src0 = thunk0();
588 return insertScalarInstruction(Res, Src0, Src1, Src2);
|
| IceCfg.cpp | [all...] |
| IceInstARM32.cpp | [all...] |
| IceTargetLoweringARM32.cpp | 541 Operand *Src0 = Instr->getSrc(0);
544 // Src0 and Src1 have to be zero-, or signed-extended to i32. For Src0,
547 Context.insert<InstCast>(CastKind, Src0_32, Src0);
548 Src0 = Src0_32;
574 assert(Src0->getType() == IceType_i32);
575 Call->addArg(Src0);
602 Operand *Src0 = Instr->getSrc(0);
604 const Type SrcTy = Src0->getType();
626 Call->addArg(Src0);
[all...] |
| IceTargetLoweringX86BaseImpl.h | 802 /// Replaces Src0 or Src1 with LoadSrc if the answer is true.
804 Operand *&Src0, Operand *&Src1) {
805 if (Src0 == LoadDest && Src1 != LoadDest) {
806 Src0 = LoadSrc;
809 if (Src0 != LoadDest && Src1 == LoadDest) {
855 Operand *Src0 = Arith->getSrc(0);
857 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
859 Arith->getDest(), Src0, Src1);
862 Operand *Src0 = Icmp->getSrc(0);
864 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1))
[all...] |
| IceTargetLoweringMIPS32.cpp | 306 Operand *Src0 = Instr->getSrc(0);
316 Context.insert<InstExtractElement>(Op0, Src0, Index);
333 Operand *Src0 = Instr->getSrc(0);
335 const Type SrcType = Src0->getType();
344 Context.insert<InstExtractElement>(Op0, Src0, Index);
421 Operand *Src0 = Instr->getSrc(0);
422 const Type SrcTy = Src0->getType();
435 Context.insert<InstExtractElement>(Op, Src0, Index);
475 Call->addArg(Src0);
504 Call->addArg(Src0);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | 226 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0));
228 Value *F = CGF.CGM.getIntrinsic(IntrinsicID, Src0->getType());
229 return CGF.Builder.CreateCall(F, Src0);
236 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0));
239 Value *F = CGF.CGM.getIntrinsic(IntrinsicID, Src0->getType());
240 return CGF.Builder.CreateCall(F, { Src0, Src1 });
247 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0));
251 Value *F = CGF.CGM.getIntrinsic(IntrinsicID, Src0->getType());
252 return CGF.Builder.CreateCall(F, { Src0, Src1, Src2 });
259 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0))
[all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
