| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXMachineFunctionInfo.h | 43 RegisterMap UsedRegs;
54 UsedRegs[PTX::RegPredRegisterClass] = RegisterList();
55 UsedRegs[PTX::RegI16RegisterClass] = RegisterList();
56 UsedRegs[PTX::RegI32RegisterClass] = RegisterList();
57 UsedRegs[PTX::RegI64RegisterClass] = RegisterList();
58 UsedRegs[PTX::RegF32RegisterClass] = RegisterList();
59 UsedRegs[PTX::RegF64RegisterClass] = RegisterList();
108 UsedRegs[TRC].push_back(Reg);
124 name += utostr(UsedRegs[TRC].size() - 1);
143 return UsedRegs.lookup(TRC).size()
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CallFrameOptimization.cpp | 101 DenseSet<unsigned int> &UsedRegs);
261 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) {
308 for (unsigned int U : UsedRegs)
367 DenseSet<unsigned int> UsedRegs;
369 while ((Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs)) !=
416 UsedRegs.insert(Reg);
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIInsertWaits.cpp | 80 RegCounters UsedRegs;
351 UsedRegs[j] = Limit;
476 increaseCounters(Result, UsedRegs[j]);
529 memset(&UsedRegs, 0, sizeof(UsedRegs));
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| CallingConvLower.h | 164 SmallVector<uint32_t, 16> UsedRegs;
191 return UsedRegs[Reg/32] & (1 << (Reg&31));
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 206 SmallVector<uint32_t, 16> UsedRegs;
291 return UsedRegs[Reg/32] & (1 << (Reg&31));
|
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 201 SmallVector<uint32_t, 16> UsedRegs;
283 return UsedRegs[Reg/32] & (1 << (Reg&31));
|
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 201 SmallVector<uint32_t, 16> UsedRegs;
283 return UsedRegs[Reg/32] & (1 << (Reg&31));
|
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 201 SmallVector<uint32_t, 16> UsedRegs;
283 return UsedRegs[Reg/32] & (1 << (Reg&31));
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 201 SmallVector<uint32_t, 16> UsedRegs;
283 return UsedRegs[Reg/32] & (1 << (Reg&31));
|
| /prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 201 SmallVector<uint32_t, 16> UsedRegs;
283 return UsedRegs[Reg/32] & (1 << (Reg&31));
|
| /prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 201 SmallVector<uint32_t, 16> UsedRegs;
283 return UsedRegs[Reg/32] & (1 << (Reg&31));
|
| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 201 SmallVector<uint32_t, 16> UsedRegs;
283 return UsedRegs[Reg/32] & (1 << (Reg&31));
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 201 SmallVector<uint32_t, 16> UsedRegs;
283 return UsedRegs[Reg/32] & (1 << (Reg&31));
|
| /external/llvm/lib/CodeGen/ |
| MachineBasicBlock.cpp | 766 SmallVector<unsigned, 4> UsedRegs;
778 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
779 UsedRegs.push_back(Reg);
919 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64LoadStoreOptimizer.cpp | 99 BitVector ModifiedRegs, UsedRegs;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 821 DenseSet<unsigned> UsedRegs;
830 UsedRegs.insert(Reg);
[all...] |
| ARMFastISel.cpp | 200 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMFastISel.cpp | 199 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
