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Searched
refs:BIT1
(Results
1 - 25
of
248
) sorted by null
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/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530.h
34
#define PBIASLITEPWRDNZ0
BIT1
Omap3530Uart.h
33
#define UART_FCR_RX_FIFO_CLEAR
BIT1
38
#define UART_LCR_CHAR_LENGTH_8 (
BIT1
| BIT0)
40
#define UART_MCR_RTS_FORCE_ACTIVE
BIT1
Omap3530Usb.h
30
#define UHH_SYSCONFIG_SOFTRESET
BIT1
43
#define UHH_SYSSTATUS_RESETDONE (BIT0 |
BIT1
| BIT2)
Omap3530Timer.h
55
#define TISR_OVF_IT_FLAG_MASK
BIT1
65
#define TISR_OVF_IT_FLAG_CLEAR
BIT1
69
#define TCLR_AR_AUTORELOAD
BIT1
76
#define TIER_OVF_IT_ENABLE
BIT1
Omap3530I2c.h
25
#define NACK_IE
BIT1
32
#define NACK
BIT1
43
#define STP
BIT1
Omap3530Prcm.h
75
#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK
BIT1
77
#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE
BIT1
153
#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS
BIT1
159
#define RST_GS
BIT1
161
#define GLOBAL_SW_RST
BIT1
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530.h
34
#define PBIASLITEPWRDNZ0
BIT1
Omap3530Uart.h
33
#define UART_FCR_RX_FIFO_CLEAR
BIT1
38
#define UART_LCR_CHAR_LENGTH_8 (
BIT1
| BIT0)
40
#define UART_MCR_RTS_FORCE_ACTIVE
BIT1
Omap3530Usb.h
30
#define UHH_SYSCONFIG_SOFTRESET
BIT1
43
#define UHH_SYSSTATUS_RESETDONE (BIT0 |
BIT1
| BIT2)
Omap3530Timer.h
55
#define TISR_OVF_IT_FLAG_MASK
BIT1
65
#define TISR_OVF_IT_FLAG_CLEAR
BIT1
69
#define TCLR_AR_AUTORELOAD
BIT1
76
#define TIER_OVF_IT_ENABLE
BIT1
Omap3530I2c.h
25
#define NACK_IE
BIT1
32
#define NACK
BIT1
43
#define STP
BIT1
Omap3530Prcm.h
75
#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK
BIT1
77
#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE
BIT1
153
#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS
BIT1
159
#define RST_GS
BIT1
161
#define GLOBAL_SW_RST
BIT1
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsRcrb.h
50
#define B_PCH_RCRB_GCS_TS
BIT1
// Top Swap
PchRegsUsb.h
72
#define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (
BIT1
| BIT0) // Power State
74
#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (
BIT1
| BIT0) // D3 Hot State
95
#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (
BIT1
| BIT0)
96
#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (
BIT1
| BIT0)
PchRegsLpss.h
68
#define B_PCH_LPSS_DMAC_STSCMD_MSE
BIT1
// Memory Space Enable
86
#define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 |
BIT1
) // Type
93
#define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 |
BIT1
) // Type
122
#define B_PCH_LPSS_DMAC_PCS_PS (
BIT1
| BIT0) // Power State
153
#define B_PCH_LPSS_I2C_STSCMD_MSE
BIT1
// Memory Space Enable
171
#define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 |
BIT1
) // Type
178
#define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 |
BIT1
) // Type
207
#define B_PCH_LPSS_I2C_PCS_PS (
BIT1
| BIT0) // Power State
217
#define B_PCH_LPSS_I2C_MEM_RESETS_FUNC
BIT1
// Function Clock Domain Reset
240
#define B_PCH_LPSS_PWM_STSCMD_MSE
BIT1
// Memory Space Enable
[
all
...]
PchRegsPcu.h
84
#define B_PCH_LPC_COMMAND_MSE
BIT1
// Memory Space Enable
141
#define B_PCH_LPC_ACPI_BASE_EN
BIT1
// Enable Bit
148
#define B_PCH_LPC_PMC_BASE_EN
BIT1
// Enable Bit
153
#define B_PCH_LPC_GPIO_BASE_EN
BIT1
// Enable Bit
160
#define B_PCH_LPC_IO_BASE_EN
BIT1
// Enable Bit
167
#define B_PCH_LPC_ILB_BASE_EN
BIT1
// Enable Bit
174
#define B_PCH_LPC_SPI_BASE_EN
BIT1
// Enable Bit
181
#define B_PCH_LPC_MPHY_BASE_EN
BIT1
// Enable Bit
188
#define B_PCH_LPC_PUNIT_BASE_EN
BIT1
// Enable Bit
207
#define B_PCH_LPC_FWH_BIOS_DEC_E50
BIT1
// 50-5F Enable
[
all
...]
PchRegsHda.h
52
#define B_PCH_HDA_PCS_PS (
BIT1
| BIT0) // Power State - D0/D3 Hot
PchRegsSmbus.h
63
#define B_PCH_SMBUS_PCICMD_MSE
BIT1
// Memory Space Enable
85
#define B_PCH_SMBUS_INTR
BIT1
// Interrupt
101
#define B_PCH_SMBUS_KILL
BIT1
// Kill
127
#define B_PCH_SMBUS_E32B
BIT1
// Enable 32-byte Buffer
132
#define B_PCH_SMBUS_SMLINK1_CUR_STS
BIT1
// Not supported
138
#define B_PCH_SMBUS_SMBDATA_CUR_STS
BIT1
// SMBDATA Current Status
146
#define B_PCH_SMBUS_HOST_NOTIFY_WKEN
BIT1
// Host Notify Wake Enable
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
I2cRegs.h
50
#define B_I2C_REG_CON_SPEED (BIT2+
BIT1
) // standard mode (01) or fast mode (10)
53
#define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+
BIT1
+BIT0) // Master Target Address bits
69
#define I2C_REG_RAW_INTR_STAT_RX_OVER (
BIT1
) // Raw Interrupt Status Register RX Overflow signal status.
88
#define B_I2C_REG_TXFLR (BIT3+BIT2+
BIT1
+BIT0) // Transmit FIFO Level Register bits
90
#define B_I2C_REG_RXFLR (BIT3+BIT2+
BIT1
+BIT0) // Receive FIFO Level Register bits
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeUtil.h
105
#define SOFT_RESET_CLEAR_INT
BIT1
117
#define PHY_RESET_BCR
BIT1
149
#define AUTO_NEGOTIATE_ADVERTISE_ALL
BIT1
167
#define STOP_TX_CFG
BIT1
189
#define START_TX_CFG
BIT1
240
#define ALLOC_USE_FIFOS
BIT1
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
Fdc.h
43
#define MSR_DBB
BIT1
// Drive B Busy
51
#define CCR_DRC (BIT0 |
BIT1
) // Data Rate select
105
#define STS0_US1
BIT1
// Unit Select1
120
#define STS1_NW
BIT1
// Not Writable
135
#define STS2_BC
BIT1
// Bad Cylinder
155
#define STS3_US1
BIT1
// Unit Select1
/device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/
CacheLibInternal.h
36
#define B_EFI_MSR_CACHE_MEMORY_TYPE (BIT2 |
BIT1
| BIT0)
53
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 |
BIT1
| BIT0)
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/
ExI.c
99
MmioOr32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), (UINT32) BIT0+
BIT1
+BIT2);
101
MmioAnd32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), ~((UINT32) BIT0+
BIT1
+BIT2)); //clear bit 0,1,2
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
UhciReg.h
50
#define USBPORTSC_CSC
BIT1
// Connect Status Change
71
#define USBCMD_HCRESET
BIT1
// Host reset
83
#define USBSTS_ERROR
BIT1
// Interrupt due to error
95
#define USBTD_BITSTUFF
BIT1
// Bit stuff error
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h
34
#define MCH_GGC_IVD
BIT1
47
#define MCH_ESMRAMC_TSEG_2MB
BIT1
49
#define MCH_ESMRAMC_TSEG_MASK (BIT2 |
BIT1
)
Completed in 218 milliseconds
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