1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "PPC.h" 11 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 12 #include "llvm/MC/MCFixedLenDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/Support/Endian.h" 16 #include "llvm/Support/TargetRegistry.h" 17 18 using namespace llvm; 19 20 #define DEBUG_TYPE "ppc-disassembler" 21 22 typedef MCDisassembler::DecodeStatus DecodeStatus; 23 24 namespace { 25 class PPCDisassembler : public MCDisassembler { 26 bool IsLittleEndian; 27 28 public: 29 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 30 bool IsLittleEndian) 31 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 32 33 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 34 ArrayRef<uint8_t> Bytes, uint64_t Address, 35 raw_ostream &VStream, 36 raw_ostream &CStream) const override; 37 }; 38 } // end anonymous namespace 39 40 static MCDisassembler *createPPCDisassembler(const Target &T, 41 const MCSubtargetInfo &STI, 42 MCContext &Ctx) { 43 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 44 } 45 46 static MCDisassembler *createPPCLEDisassembler(const Target &T, 47 const MCSubtargetInfo &STI, 48 MCContext &Ctx) { 49 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 50 } 51 52 extern "C" void LLVMInitializePowerPCDisassembler() { 53 // Register the disassembler for each target. 54 TargetRegistry::RegisterMCDisassembler(ThePPC32Target, 55 createPPCDisassembler); 56 TargetRegistry::RegisterMCDisassembler(ThePPC64Target, 57 createPPCDisassembler); 58 TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget, 59 createPPCLEDisassembler); 60 } 61 62 // FIXME: These can be generated by TableGen from the existing register 63 // encoding values! 64 65 static const unsigned CRRegs[] = { 66 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 67 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 68 }; 69 70 static const unsigned CRBITRegs[] = { 71 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 72 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 73 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 74 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 75 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 76 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 77 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 78 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN 79 }; 80 81 static const unsigned FRegs[] = { 82 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 83 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 84 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 85 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 86 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 87 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 88 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 89 PPC::F28, PPC::F29, PPC::F30, PPC::F31 90 }; 91 92 static const unsigned VRegs[] = { 93 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 94 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 95 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 96 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 97 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 98 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 99 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 100 PPC::V28, PPC::V29, PPC::V30, PPC::V31 101 }; 102 103 static const unsigned VSRegs[] = { 104 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, 105 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, 106 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, 107 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, 108 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 109 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, 110 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, 111 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 112 113 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3, 114 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, 115 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11, 116 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15, 117 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19, 118 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23, 119 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27, 120 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31 121 }; 122 123 static const unsigned VSFRegs[] = { 124 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 125 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 126 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 127 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 128 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 129 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 130 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 131 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 132 133 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 134 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 135 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 136 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 137 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 138 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 139 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 140 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 141 }; 142 143 static const unsigned VSSRegs[] = { 144 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 145 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 146 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 147 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 148 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 149 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 150 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 151 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 152 153 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 154 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 155 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 156 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 157 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 158 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 159 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 160 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 161 }; 162 163 static const unsigned GPRegs[] = { 164 PPC::R0, PPC::R1, PPC::R2, PPC::R3, 165 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 166 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 167 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 168 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 169 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 170 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 171 PPC::R28, PPC::R29, PPC::R30, PPC::R31 172 }; 173 174 static const unsigned GP0Regs[] = { 175 PPC::ZERO, PPC::R1, PPC::R2, PPC::R3, 176 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 177 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 178 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 179 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 180 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 181 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 182 PPC::R28, PPC::R29, PPC::R30, PPC::R31 183 }; 184 185 static const unsigned G8Regs[] = { 186 PPC::X0, PPC::X1, PPC::X2, PPC::X3, 187 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 188 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 189 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 190 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 191 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 192 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 193 PPC::X28, PPC::X29, PPC::X30, PPC::X31 194 }; 195 196 static const unsigned QFRegs[] = { 197 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3, 198 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7, 199 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, 200 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15, 201 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19, 202 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23, 203 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27, 204 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31 205 }; 206 207 template <std::size_t N> 208 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 209 const unsigned (&Regs)[N]) { 210 assert(RegNo < N && "Invalid register number"); 211 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 212 return MCDisassembler::Success; 213 } 214 215 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 216 uint64_t Address, 217 const void *Decoder) { 218 return decodeRegisterClass(Inst, RegNo, CRRegs); 219 } 220 221 static DecodeStatus DecodeCRRC0RegisterClass(MCInst &Inst, uint64_t RegNo, 222 uint64_t Address, 223 const void *Decoder) { 224 return decodeRegisterClass(Inst, RegNo, CRRegs); 225 } 226 227 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 228 uint64_t Address, 229 const void *Decoder) { 230 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 231 } 232 233 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 234 uint64_t Address, 235 const void *Decoder) { 236 return decodeRegisterClass(Inst, RegNo, FRegs); 237 } 238 239 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 240 uint64_t Address, 241 const void *Decoder) { 242 return decodeRegisterClass(Inst, RegNo, FRegs); 243 } 244 245 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 246 uint64_t Address, 247 const void *Decoder) { 248 return decodeRegisterClass(Inst, RegNo, VRegs); 249 } 250 251 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 252 uint64_t Address, 253 const void *Decoder) { 254 return decodeRegisterClass(Inst, RegNo, VSRegs); 255 } 256 257 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 258 uint64_t Address, 259 const void *Decoder) { 260 return decodeRegisterClass(Inst, RegNo, VSFRegs); 261 } 262 263 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 264 uint64_t Address, 265 const void *Decoder) { 266 return decodeRegisterClass(Inst, RegNo, VSSRegs); 267 } 268 269 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 270 uint64_t Address, 271 const void *Decoder) { 272 return decodeRegisterClass(Inst, RegNo, GPRegs); 273 } 274 275 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 276 uint64_t Address, 277 const void *Decoder) { 278 return decodeRegisterClass(Inst, RegNo, GP0Regs); 279 } 280 281 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 282 uint64_t Address, 283 const void *Decoder) { 284 return decodeRegisterClass(Inst, RegNo, G8Regs); 285 } 286 287 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 288 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 289 290 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 291 uint64_t Address, 292 const void *Decoder) { 293 return decodeRegisterClass(Inst, RegNo, QFRegs); 294 } 295 296 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 297 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 298 299 template<unsigned N> 300 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 301 int64_t Address, const void *Decoder) { 302 assert(isUInt<N>(Imm) && "Invalid immediate"); 303 Inst.addOperand(MCOperand::createImm(Imm)); 304 return MCDisassembler::Success; 305 } 306 307 template<unsigned N> 308 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 309 int64_t Address, const void *Decoder) { 310 assert(isUInt<N>(Imm) && "Invalid immediate"); 311 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 312 return MCDisassembler::Success; 313 } 314 315 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 316 int64_t Address, const void *Decoder) { 317 // Decode the memri field (imm, reg), which has the low 16-bits as the 318 // displacement and the next 5 bits as the register #. 319 320 uint64_t Base = Imm >> 16; 321 uint64_t Disp = Imm & 0xFFFF; 322 323 assert(Base < 32 && "Invalid base register"); 324 325 switch (Inst.getOpcode()) { 326 default: break; 327 case PPC::LBZU: 328 case PPC::LHAU: 329 case PPC::LHZU: 330 case PPC::LWZU: 331 case PPC::LFSU: 332 case PPC::LFDU: 333 // Add the tied output operand. 334 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); 335 break; 336 case PPC::STBU: 337 case PPC::STHU: 338 case PPC::STWU: 339 case PPC::STFSU: 340 case PPC::STFDU: 341 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base])); 342 break; 343 } 344 345 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 346 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); 347 return MCDisassembler::Success; 348 } 349 350 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 351 int64_t Address, const void *Decoder) { 352 // Decode the memrix field (imm, reg), which has the low 14-bits as the 353 // displacement and the next 5 bits as the register #. 354 355 uint64_t Base = Imm >> 14; 356 uint64_t Disp = Imm & 0x3FFF; 357 358 assert(Base < 32 && "Invalid base register"); 359 360 if (Inst.getOpcode() == PPC::LDU) 361 // Add the tied output operand. 362 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); 363 else if (Inst.getOpcode() == PPC::STDU) 364 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base])); 365 366 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 367 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); 368 return MCDisassembler::Success; 369 } 370 371 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 372 int64_t Address, const void *Decoder) { 373 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 374 // displacement with 16-byte aligned, and the next 5 bits as the register #. 375 376 uint64_t Base = Imm >> 12; 377 uint64_t Disp = Imm & 0xFFF; 378 379 assert(Base < 32 && "Invalid base register"); 380 381 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 382 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); 383 return MCDisassembler::Success; 384 } 385 386 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 387 int64_t Address, const void *Decoder) { 388 // The cr bit encoding is 0x80 >> cr_reg_num. 389 390 unsigned Zeros = countTrailingZeros(Imm); 391 assert(Zeros < 8 && "Invalid CR bit value"); 392 393 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 394 return MCDisassembler::Success; 395 } 396 397 #include "PPCGenDisassemblerTables.inc" 398 399 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 400 ArrayRef<uint8_t> Bytes, 401 uint64_t Address, raw_ostream &OS, 402 raw_ostream &CS) const { 403 // Get the four bytes of the instruction. 404 Size = 4; 405 if (Bytes.size() < 4) { 406 Size = 0; 407 return MCDisassembler::Fail; 408 } 409 410 // Read the instruction in the proper endianness. 411 uint32_t Inst = IsLittleEndian ? support::endian::read32le(Bytes.data()) 412 : support::endian::read32be(Bytes.data()); 413 414 if (STI.getFeatureBits()[PPC::FeatureQPX]) { 415 DecodeStatus result = 416 decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI); 417 if (result != MCDisassembler::Fail) 418 return result; 419 } 420 421 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 422 } 423 424