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  /external/swiftshader/third_party/LLVM/utils/TableGen/
CodeGenInstruction.cpp 36 if (Init->getDef()->getName() != "outs")
45 if (Init->getDef()->getName() != "ins")
67 Record *Rec = Arg->getDef();
85 ->getDef()->getName() != "ops")
416 if (ADI && ADI->getDef() == InstOpRec) {
422 ResOp = ResultOperand(Result->getArgName(AliasOpNo), ADI->getDef());
427 if (ADI && ADI->getDef()->isSubClassOf("Register")) {
432 InstOpRec = dynamic_cast<DefInit*>(DI->getArg(0))->getDef();
442 .contains(T.getRegBank().getReg(ADI->getDef())))
443 throw TGError(Loc, "fixed register " + ADI->getDef()->getName()
    [all...]
PseudoLoweringEmitter.cpp 34 if (DI->getDef()->isSubClassOf("Register") ||
35 DI->getDef()->getName() == "zero_reg") {
37 OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
46 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
48 "Pseudo operand type '" + DI->getDef()->getName() +
88 Record *Operator = OpDef->getDef();
SetTheory.cpp 170 dynamic_cast<DefInit&>(*Expr->getOperator()).getDef()->getRecords();
177 Record *Rec = Records.getDef(OS.str());
228 if (const RecVec *Result = expand(Def->getDef()))
230 Elts.insert(Def->getDef());
245 Operator *Op = Operators.lookup(OpInit->getDef()->getName());
CodeGenRegisters.cpp 103 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
112 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
116 SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef());
124 SubRegs[BaseIdxInit->getDef()] = R2;
309 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
317 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
352 assert(!getDef() && "Only synthesized classes can inherit properties");
503 if (!RegClasses[rci]->getDef())
576 if (Record *Def = RC->getDef())
CodeGenDAGPatterns.cpp 746 Record *Def = Pred->getDef();
870 !static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef()
874 getValueType(static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef());
    [all...]
CodeGenRegisters.h 121 Record *getDef() const { return TheDef; }
  /external/llvm/utils/TableGen/
CodeGenInstruction.cpp 36 if (Init->getDef()->getName() != "outs")
45 if (Init->getDef()->getName() != "ins")
69 Record *Rec = Arg->getDef();
90 cast<DefInit>(MIOpInfo->getOperator())->getDef()->getName() != "ops")
446 Record *ResultRecord = ADI ? ADI->getDef() : nullptr;
448 if (ADI && ADI->getDef() == InstOpRec) {
463 if (ADI && ADI->getDef()->isSubClassOf("RegisterOperand"))
464 ADI = ADI->getDef()->getValueAsDef("RegClass")->getDefInit();
466 if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) {
470 .hasSubClass(&T.getRegisterClass(ADI->getDef())))
    [all...]
OptParserEmitter.cpp 181 OS << getOptionName(*DI->getDef());
226 GroupFlags = DI->getDef()->getValueAsListInit("Flags");
227 OS << getOptionName(*DI->getDef());
234 OS << getOptionName(*DI->getDef());
259 << cast<DefInit>(I)->getDef()->getName();
263 << cast<DefInit>(I)->getDef()->getName();
PseudoLoweringEmitter.cpp 81 if (DI->getDef()->isSubClassOf("Register") ||
82 DI->getDef()->getName() == "zero_reg") {
84 OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
95 "Pseudo operand type '" + DI->getDef()->getName() +
135 Record *Operator = OpDef->getDef();
CodeGenDAGPatterns.cpp 875 Record *Def = Pred->getDef();
    [all...]
  /external/mesa3d/src/gallium/drivers/nouveau/codegen/
nv50_ir_lowering_nvc0.cpp 51 def[0] = bld.mkMovToReg(0, i->getSrc(0))->getDef(0);
52 def[1] = bld.mkMovToReg(1, i->getSrc(1))->getDef(0);
60 bld.mkMov(i->getDef(0), def[(i->op == OP_DIV) ? 0 : 1]);
80 Value *src[2], *dst[2], *def = i->getDef(0);
401 prev->setSrc(prev->srcCount(), useVec[i].tex->getDef(0));
407 bar->setSrc(bar->srcCount(), useVec[i].tex->getDef(0));
592 if (!i->getDef(0)->refCount())
    [all...]
nv50_ir_lowering_nv50.cpp 180 bld->mkOp2(OP_UNION, mul->sType, mul->getDef(0), rr[5], rr[6]);
182 bld->mkMov(mul->getDef(0), r[4]);
185 bld->mkMov(mul->getDef(0), t[3]);
415 i->getDef(0)->reg.size = 2; // $aX are only 16 bit
448 arl = bld.mkOp2(OP_SHL, TYPE_U32, i->getDef(0), bld.getSSA(), bld.mkImm(0));
457 Value *def = mul->getDef(0);
466 Value *res = cloneShallow(func, mul->getDef(0));
469 add->setSrc(0, mul->getDef(0));
586 if (insn->defExists(0) && insn->getDef(0)->reg.file == FILE_ADDRESS)
676 tid = bld.mkMov(bld.getScratch(), arg, TYPE_U32)->getDef(0)
    [all...]
nv50_ir_peephole.cpp 53 if (!getDef(0)->equals(getSrc(0)))
74 if (getDef(d)->refCount() || getDef(d)->reg.data.id >= 0)
110 if (mov->getDef(0)->reg.data.id < 0 && si && si->op != OP_PHI) {
273 if (ld->getDef(0)->refCount() == 0)
713 i->setSrc(1, bld.mkMov(bld.getSSA(type), i->getSrc(0), type)->getDef(0));
862 mul2->def(0).replace(mul1->getDef(0), false);
869 mul2->def(0).replace(mul1->getDef(0), false);
877 if (mul2->getDef(0)->refCount() == 1 && !mul2->saturate) {
881 insn = (*mul2->getDef(0)->uses.begin())->getInsn()
    [all...]
nv50_ir_ra.cpp 471 LValue *tmp = new_LValue(func, phi->getDef(0)->asLValue());
517 LValue *tmp = new_LValue(func, cal->getDef(d)->asLValue());
523 mov->setDef(0, cal->getDef(d));
601 bb->liveSet.clr(i->getDef(d)->id);
607 bb->liveSet.clr(i->getDef(0)->id);
656 bb->liveSet.clr(i->getDef(0)->id);
677 bb->liveSet.clr(i->getDef(d)->id);
678 if (i->getDef(d)->reg.data.id >= 0) // add hazard for fixed regs
679 i->getDef(d)->livei.extend(i->serial, i->serial);
1023 LValue *rep = (split ? insn->getSrc(0) : insn->getDef(0))->asLValue()
    [all...]
nv50_ir_lowering_gm107.cpp 170 mov = bld.mkMov(def[c][l], tex->getDef(c));
177 Instruction *u = bld.mkOp(OP_UNION, TYPE_U32, i->getDef(c));
213 insn->setSrc(0, shfl->getDef(0));
nv50_ir.cpp 769 i->setDef(d, pol.get(getDef(d)));
794 if (getDef(i)->reg.file != getDef(d)->reg.file)
868 if (getDef(d)->inFile(FILE_PREDICATE) || getDef(d)->inFile(FILE_FLAGS))
878 if (getDef(d)->interfers(i->getSrc(s)))
888 if (getDef(d)->interfers(i->getDef(c)))
nv50_ir_build_util.cpp 188 insn->getDef(0)->reg.data.id = id;
292 val = mkMov(getSSA(halfSize * 2), val, fTy)->getDef(0);
595 i->setDef(0, cloneShallow(fn, i->getDef(0)));
596 i->getDef(0)->reg.size = 4;
601 hi->getDef(0)->reg.data.id++;
  /external/clang/utils/TableGen/
ClangSACheckersEmitter.cpp 33 return isHidden(*DI->getDef());
47 name = getPackageFullName(DI->getDef());
135 package = DI->getDef();
156 Record *parentPackage = DI->getDef();
162 recordGroupMap[DI->getDef()]->Checkers.insert(R);
169 addPackageToCheckerGroup(packages[i], DI->getDef(), recordGroupMap);
210 OS << groupToSortIndex[DI->getDef()] << ", ";
238 OS << groupToSortIndex[DI->getDef()] << ", ";
ClangDiagnosticsEmitter.cpp 86 std::string CatName = getCategoryFromDiagGroup(Group->getDef(),
176 std::string GroupName = DI->getDef()->getValueAsString("GroupName");
232 const Record *NextDiagGroup = GroupInit->getDef();
263 const Record *NextDiagGroup = GroupInit->getDef();
276 SrcMgr.PrintMessage(GroupInit->getDef()->getLoc().front(),
404 const Record *GroupRec = Group->getDef();
423 if (groupInPedantic(Group->getDef()))
520 const Record *GroupRec = Group->getDef();
552 DiagsInGroup.find(DI->getDef()->getValueAsString("GroupName"));
    [all...]
  /external/llvm/lib/TableGen/
SetTheory.cpp 204 cast<DefInit>(Expr->getOperator())->getDef()->getRecords();
215 Record *Rec = Records.getDef(OS.str());
275 if (const RecVec *Result = expand(Def->getDef()))
277 Elts.insert(Def->getDef());
292 auto I = Operators.find(OpInit->getDef()->getName());
  /external/llvm/lib/Analysis/
MemoryDependenceAnalysis.cpp 200 return MemDepResult::getDef(Inst);
389 return MemDepResult::getDef(U);
490 return MemDepResult::getDef(II);
551 return MemDepResult::getDef(Inst);
578 return MemDepResult::getDef(Inst);
618 return MemDepResult::getDef(Inst);
633 return MemDepResult::getDef(Inst);
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Analysis/
MemoryDependenceAnalysis.cpp 226 return MemDepResult::getDef(Inst);
370 return MemDepResult::getDef(II);
407 return MemDepResult::getDef(Inst);
434 return MemDepResult::getDef(Inst);
459 return MemDepResult::getDef(Inst);
476 return MemDepResult::getDef(Inst);
    [all...]
  /external/swiftshader/third_party/LLVM/lib/TableGen/
Record.cpp 363 if (!DI->getDef()->isSubClassOf(Rec))
640 return DI->getDef();
748 return StringInit::get(LHSd->getDef()->getName());
788 if (Record *D = (CurRec->getRecords()).getDef(Name))
895 if (LOp == 0 || ROp == 0 || LOp->getDef() != ROp->getDef())
    [all...]
  /external/llvm/include/llvm/Analysis/
MemoryDependenceAnalysis.h 122 static MemDepResult getDef(Instruction *Inst) {
  /external/swiftshader/third_party/LLVM/include/llvm/Analysis/
MemoryDependenceAnalysis.h 105 static MemDepResult getDef(Instruction *Inst) {

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