| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCFrameLowering.h | 55 static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) {
57 return isPPC64 ? 16 : 8;
59 return isPPC64 ? 16 : 4;
64 static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
71 return isPPC64 ? -8U : -4U;
74 return isPPC64 ? -8U : -4U;
79 static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) {
80 if (isDarwinABI || isPPC64)
81 return 6 * (isPPC64 ? 8 : 4);
89 static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI)
[all...] |
| PPCSubtarget.h | 65 bool IsPPC64;
108 return isPPC64() ? "E-p:64:64-f64:64:64-i64:64:64-f128:64:128-n32:64"
112 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
114 bool isPPC64() const { return IsPPC64; }
|
| PPCFrameLowering.cpp | 204 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
288 bool isPPC64 = Subtarget.isPPC64();
297 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
307 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
311 if (isPPC64) {
352 if (!isPPC64) {
437 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
443 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
449 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR)
[all...] |
| PPCAsmPrinter.cpp | 384 if (!Subtarget.isPPC64()) // linux/ppc32 - Normal entry label.
402 bool isPPC64 = TD->getPointerSizeInBits() == 64;
404 if (isPPC64 && !TOC.empty()) {
438 if (Subtarget.isPPC64() && Directive < PPC::DIR_970)
483 bool isPPC64 = TM.getTargetData()->getPointerSizeInBits() == 64;
518 if (isPPC64)
531 if (isPPC64)
555 if (isPPC64)
567 if (isPPC64)
578 bool isPPC64 = TM.getTargetData()->getPointerSizeInBits() == 64
[all...] |
| PPCRegisterInfo.cpp | 66 return ((EnablePPC32RS && !Subtarget.isPPC64()) ||
67 (EnablePPC64RS && Subtarget.isPPC64()));
72 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
73 ST.isPPC64() ? 0 : 1,
74 ST.isPPC64() ? 0 : 1),
97 if (Subtarget.isPPC64())
214 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
217 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs;
246 if (Subtarget.isPPC64()) {
286 bool is64Bit = Subtarget.isPPC64();
[all...] |
| PPCISelLowering.cpp | 78 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4);
222 && !TM.getSubtarget<PPCSubtarget>().isPPC64()) {
375 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
[all...] |
| PPCTargetMachine.cpp | 81 if (Subtarget.isPPC64())
|
| PPCISelDAGToDAG.cpp | 614 bool isPPC64 = (PtrVT == MVT::i64);
630 if (isPPC64) break;
654 if (isPPC64) break;
663 if (isPPC64) break;
[all...] |
| PPCInstrInfo.cpp | 380 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
381 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 44 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64);
45 unsigned Flavour = isPPC64 ? 0 : 1;
46 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
62 bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
66 MAI = new PPCMCAsmInfoDarwin(isPPC64);
68 MAI = new PPCLinuxMCAsmInfo(isPPC64);
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 54 bool isPPC64 =
56 unsigned Flavour = isPPC64 ? 0 : 1;
57 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
71 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
76 MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
78 MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
81 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
|
| PPCMCCodeEmitter.cpp | 326 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
327 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 42 return STI.isPPC64() ? 16 : 8;
44 return STI.isPPC64() ? 16 : 4;
58 return STI.isPPC64() ? -8U : -4U;
61 return STI.isPPC64() ? -8U : -4U;
65 if (STI.isDarwinABI() || STI.isPPC64())
66 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
74 return STI.isPPC64() ? -16U : -8U;
77 return STI.isPPC64()
96 if (Subtarget.isPPC64()) {
236 if (Subtarget.isPPC64()) {
[all...] |
| PPCAsmPrinter.cpp | 451 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
452 (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
455 ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) ||
456 (!Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::R3)) &&
459 if (!Subtarget->isPPC64() && !Subtarget->isDarwin() &&
469 MCInstBuilder(Subtarget->isPPC64() ?
480 bool isPPC64 = Subtarget->isPPC64();
758 assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
777 TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ)
[all...] |
| PPCSubtarget.cpp | 53 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
131 if (IsPPC64 && has64BitSupport())
197 CriticalPathRCs.push_back(isPPC64() ?
251 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
|
| PPCRegisterInfo.cpp | 61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
62 TM.isPPC64() ? 0 : 1,
63 TM.isPPC64() ? 0 : 1),
91 if (TM.isPPC64())
96 if (TM.isPPC64())
113 return TM.isPPC64()
119 if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
125 return TM.isPPC64()
140 if (!TM.isPPC64())
172 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMas
[all...] |
| PPCTargetMachine.h | 55 bool isPPC64() const {
|
| PPCInstrInfo.cpp | 452 bool isPPC64 = Subtarget.isPPC64();
504 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
515 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
572 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
586 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
648 bool isPPC64 = Subtarget.isPPC64();
656 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
657 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB)
[all...] |
| PPCISelLowering.cpp | 78 bool isPPC64 = Subtarget.isPPC64();
79 setMinStackArgumentAlignment(isPPC64 ? 8:4);
115 if (isPPC64 || Subtarget.hasFPCVT()) {
118 isPPC64 ? MVT::i64 : MVT::i32);
121 isPPC64 ? MVT::i64 : MVT::i32);
266 if (Subtarget.hasDirectMove() && isPPC64) {
314 if (isPPC64) {
333 if (Subtarget.isSVR4ABI() && !isPPC64)
378 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
[all...] |
| PPCSubtarget.h | 95 bool IsPPC64;
199 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
201 bool isPPC64() const;
|
| PPCTLSDynamicCall.cpp | 55 bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
|
| PPCTargetTransformInfo.cpp | 175 if (ST->isPPC64() &&
234 if (ST->isPPC64())
|
| PPCISelDAGToDAG.cpp | [all...] |
| PPCFastISel.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 245 bool IsPPC64;
251 bool isPPC64() const { return IsPPC64; }
296 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
328 bool IsPPC64;
361 IsPPC64 = o.IsPPC64;
389 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
390 bool isPPC64() const { return IsPPC64; }
[all...] |
