/external/llvm/lib/IR/ |
Constants.cpp | 1459 Instruction::CastOps opc = Instruction::CastOps(oc); local [all...] |
/external/mesa3d/src/gallium/drivers/etnaviv/ |
etnaviv_compiler.c | 1037 uint8_t opc; member in struct:instr_translater 1843 const unsigned opc = inst->Instruction.Opcode; local [all...] |
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
ir3.h | 133 opc_t opc; member in struct:ir3_instruction 467 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc); 469 opc_t opc, int nreg); 530 return (opc_cat(instr->opc) == 0); 535 return instr->opc == OPC_KILL; 540 return instr->opc == OPC_NOP; 560 switch (instr->opc) { 573 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3); 578 return (opc_cat(instr->opc) == 4) [all...] |
ir3_compiler_nir.c | 1398 opc_t opc = 0; local [all...] |
instr-a3xx.h | 32 /* size of largest OPC field of all the instruction categories: */ 35 #define _OPC(cat, opc) (((cat) << NOPC_BITS) | opc) 212 #define opc_cat(opc) ((int)((opc) >> NOPC_BITS)) 213 #define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1))) 312 uint32_t opc : 4; member in struct:PACKED 418 uint32_t opc : 6; member in struct:PACKED 478 uint32_t opc : 4 member in struct:PACKED 535 uint32_t opc : 6; member in struct:PACKED 584 uint32_t opc : 5; member in struct:PACKED 666 uint32_t opc : 5; member in struct:PACKED::PACKED [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | 3126 unsigned opc = fieldFromInstruction32(Insn, 4, 28); local [all...] |
/external/swiftshader/third_party/LLVM/lib/VMCore/ |
Constants.cpp | 1231 Instruction::CastOps opc = Instruction::CastOps(oc); local [all...] |
/external/valgrind/VEX/priv/ |
host_amd64_defs.c | 2455 UInt \/*irno,*\/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; local [all...] |
host_arm_defs.c | 4044 UInt opc, opc1, opc2; local [all...] |
/prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Target/ |
TargetLowering.h | 666 unsigned opc = 0; // target opcode member in struct:llvm::TargetLoweringBase::IntrinsicInfo [all...] |
/prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Target/ |
TargetLowering.h | 666 unsigned opc = 0; // target opcode member in struct:llvm::TargetLoweringBase::IntrinsicInfo [all...] |
/prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Target/ |
TargetLowering.h | 666 unsigned opc = 0; // target opcode member in struct:llvm::TargetLoweringBase::IntrinsicInfo [all...] |
/prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
TargetLowering.h | 666 unsigned opc = 0; // target opcode member in struct:llvm::TargetLoweringBase::IntrinsicInfo [all...] |
/prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Target/ |
TargetLowering.h | 666 unsigned opc = 0; // target opcode member in struct:llvm::TargetLoweringBase::IntrinsicInfo [all...] |
/prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Target/ |
TargetLowering.h | 666 unsigned opc = 0; // target opcode member in struct:llvm::TargetLoweringBase::IntrinsicInfo [all...] |
/prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Target/ |
TargetLowering.h | 666 unsigned opc = 0; // target opcode member in struct:llvm::TargetLoweringBase::IntrinsicInfo [all...] |
/prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
TargetLowering.h | 666 unsigned opc = 0; // target opcode member in struct:llvm::TargetLoweringBase::IntrinsicInfo [all...] |
/toolchain/binutils/binutils-2.25/gas/config/ |
tc-bfin.c | 2064 int opc = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask); local 2245 int opc = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask); local [all...] |
tc-m68hc11.c | 474 struct m68hc11_opcode_def *opc; 478 opc = m68hc11_opcode_defs; 479 if (opc == 0 || m68hc11_nb_opcode_defs == 0) 484 for (i = 0; i < m68hc11_nb_opcode_defs; i++, opc++) 487 opc->opcode->name, 488 opc->nb_modes, 489 opc->min_operands, opc->max_operands, opc->format, opc->used) 473 struct m68hc11_opcode_def *opc; local 608 struct m68hc11_opcode_def *opc = 0; local 1012 struct m68hc11_opcode_def *opc; local 2814 struct m68hc11_opcode_def *opc; local [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
v850-opc.c | 604 unsigned long msb, lsb, opc, ret; 609 opc = 0; 616 opc = 0x0090; 618 opc = 0x00b0; 620 opc = 0x00d0; 629 ret = (insn & 0x0000ffff) | ((opc | msb_expand | lsb_expand) << 16); 603 unsigned long msb, lsb, opc, ret; local [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelDAGToDAG.cpp | 107 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc); 110 SDValue &Offset, SDValue &Opc); 112 SDValue &Opc) { 113 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE; 117 SDValue &Opc) { 118 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP; 122 SDValue &Opc) { 123 SelectAddrMode2Worker(N, Base, Offset, Opc); 124 // return SelectAddrMode2ShOp(N, Base, Offset, Opc); 137 SDValue &Offset, SDValue &Opc); 2970 unsigned opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL; local [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | 4006 unsigned opc = fieldFromInstruction(Insn, 4, 28); local [all...] |
/external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
instr-a2xx.h | 212 instr_cf_opc_t opc : 4; member in struct:PACKED 221 instr_cf_opc_t opc : 4; member in struct:PACKED 234 instr_cf_opc_t opc : 4; member in struct:PACKED 243 instr_cf_opc_t opc : 4; member in struct:PACKED 253 instr_cf_opc_t opc : 4; member in struct:PACKED::PACKED 312 instr_fetch_opc_t opc : 5; member in struct:PACKED 346 instr_fetch_opc_t opc : 5; member in struct:PACKED 381 instr_fetch_opc_t opc : 5; member in struct:PACKED::PACKED
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/external/pcre/dist2/src/sljit/ |
sljitNativeTILEGX_64.c | 524 void insert_nop(tilegx_mnemonic opc, int line) 530 opcode = &tilegx_opcodes[opc]; 566 tilegx_mnemonic opc = inst_buf[0].opcode->can_bundle local 568 insert_nop(opc, __LINE__); 744 static sljit_s32 push_4_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int op1, int op2, int op3, int line) 749 const struct tilegx_opcode* opcode = &tilegx_opcodes[opc]; 764 static sljit_s32 push_3_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int op1, int op2, int line) 769 const struct tilegx_opcode* opcode = &tilegx_opcodes[opc]; 777 switch (opc) { 816 printf("unrecoginzed opc: %s\n", opcode->name) [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
MipsISelLowering.cpp | 424 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : local 428 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 640 unsigned opc = N->getOpcode(); local 642 switch (opc) { 715 bool isFPCmp, unsigned Opc) { 754 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 756 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) [all...] |