| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| fp.convert.ll | 506 ; MIPS32O2: mtc1 $a0, $[[REG:f[0-9]+]]
|
| /external/v8/src/compiler/mips64/ |
| code-generator-mips64.cc | 216 __ mtc1(at, result_);
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.cc | 2318 void Assembler::mtc1(Register rt, FPURegister fs) { function in class:v8::Assembler
[all...] |
| constants-mips.h | 499 MTC1 = ((0U << 3) + 4) << 21,
[all...] |
| assembler-mips.h | 869 void mtc1(Register rt, FPURegister fs);
[all...] |
| macro-assembler-mips.h | 301 mtc1(src_low, dst);
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.cc | 2641 void Assembler::mtc1(Register rt, FPURegister fs) { function in class:v8::internal::Assembler
[all...] |
| constants-mips64.h | 528 MTC1 = ((0U << 3) + 4) << 21,
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.cc | [all...] |
| assembler_mips_test.cc | 730 TEST_F(AssemblerMIPSTest, Mtc1) {
731 DriverStr(RepeatRF(&mips::MipsAssembler::Mtc1, "mtc1 ${reg1}, ${reg2}"), "Mtc1");
[all...] |
| assembler_mips.h | 455 void Mtc1(Register rt, FRegister fs);
[all...] |
| /external/v8/src/crankshaft/mips/ |
| lithium-codegen-mips.cc | 465 __ mtc1(at, flt_scratch);
[all...] |
| /art/compiler/optimizing/ |
| code_generator_mips64.cc | [all...] |
| intrinsics_mips64.cc | 194 __ Mtc1(in, out);
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | 635 TEST_F(AssemblerMIPS64Test, Mtc1) {
636 DriverStr(RepeatRF(&mips64::Mips64Assembler::Mtc1, "mtc1 ${reg1}, ${reg2}"), "Mtc1");
[all...] |
| assembler_mips64.h | 639 void Mtc1(GpuRegister rt, FpuRegister fs);
[all...] |
| /art/disassembler/ |
| disassembler_mips.cc | 375 { kFpMask | (0x1f << 21), kCop1 | (0x04 << 21), "mtc1", "Td" },
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 277 // transferred with mtc1 which is redirected to the upper half of the even
[all...] |
| MipsFastISel.cpp | 350 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceTargetLoweringMIPS32.cpp | [all...] |
| /external/valgrind/VEX/priv/ |
| host_mips_isel.c | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| ChangeLog | 340 (dmtc1, mtc1, mthc1): Add COD attribute.
|
| ChangeLog-0001 | [all...] |
| /art/runtime/arch/mips64/ |
| quick_entrypoints_mips64.S | 971 mtc1 $t3, $\fpu
983 mtc1 $t3, $\fpu
[all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_mips.S | 188 mtc1 r, fhi
[all...] |
