| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| armv1-bad.l | 6 [^:]*:8: Warning: writeback of base register is UNPREDICTABLE
7 [^:]*:9: Warning: writeback of base register when in register list is UNPREDICTABLE
8 [^:]*:10: Warning: writeback of base register is UNPREDICTABLE
9 [^:]*:12: Warning: if writeback register is in list, it must be the lowest reg in the list
|
| /external/v8/src/x64/ |
| assembler-x64.h | 91 // the register initialization to depend on the particular initialization
94 // "initialization". Also, the Register objects cannot be const as this
106 struct Register {
117 static Register from_code(int code) {
120 Register r = {code};
124 bool is(Register reg) const { return reg_code == reg.reg_code; }
135 // Return the high bit of the register code as a 0 or 1. Used often
138 // Return the 3 low bits of the register code. Used when encoding registers
148 #define DECLARE_REGISTER(R) const Register R = {Register::kCode_##R}
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Include/Library/ |
| PciCf8Lib.h | 24 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
28 unused upper bits of Bus, Device, Function and Register are stripped prior to
34 @param Register PCI Register number. Range 0..255.
50 If the register specified by Address >= 0x100, then ASSERT().
53 Register.
71 Reads an 8-bit PCI configuration register.
73 Reads and returns the 8-bit PCI configuration register specified by Address.
78 If the register specified by Address >= 0x100, then ASSERT().
81 Register.
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Library/ |
| EdkIIGluePciCf8Lib.h | 28 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
32 unused upper bits of Bus, Device, Function and Register are stripped prior to
38 @param Register PCI Register number. Range 0..255.
47 Reads an 8-bit PCI configuration register.
49 Reads and returns the 8-bit PCI configuration register specified by Address.
54 If the register specified by Address >= 0x100, then ASSERT().
57 Register.
59 @return The read value from the PCI configuration register.
69 Writes an 8-bit PCI configuration register.
[all...] |
| /external/v8/src/interpreter/ |
| bytecode-register-optimizer.h | 30 // Perform explicit register transfer operations.
31 void DoLdar(Register input, BytecodeSourceInfo source_info) {
35 void DoStar(Register output, BytecodeSourceInfo source_info) {
39 void DoMov(Register input, Register output, BytecodeSourceInfo source_info) {
54 // - a jump bytecode (as the register equivalents at the jump target
63 // accumulator is special and no other register can be materialized
77 void PrepareOutputRegister(Register reg);
82 // Returns an equivalent register to |reg| to be used as an input operand.
83 Register GetInputRegister(Register reg)
[all...] |
| /external/v8/src/ppc/ |
| macro-assembler-ppc.cc | 15 #include "src/register-configuration.h"
35 void MacroAssembler::Jump(Register target) {
41 void MacroAssembler::JumpToJSEntry(Register target) {
79 int MacroAssembler::CallSize(Register target) { return 2 * kInstrSize; }
82 void MacroAssembler::Call(Register target) {
87 // branch via link register and set LK bit for return point
95 void MacroAssembler::CallJSEntry(Register target) {
177 void MacroAssembler::Drop(Register count, Register scratch) {
191 void MacroAssembler::Move(Register dst, Handle<Object> value)
[all...] |
| code-stubs-ppc.h | 21 Register left, Register right,
22 Register scratch1,
23 Register scratch2,
24 Register scratch3);
28 Register left, Register right,
29 Register scratch1,
30 Register scratch2);
34 Register left, Register right
[all...] |
| /external/v8/src/regexp/arm64/ |
| regexp-macro-assembler-arm64.h | 117 // Register parameters stored by setup code.
125 // First position register address on the stack. Following positions are
138 // We are using x0 to x7 as a register cache. Each hardware register must
144 // current position, into the current-character register.
154 void CallCheckStackGuardState(Register scratch);
156 // Location of a 32 bit position register.
160 MemOperand capture_location(int register_index, Register scratch);
162 // Register holding the current input position as negative offset from
164 Register current_input_offset() { return w21;
[all...] |
| /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/ |
| core_cmFunc.h | 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
58 /** \brief Get Control Register
60 This function returns the content of the Control Register.
62 \return Control Register value
66 register uint32_t __regControl __ASM("control");
71 /** \brief Set Control Register
73 This function writes the given value to the Control Register.
75 \param [in] control Control Register value to set
79 register uint32_t __regControl __ASM("control");
84 /** \brief Get IPSR Register
[all...] |
| /external/llvm/test/TableGen/ |
| MultiPat.td | 41 class Register<string n> {
45 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
47 list<Register> MemberList = regList;
50 def XMM0: Register<"xmm0">;
51 def XMM1: Register<"xmm1">;
52 def XMM2: Register<"xmm2">;
53 def XMM3: Register<"xmm3">;
54 def XMM4: Register<"xmm4">;
55 def XMM5: Register<"xmm5">;
56 def XMM6: Register<"xmm6">
[all...] |
| Slice.td | 31 class Register<string n> {
35 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
37 list<Register> MemberList = regList;
40 def XMM0: Register<"xmm0">;
41 def XMM1: Register<"xmm1">;
42 def XMM2: Register<"xmm2">;
43 def XMM3: Register<"xmm3">;
44 def XMM4: Register<"xmm4">;
45 def XMM5: Register<"xmm5">;
46 def XMM6: Register<"xmm6">
[all...] |
| TargetInstrSpec.td | 38 class Register<string n> {
42 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
44 list<Register> MemberList = regList;
47 def XMM0: Register<"xmm0">;
48 def XMM1: Register<"xmm1">;
49 def XMM2: Register<"xmm2">;
50 def XMM3: Register<"xmm3">;
51 def XMM4: Register<"xmm4">;
52 def XMM5: Register<"xmm5">;
53 def XMM6: Register<"xmm6">
[all...] |
| /external/swiftshader/third_party/LLVM/test/TableGen/ |
| MultiPat.td | 41 class Register<string n> {
45 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
47 list<Register> MemberList = regList;
50 def XMM0: Register<"xmm0">;
51 def XMM1: Register<"xmm1">;
52 def XMM2: Register<"xmm2">;
53 def XMM3: Register<"xmm3">;
54 def XMM4: Register<"xmm4">;
55 def XMM5: Register<"xmm5">;
56 def XMM6: Register<"xmm6">
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm_vixl.h | 58 void CompareAndBranchIfZero(vixl32::Register rn,
61 void CompareAndBranchIfNonZero(vixl32::Register rn,
75 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
100 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
111 void Rrx(vixl32::Register rd, vixl32::Register rn) {
116 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm)
[all...] |
| /external/llvm/test/MC/AArch64/ |
| trace-regs-diagnostics.s | 5 // CHECK: error: expected readable system register
8 // CHECK-NEXT: error: expected readable system register
49 // CHECK: error: expected writable system register or pstate
52 // CHECK-NEXT: error: expected writable system register or pstate
55 // CHECK-NEXT: error: expected writable system register or pstate
58 // CHECK-NEXT: error: expected writable system register or pstate
61 // CHECK-NEXT: error: expected writable system register or pstate
64 // CHECK-NEXT: error: expected writable system register or pstate
67 // CHECK-NEXT: error: expected writable system register or pstate
70 // CHECK-NEXT: error: expected writable system register or pstat
[all...] |
| /external/compiler-rt/lib/sanitizer_common/ |
| sanitizer_syscall_linux_aarch64.inc | 17 register u64 x8 asm("x8") = nr;
18 register u64 x0 asm("x0");
29 register u64 x8 asm("x8") = nr;
30 register u64 x0 asm("x0") = arg1;
41 register u64 x8 asm("x8") = nr;
42 register u64 x0 asm("x0") = arg1;
43 register u64 x1 asm("x1") = arg2;
54 register u64 x8 asm("x8") = nr;
55 register u64 x0 asm("x0") = arg1;
56 register u64 x1 asm("x1") = arg2
[all...] |
| /external/v8/src/s390/ |
| code-stubs-s390.h | 19 Register left, Register right,
20 Register scratch1,
21 Register scratch2,
22 Register scratch3);
26 Register left, Register right,
27 Register scratch1,
28 Register scratch2);
32 Register left, Register right
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.h | 80 // the register initialization to depend on the particular initialization
83 // "initialization". Also, the Register objects cannot be const as this
97 // Implementation of Register and FPURegister.
99 struct Register {
100 static const int kCpRegister = 23; // cp (s7) is the 23rd register.
123 static Register from_code(int code) {
126 Register r = {code};
130 bool is(Register reg) const { return reg_code == reg.reg_code; }
144 // s7: context register
147 #define DECLARE_REGISTER(R) const Register R = {Register::kCode_##R}
[all...] |
| /external/v8/src/arm64/ |
| code-stubs-arm64.h | 19 MacroAssembler* masm, Register left, Register right, Register scratch1,
20 Register scratch2, Register scratch3, Register scratch4);
24 Register left, Register right,
25 Register scratch1,
26 Register scratch2
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/AArch64/ |
| AArch64ArchTimerSupport.S | 51 mrs x0, cntpct_el0 // Read CNTPCT (Physical counter register)
56 mrs x0, cntkctl_el1 // Read CNTK_CTL (Timer PL1 Control Register)
61 msr cntkctl_el1, x0 // Write to CNTK_CTL (Timer PL1 Control Register)
66 mrs x0, cntp_tval_el0 // Read CNTP_TVAL (PL1 physical timer value register)
71 msr cntp_tval_el0, x0 // Write to CNTP_TVAL (PL1 physical timer value register)
76 mrs x0, cntp_ctl_el0 // Read CNTP_CTL (PL1 Physical Timer Control Register)
81 msr cntp_ctl_el0, x0 // Write to CNTP_CTL (PL1 Physical Timer Control Register)
86 mrs x0, cntv_tval_el0 // Read CNTV_TVAL (Virtual Timer Value register)
91 msr cntv_tval_el0, x0 // Write to CNTV_TVAL (Virtual Timer Value register)
96 mrs x0, cntv_ctl_el0 // Read CNTV_CTL (Virtual Timer Control Register)
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/ArmV7/ |
| ArmV7ArchTimerSupport.asm | 28 mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)
32 mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)
36 mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)
40 mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)
44 mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)
48 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
52 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
56 mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)
60 mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)
64 mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| XhciReg.h | 23 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
30 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
35 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
36 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
37 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
38 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
39 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
40 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
41 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
42 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
[all...] |
| /external/jmdns/src/javax/jmdns/impl/ |
| NameRegister.java | 31 * @see javax.jmdns.impl.NameRegister#register(java.net.InetAddress, java.lang.String, javax.jmdns.impl.NameRegister.NameType)
34 public void register(InetAddress networkInterface, String name, NameType type) { method in class:NameRegister.UniqueNamePerInterface
65 * @see javax.jmdns.impl.NameRegister#register(java.net.InetAddress, java.lang.String, javax.jmdns.impl.NameRegister.NameType)
68 public void register(InetAddress networkInterface, String name, NameType type) { method in class:NameRegister.UniqueNameAcrossInterface
100 * Register a Name register.
102 * @param register
103 * new register
105 * the register can only be set once
107 public static void setRegistry(NameRegister register) throws IllegalStateException
140 public abstract void register(InetAddress networkInterface, String name, NameType type); method in interface:NameRegister
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| ghc-cc.ll | 5 @base = external global i64 ; assigned to register: r19
6 @sp = external global i64 ; assigned to register: r20
7 @hp = external global i64 ; assigned to register: r21
8 @r1 = external global i64 ; assigned to register: r22
9 @r2 = external global i64 ; assigned to register: r23
10 @r3 = external global i64 ; assigned to register: r24
11 @r4 = external global i64 ; assigned to register: r25
12 @r5 = external global i64 ; assigned to register: r26
13 @r6 = external global i64 ; assigned to register: r27
14 @splim = external global i64 ; assigned to register: r2
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| MachineLocation.h | 10 // frame. Locations will be one of two forms; a register or an address formed
11 // from a base address plus an offset. Register indirection can be specified by
29 bool IsRegister; // True if location is a register.
30 unsigned Register; // gcc/gdb register number.
31 int Offset; // Displacement if not register.
34 // The target register number for an abstract frame pointer. The value is
35 // an arbitrary value that doesn't collide with any real target register.
39 : IsRegister(false), Register(0), Offset(0) {}
41 : IsRegister(true), Register(R), Offset(0) {
[all...] |
