| /external/mesa3d/src/amd/common/ |
| ac_nir_to_llvm.c | 97 LLVMTypeRef v2i32; member in struct:nir_to_llvm_context
435 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
436 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
437 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
439 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
440 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
441 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
555 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 433 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64.
598 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 },
599 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 },
610 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
695 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 },
[all...] |
| /external/clang/test/CodeGen/ |
| systemz-abi-vector.c | 22 typedef __attribute__((vector_size(8))) int v2i32; typedef
86 v2i32 pass_v2i32(v2i32 arg) { return arg; }
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_shader.c | 812 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
851 const char *types[] = {"i32", "v2i32", "v4i32"};
937 const char *type_names[] = {"i32", "v2i32", "v4i32"};
944 arg_type = "v2i32";
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| masked_gather_scatter.ll | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 154 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
468 addDRTypeForNEON(MVT::v2i32);
578 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
591 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
601 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
635 MVT::v2i32}) {
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 351 // x86 this turns v1i64 = BITCAST i64 into v1i64 = BITCAST v2i32.
|
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedM1.td | 346 def : InstRW<[M1WriteNALU1], (instregex "^(TRN|UZP)[12](v8i8|v4i16|v2i32)")>;
|
| AArch64RegisterInfo.td | 396 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
|
| /external/swiftshader/third_party/LLVM/include/llvm/ |
| Intrinsics.td | 127 def llvm_v2i32_ty : LLVMType<v2i32>; // 2 x i32
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 276 // x86 this turns v1i64 = BITCAST i64 into v1i64 = BITCAST v2i32.
|
| /external/swiftshader/third_party/LLVM/lib/Target/ |
| TargetData.cpp | 152 setAlignment(VECTOR_ALIGN, 8, 8, 64); // v2i32, v1i64, ...
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vmul.ll | 144 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
168 declare <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
195 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
219 declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
775 %tmp4 = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp3)
828 %tmp4 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp3)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZInstrInfo.td | [all...] |
| SystemZISelDAGToDAG.cpp | 695 ResVT = MVT::v2i32;
|
| SystemZISelLowering.cpp | 51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
[all...] |
| /external/llvm/include/llvm/IR/ |
| Intrinsics.td | 198 def llvm_v2i32_ty : LLVMType<v2i32>; // 2 x i32
[all...] |
| /external/llvm/lib/IR/ |
| DataLayout.cpp | 173 { VECTOR_ALIGN, 64, 8, 8 }, // v2i32, v1i64, ...
|
| /external/llvm/lib/Target/PowerPC/ |
| README_P9.txt | 85 (set v2i64:$vD, (sext v2i32:$vB))
|
| /external/llvm/test/Analysis/CostModel/X86/ |
| alternate-shuffle-cost.ll | 11 ; 64-bit packed integer vectors (v2i32) are promoted to type v2i64.
|
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/IR/ |
| Intrinsics.td | 208 def llvm_v2i32_ty : LLVMType<v2i32>; // 2 x i32
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/IR/ |
| Intrinsics.td | 208 def llvm_v2i32_ty : LLVMType<v2i32>; // 2 x i32
[all...] |
