| /external/mesa3d/src/intel/vulkan/ |
| anv_intel.c | 75 /* FIXME: Need a way to use X tiling to allow scanout */
76 .tiling = VK_IMAGE_TILING_OPTIMAL,
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| anv_formats.c | 257 VkImageAspectFlags aspect, VkImageTiling tiling)
281 if (tiling == VK_IMAGE_TILING_OPTIMAL &&
457 VkImageTiling tiling,
477 * tiling.
479 if (tiling == VK_IMAGE_TILING_LINEAR) {
481 } else if (tiling == VK_IMAGE_TILING_OPTIMAL) {
528 if (tiling == VK_IMAGE_TILING_OPTIMAL &&
613 VkImageTiling tiling,
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| /hardware/intel/img/psb_video/src/ |
| psb_surface.c | 53 int tiling = GET_SURFACE_INFO_tiling(psb_surface); local
54 if (tiling)
75 if (tiling) {
120 if (tiling) {
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| psb_surface_attrib.c | 116 if (graphic_buffers->tiling)
271 unsigned int tiling
391 psb_surface->extra_info[7] = tiling;
425 unsigned int tiling
529 psb_surface->extra_info[7] = tiling;
771 int tiling; local
775 drv_debug_msg(VIDEO_DEBUG_GENERAL, "Create %d surface(%dx%d) with type %d, tiling is %d\n",
776 num_surfaces, width, height, attribute_tpi->type, attribute_tpi->tiling);
778 tiling = attribute_tpi->tiling;
[all...] |
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_resource_texture.c | 178 if (!is->debug.tiling)
216 tex->tiling = I915_TILE_X;
254 tex->tiling = I915_TILE_X;
938 tex->tiling = I915_TILE_NONE;
940 tex->tiling = i915_texture_tiling(is, tex);
961 &tex->tiling, buf_usage);
965 I915_DBG(DBG_TEXTURE, "%s: %p stride %u, blocks (%u, %u) tiling %s\n", __func__,
968 tex->total_nblocksy, get_tiling_string(tex->tiling));
987 enum i915_winsys_buffer_tile tiling; local
991 buffer = iws->buffer_from_handle(iws, whandle, template->height0, &tiling, &stride)
[all...] |
| i915_state_sampler.c | 282 ms3_tiling_bits(enum i915_winsys_buffer_tile tiling)
286 switch (tiling) {
339 | ms3_tiling_bits(tex->tiling));
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| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_texture.c | 1080 struct radeon_bo_metadata tiling = {}; local
1180 struct radeon_bo_metadata tiling = {}; local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| intel_blit.c | 42 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type) \
44 switch (tiling) { \
113 * tiling state would leak into other unsuspecting applications (like the X
123 /* Idle the blitter before we update how tiling is interpreted. */
152 if (mt->tiling)
191 enum isl_tiling tiling = intel_miptree_get_isl_tiling(mt); local
193 tiling, mt->cpp, mt->pitch,
197 if (tiling == ISL_TILING_LINEAR) {
201 * of the 48bit addressing. When Src Tiling is enabled (Bit_15
202 * enabled), this address must be 4KB-aligned. When Tiling is no
[all...] |
| intel_mipmap_tree.c | 106 unsigned tiling)
116 return tiling == I915_TILING_Y;
118 return tiling != I915_TILING_NONE;
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
586 intel_get_tile_dims(mt->tiling, mt->tr_mode, mt->cpp,
639 if (mt->tiling == (I915_TILING_Y | I915_TILING_X))
640 mt->tiling = I915_TILING_Y;
661 mt->cpp, &mt->tiling, &pitch,
666 mt->cpp, &mt->tiling, &pitch,
696 * handle Y-tiling, so we need to fall back to X
772 uint32_t tiling, swizzle; local
1233 uint32_t tiling = mt->tiling; local
1616 uint32_t tiling = I915_TILING_Y; local
1759 uint32_t tiling = I915_TILING_Y; local
1856 uint32_t tiling = I915_TILING_Y; local
[all...] |
| intel_screen.c | 320 uint32_t tiling, swizzle; local
321 drm_intel_bo_get_tiling(image->bo, &tiling, &swizzle);
323 if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) {
550 uint32_t tiling; local
554 tiling = I915_TILING_X;
558 tiling = I915_TILING_NONE;
562 tiling = I915_TILING_NONE;
570 width, height, cpp, &tiling,
1213 uint32_t tiling = I915_TILING_X; local
[all...] |
| /external/deqp/external/vulkancts/modules/vulkan/ycbcr/ |
| vktYCbCrCopyTests.cpp | 70 , tiling (tiling_)
77 vk::VkImageTiling tiling; member in struct:vkt::ycbcr::__anon16854::ImageConfig
103 const vk::VkFormatFeatureFlags features (config.src.tiling == vk::VK_IMAGE_TILING_OPTIMAL
127 const vk::VkFormatFeatureFlags features (config.dst.tiling == vk::VK_IMAGE_TILING_OPTIMAL
154 vk::VkImageTiling tiling)
168 tiling,
703 builder << (deUint32)config.format << (deUint32)config.tiling << config.disjoint << config.size[0] << config.size[1];
720 log << TestLog::Message << "Tiling: " << config.tiling << TestLog::EndMessage;
771 const vk::Unique<vk::VkImage> srcImage (createImage(vkd, device, config.src.format, config.src.size, config.src.disjoint, config.src.tiling));
[all...] |
| vktYCbCrConversionTests.cpp | [all...] |
| /external/deqp/external/vulkancts/modules/vulkan/memory/ |
| vktMemoryRequirementsTests.cpp | 639 , tiling (tiling_)
649 VkImageTiling tiling; member in struct:vkt::memory::__anon16606::ImageTestParams
760 params.tiling = VK_IMAGE_TILING_OPTIMAL;
765 params.tiling = VK_IMAGE_TILING_LINEAR;
769 if ((params.flags & VK_IMAGE_CREATE_SPARSE_RESIDENCY_BIT) && (params.tiling == VK_IMAGE_TILING_LINEAR))
850 result.check(m_currentTestImageInfo.tiling == VK_IMAGE_TILING_OPTIMAL || hostVisibleCoherentMemoryFound,
1798 const VkImageTiling tiling = tilings[tilingNdx].value; local
[all...] |
| /hardware/intel/img/hwcomposer/merrifield/ips/common/ |
| RotationBufferProvider.cpp | 143 int allignment = 16 * 2048; // tiling row stride aligned
201 vaSurfaceAttrib->tiling = payload->tiling;
245 ETRACE("Attributes: target: %d, width: %d, height %d, bufferHeight %d, tiling %d",
246 isTarget, width, height, bufferHeight, payload->tiling);
394 payload->tiling = 1;
529 payload->tiling = 1;
|
| /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/common/ |
| RotationBufferProvider.cpp | 143 int allignment = 16 * 2048; // tiling row stride aligned
200 vaSurfaceAttrib->tiling = payload->tiling;
244 ELOGTRACE("Attributes: target: %d, width: %d, height %d, bufferHeight %d, tiling %d",
245 isTarget, width, height, bufferHeight, payload->tiling);
393 payload->tiling = 1;
522 payload->tiling = 1;
|
| /hardware/intel/img/psb_video/src/android/ |
| psb_surface_gralloc.c | 229 psb_surface->extra_info[7] = external_buffers->tiling;
356 external_buffers->tiling = 0;
401 obj_surface->share_info->tiling = external_buffers->tiling;
485 psb_surface->extra_info[7] = external_buffers->tiling;
|
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| intel_mipmap_tree.c | 132 /* Some usages may want only one type of tiling, like depth miptrees (Y
146 /* If the width is much smaller than a tile, don't bother tiling. */
156 /* We don't have BLORP to handle Y-tiled blits, so use X-tiling. */
190 uint32_t tiling = intel_miptree_choose_tiling(intel, format, width0, local
193 bool y_or_x = tiling == (I915_TILING_Y | I915_TILING_X);
196 y_or_x ? I915_TILING_Y : tiling,
203 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
237 uint32_t tiling)
248 if (tiling != I915_TILING_NONE)
271 region->tiling = tiling
[all...] |
| intel_screen.c | 435 uint32_t tiling; local
438 tiling = I915_TILING_X;
442 tiling = I915_TILING_NONE;
446 tiling = I915_TILING_NONE;
454 intel_region_alloc(intelScreen, tiling, cpp, width, height, true);
676 image->region->tiling = parent->region->tiling;
1024 uint32_t tiling = I915_TILING_X; local
1029 &tiling, &aligned_pitch, flags);
1033 drm_intel_bo_get_tiling(buffer, &tiling, &swizzle_mode)
[all...] |
| intel_tex_subimage.c | 63 /* The blitter can't handle Y tiling */
64 if (intelImage->mt->region->tiling == I915_TILING_Y)
|
| /external/mesa3d/src/gallium/drivers/vc4/kernel/ |
| vc4_render_cl.c | 422 uint8_t tiling = VC4_GET_FIELD(surf->bits, local
470 if (tiling > VC4_TILING_FORMAT_LT) {
471 DRM_ERROR("Bad tiling format\n");
504 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
518 uint8_t tiling = VC4_GET_FIELD(surf->bits, local
545 if (tiling > VC4_TILING_FORMAT_LT) {
546 DRM_ERROR("Bad tiling format\n");
563 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
|
| /external/mesa3d/src/intel/isl/ |
| isl_surface_state.c | 141 if (isl_tiling_is_std_y(surf->tiling) ||
178 if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
182 * W-tiling is handled as modified Y-tiling. If you bind a 3-D
210 * Formats >> Surface Layout and Tiling >> 1D Surfaces:
421 s.TileMode = isl_to_gen_tiling[info->surf->tiling];
423 s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
424 s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
474 assert(info->surf->tiling != ISL_TILING_LINEAR);
|
| isl.h | 438 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
445 ISL_TILING_Y0, /**< Legacy Y tiling */
446 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
447 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
448 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
449 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
453 * @defgroup Tiling Flags
468 /** Any Y tiling, including legacy Y tiling. */
473 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". *
741 enum isl_tiling tiling; member in struct:isl_tile_info
826 enum isl_tiling tiling; member in struct:isl_surf
[all...] |
| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_resource.c | 93 slice->tiling, rsc->cpp,
288 * is 4x4 pixels. Texture tiling operates on the
347 slice->tiling, rsc->cpp,
428 slice->tiling = VC4_TILING_FORMAT_LINEAR;
439 slice->tiling = VC4_TILING_FORMAT_LT;
443 slice->tiling = VC4_TILING_FORMAT_T;
471 i, tiling_chars[slice->tiling],
548 * communicate metadata about tiling currently.
610 slice->tiling = VC4_TILING_FORMAT_LINEAR;
658 surface->tiling = rsc->slices[level].tiling
[all...] |
| /external/deqp/external/vulkancts/framework/vulkan/ |
| vkInstanceDriverImpl.inl | 25 VkResult InstanceDriver::getPhysicalDeviceImageFormatProperties (VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags, VkImageFormatProperties* pImageFormatProperties) const
27 return m_vk.getPhysicalDeviceImageFormatProperties(physicalDevice, format, type, tiling, usage, flags, pImageFormatProperties);
65 void InstanceDriver::getPhysicalDeviceSparseImageFormatProperties (VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling, deUint32* pPropertyCount, VkSparseImageFormatProperties* pProperties) const
67 m_vk.getPhysicalDeviceSparseImageFormatProperties(physicalDevice, format, type, samples, usage, tiling, pPropertyCount, pProperties);
|
| vkQueryUtil.hpp | 43 VkImageFormatProperties getPhysicalDeviceImageFormatProperties (const InstanceInterface& vk, VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags);
44 std::vector<VkSparseImageFormatProperties> getPhysicalDeviceSparseImageFormatProperties (const InstanceInterface& vk, VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling);
|
