| /toolchain/binutils/binutils-2.25/opcodes/ |
| d30v-opc.c | 370 #define IMM6 (IMM5S3 + 1)
372 #define IMM6U (IMM6 + 1)
425 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
429 { SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
432 { SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */
454 { SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */
[all...] |
| cr16-opc.c | 147 SHIFT_INST_A("ashud", 0x26, 0x48, 25, imm6, regp),
157 SHIFT_INST_L("lshd", 0x25, 0x47, 25, imm6, regp),
559 {6, arg_ic, OP_SIGNED}, /* imm6 */
|
| v850-opc.c | 1151 /* The IMM6 field in a callt instruction. */
1152 #define IMM6 (D5_4U + 1)
1156 #define D7U (IMM6 + 1)
[all...] |
| bfin-dis.c | 93 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
469 #define imm6(x) fmtconst (c_imm6, x, 0, outf) macro
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/score/ |
| load_store_32.s | 36 /* ldi rD,SImm16 -> ldiu! rD,Imm6 */
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-basic-a64-undefined.txt | 16 # ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMInstrNEON.td | [all...] |
| ARMInstrFormats.td | 197 // other shift immediates. The imm6 field is encoded like so:
200 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
201 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
202 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
203 // 64 64 - <imm> is encoded in imm6<5:0>
[all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCJITInfo.cpp | 45 #define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6)
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrNEON.td | [all...] |
| ARMInstrFormats.td | 217 // other shift immediates. The imm6 field is encoded like so:
220 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
221 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
222 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
223 // 64 64 - <imm> is encoded in imm6<5:0>
[all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| sh64-media.cpu | 102 (df f-imm6 "Immediate value (6 bits)" ((ISA media)) 15 6 INT #f #f)
176 (dshmop imm6 "Immediate (6 bits)" () h-sint f-imm6)
254 "beqi$likely $rm, $imm6, $tra"
255 (+ (f-op 57) rm (f-ext 1) imm6 likely (f-8-2 0) tra (f-rsvd 0))
256 (if (eq rm (ext DI imm6))
304 "bnei$likely $rm, $imm6, $tra"
306 (if (ne rm (ext DI imm6))
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerARM32.cpp | [all...] |
| IceInstARM32.cpp | 966 if (const auto *Imm6 = llvm::dyn_cast<ConstantInteger32>(getSrc(1))) {
967 Asm->vshlqc(ElmtTy, Dest, getSrc(0), Imm6);
973 if (const auto *Imm6 = llvm::dyn_cast<ConstantInteger32>(getSrc(1))) {
974 Asm->vshlqc(ElmtTy, Dest, getSrc(0), Imm6);
1001 const auto *Imm6 = llvm::cast<ConstantInteger32>(getSrc(1));
1006 Asm->vshrquc(ElmtTy, Dest, getSrc(0), Imm6);
[all...] |
| IceAssemblerARM32.h | 788 // iiiiii=Imm6, and Opcode is unioned into the pattern.
790 const Operand *OpQm, const IValueT Imm6,
|
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | 2698 UInt imm6 = INSN(15,10); local
2818 UInt imm6 = INSN(15,10); local
2926 UInt imm6 = INSN(15,10); local
[all...] |
| host_arm64_defs.h | 221 UInt imm6; /* 1 .. 63 */ member in struct:__anon36487::__anon36488::__anon36489
230 extern ARM64RI6* ARM64RI6_I6 ( UInt imm6 );
[all...] |
| host_arm_isel.c | 3268 UInt imm6; local
5354 UInt imm6; local
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| cr16.h | 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon116248
|
| nds32.h | 105 #define N16_TYPE36(op6, rt3, imm6) \
107 | __MF (imm6, 0, 6))
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 289 out |= (Value & 0x1FF800) << 5; // imm6 field
304 out |= (Value & 0x1F800) << 5; // imm6 field
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| bfin-parse.y | 214 #define imm6(x) EXPR_VALUE (x)
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 486 out |= (Value & 0x1FF800) << 5; // imm6 field
499 out |= (Value & 0x1F800) << 5; // imm6 field
[all...] |
| /art/compiler/linker/arm/ |
| relative_patcher_thumb2.cc | 173 ((disp << (16 - 12)) & 0x003f0000u) | // Shift bits 12-17 to 16-25, "imm6".
|
