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      1 /* Disassemble ADI Blackfin Instructions.
      2    Copyright (C) 2005-2014 Free Software Foundation, Inc.
      3 
      4    This file is part of libopcodes.
      5 
      6    This library is free software; you can redistribute it and/or modify
      7    it under the terms of the GNU General Public License as published by
      8    the Free Software Foundation; either version 3, or (at your option)
      9    any later version.
     10 
     11    It is distributed in the hope that it will be useful, but WITHOUT
     12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     14    License for more details.
     15 
     16    You should have received a copy of the GNU General Public License
     17    along with this program; if not, write to the Free Software
     18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
     19    MA 02110-1301, USA.  */
     20 
     21 #include "sysdep.h"
     22 #include <stdio.h>
     23 
     24 #include "opcode/bfin.h"
     25 
     26 #ifndef PRINTF
     27 #define PRINTF printf
     28 #endif
     29 
     30 #ifndef EXIT
     31 #define EXIT exit
     32 #endif
     33 
     34 typedef long TIword;
     35 
     36 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
     37 #define XFIELD(w,p,s)       (((w) & ((1 << (s)) - 1) << (p)) >> (p))
     38 #define SIGNEXTEND(v, n)    ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
     39 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
     40 
     41 #include "dis-asm.h"
     42 
     43 typedef unsigned int bu32;
     44 
     45 struct private
     46 {
     47   TIword iw0;
     48   bfd_boolean comment, parallel;
     49 };
     50 
     51 typedef enum
     52 {
     53   c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
     54   c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
     55   c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
     56   c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
     57   c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
     58 } const_forms_t;
     59 
     60 static const struct
     61 {
     62   const char *name;
     63   const int nbits;
     64   const char reloc;
     65   const char issigned;
     66   const char pcrel;
     67   const char scale;
     68   const char offset;
     69   const char negative;
     70   const char positive;
     71   const char decimal;
     72   const char leading;
     73   const char exact;
     74 } constant_formats[] =
     75 {
     76   { "0",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
     77   { "1",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
     78   { "4",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
     79   { "2",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
     80   { "uimm2",      2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
     81   { "uimm3",      3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
     82   { "imm3",       3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
     83   { "pcrel4",     4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
     84   { "imm4",       4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
     85   { "uimm4s4",    4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
     86   { "uimm4s4d",   4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
     87   { "uimm4",      4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
     88   { "uimm4s2",    4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
     89   { "negimm5s4",  5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
     90   { "imm5",       5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
     91   { "imm5d",      5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
     92   { "uimm5",      5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
     93   { "imm6",       6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
     94   { "imm7",       7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
     95   { "imm7d",      7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
     96   { "imm8",       8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
     97   { "uimm8",      8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
     98   { "pcrel8",     8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
     99   { "uimm8s4",    8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
    100   { "pcrel8s4",   8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
    101   { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
    102   { "pcrel10",   10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
    103   { "pcrel12",   12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
    104   { "imm16s4",   16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
    105   { "luimm16",   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
    106   { "imm16",     16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
    107   { "imm16d",    16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
    108   { "huimm16",   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
    109   { "rimm16",    16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
    110   { "imm16s2",   16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
    111   { "uimm16s4",  16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
    112   { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
    113   { "uimm16",    16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
    114   { "pcrel24",   24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
    115   { "uimm32",    32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
    116   { "imm32",     32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
    117   { "huimm32",   32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
    118   { "huimm32e",  32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
    119 };
    120 
    121 static const char *
    122 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
    123 {
    124   static char buf[60];
    125 
    126   if (constant_formats[cf].reloc)
    127     {
    128       bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
    129 		      : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
    130       if (constant_formats[cf].pcrel)
    131 	ea += pc;
    132 
    133       /* truncate to 32-bits for proper symbol lookup/matching */
    134       ea = (bu32)ea;
    135 
    136       if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
    137 	{
    138 	  outf->print_address_func (ea, outf);
    139 	  return "";
    140 	}
    141       else
    142 	{
    143 	  sprintf (buf, "%lx", (unsigned long) x);
    144 	  return buf;
    145 	}
    146     }
    147 
    148   /* Negative constants have an implied sign bit.  */
    149   if (constant_formats[cf].negative)
    150     {
    151       int nb = constant_formats[cf].nbits + 1;
    152 
    153       x = x | (1 << constant_formats[cf].nbits);
    154       x = SIGNEXTEND (x, nb);
    155     }
    156   else
    157     x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
    158 
    159   if (constant_formats[cf].offset)
    160     x += constant_formats[cf].offset;
    161 
    162   if (constant_formats[cf].scale)
    163     x <<= constant_formats[cf].scale;
    164 
    165   if (constant_formats[cf].decimal)
    166     sprintf (buf, "%*li", constant_formats[cf].leading, x);
    167   else
    168     {
    169       if (constant_formats[cf].issigned && x < 0)
    170 	sprintf (buf, "-0x%x", abs (x));
    171       else
    172 	sprintf (buf, "0x%lx", (unsigned long) x);
    173     }
    174 
    175   return buf;
    176 }
    177 
    178 static bu32
    179 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
    180 {
    181   if (0 && constant_formats[cf].reloc)
    182     {
    183       bu32 ea = (((constant_formats[cf].pcrel
    184 		   ? SIGNEXTEND (x, constant_formats[cf].nbits)
    185 		   : x) + constant_formats[cf].offset)
    186 		 << constant_formats[cf].scale);
    187       if (constant_formats[cf].pcrel)
    188 	ea += pc;
    189 
    190       return ea;
    191     }
    192 
    193   /* Negative constants have an implied sign bit.  */
    194   if (constant_formats[cf].negative)
    195     {
    196       int nb = constant_formats[cf].nbits + 1;
    197       x = x | (1 << constant_formats[cf].nbits);
    198       x = SIGNEXTEND (x, nb);
    199     }
    200   else if (constant_formats[cf].issigned)
    201     x = SIGNEXTEND (x, constant_formats[cf].nbits);
    202 
    203   x += constant_formats[cf].offset;
    204   x <<= constant_formats[cf].scale;
    205 
    206   return x;
    207 }
    208 
    209 enum machine_registers
    210 {
    211   REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
    212   REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
    213   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
    214   REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
    215   REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
    216   REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
    217   REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
    218   REG_L2, REG_L3,
    219   REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
    220   REG_AQ, REG_V, REG_VS,
    221   REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
    222   REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
    223   REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
    224   REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
    225   REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
    226   REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
    227   REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
    228   REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
    229   REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
    230   REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
    231   REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
    232   REG_LASTREG,
    233 };
    234 
    235 enum reg_class
    236 {
    237   rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
    238   rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
    239   rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
    240   rc_sysregs3, rc_allregs,
    241   LIM_REG_CLASSES
    242 };
    243 
    244 static const char * const reg_names[] =
    245 {
    246   "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
    247   "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
    248   "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
    249   "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
    250   "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
    251   "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
    252   "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
    253   "L2", "L3",
    254   "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
    255   "AQ", "V", "VS",
    256   "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
    257   "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
    258   "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
    259   "RETE", "EMUDAT",
    260   "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
    261   "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
    262   "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
    263   "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
    264   "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
    265   "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
    266   "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
    267   "AC0_COPY", "V_COPY", "RND_MOD",
    268   "LASTREG",
    269   0
    270 };
    271 
    272 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
    273 
    274 /* RL(0..7).  */
    275 static const enum machine_registers decode_dregs_lo[] =
    276 {
    277   REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
    278 };
    279 
    280 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
    281 
    282 /* RH(0..7).  */
    283 static const enum machine_registers decode_dregs_hi[] =
    284 {
    285   REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
    286 };
    287 
    288 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
    289 
    290 /* R(0..7).  */
    291 static const enum machine_registers decode_dregs[] =
    292 {
    293   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
    294 };
    295 
    296 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
    297 
    298 /* R BYTE(0..7).  */
    299 static const enum machine_registers decode_dregs_byte[] =
    300 {
    301   REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
    302 };
    303 
    304 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
    305 
    306 /* P(0..5) SP FP.  */
    307 static const enum machine_registers decode_pregs[] =
    308 {
    309   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
    310 };
    311 
    312 #define pregs(x)	REGNAME (decode_pregs[(x) & 7])
    313 #define spfp(x)		REGNAME (decode_spfp[(x) & 1])
    314 #define dregs_hilo(x, i)	REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
    315 #define accum_ext(x)	REGNAME (decode_accum_ext[(x) & 1])
    316 #define accum_word(x)	REGNAME (decode_accum_word[(x) & 1])
    317 #define accum(x)	REGNAME (decode_accum[(x) & 1])
    318 
    319 /* I(0..3).  */
    320 static const enum machine_registers decode_iregs[] =
    321 {
    322   REG_I0, REG_I1, REG_I2, REG_I3,
    323 };
    324 
    325 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
    326 
    327 /* M(0..3).  */
    328 static const enum machine_registers decode_mregs[] =
    329 {
    330   REG_M0, REG_M1, REG_M2, REG_M3,
    331 };
    332 
    333 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
    334 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
    335 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
    336 
    337 /* dregs pregs.  */
    338 static const enum machine_registers decode_dpregs[] =
    339 {
    340   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
    341   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
    342 };
    343 
    344 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
    345 
    346 /* [dregs pregs].  */
    347 static const enum machine_registers decode_gregs[] =
    348 {
    349   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
    350   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
    351 };
    352 
    353 #define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
    354 
    355 /* [dregs pregs (iregs mregs) (bregs lregs)].  */
    356 static const enum machine_registers decode_regs[] =
    357 {
    358   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
    359   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
    360   REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
    361   REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
    362 };
    363 
    364 #define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
    365 
    366 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half].  */
    367 static const enum machine_registers decode_regs_lo[] =
    368 {
    369   REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
    370   REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
    371   REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
    372   REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
    373 };
    374 
    375 #define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
    376 
    377 /* [dregs pregs (iregs mregs) (bregs lregs) High Half].  */
    378 static const enum machine_registers decode_regs_hi[] =
    379 {
    380   REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
    381   REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
    382   REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
    383   REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
    384 };
    385 
    386 #define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
    387 
    388 static const enum machine_registers decode_statbits[] =
    389 {
    390   REG_AZ,        REG_AN,        REG_AC0_COPY,    REG_V_COPY,
    391   REG_LASTREG,   REG_LASTREG,   REG_AQ,          REG_LASTREG,
    392   REG_RND_MOD,   REG_LASTREG,   REG_LASTREG,     REG_LASTREG,
    393   REG_AC0,       REG_AC1,       REG_LASTREG,     REG_LASTREG,
    394   REG_AV0,       REG_AV0S,      REG_AV1,         REG_AV1S,
    395   REG_LASTREG,   REG_LASTREG,   REG_LASTREG,     REG_LASTREG,
    396   REG_V,         REG_VS,        REG_LASTREG,     REG_LASTREG,
    397   REG_LASTREG,   REG_LASTREG,   REG_LASTREG,     REG_LASTREG,
    398 };
    399 
    400 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
    401 
    402 /* LC0 LC1.  */
    403 static const enum machine_registers decode_counters[] =
    404 {
    405   REG_LC0, REG_LC1,
    406 };
    407 
    408 #define counters(x)        REGNAME (decode_counters[(x) & 1])
    409 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
    410 
    411 /* [dregs pregs (iregs mregs) (bregs lregs)
    412    dregs2_sysregs1 open sysregs2 sysregs3].  */
    413 static const enum machine_registers decode_allregs[] =
    414 {
    415   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
    416   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
    417   REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
    418   REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
    419   REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
    420   REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
    421   REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
    422   REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
    423   REG_LASTREG,
    424 };
    425 
    426 #define IS_DREG(g,r)	((g) == 0 && (r) < 8)
    427 #define IS_PREG(g,r)	((g) == 1 && (r) < 8)
    428 #define IS_AREG(g,r)	((g) == 4 && (r) >= 0 && (r) < 4)
    429 #define IS_GENREG(g,r)	((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
    430 #define IS_DAGREG(g,r)	(((g) == 2 || (g) == 3) && (r) < 8)
    431 #define IS_SYSREG(g,r) \
    432   (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
    433 #define IS_RESERVEDREG(g,r) \
    434   (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
    435 
    436 #define allreg(r,g)	(!IS_RESERVEDREG (g, r))
    437 #define mostreg(r,g)	(!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
    438 
    439 #define allregs(x, i)	REGNAME (decode_allregs[((i) << 3) | (x)])
    440 #define uimm16s4(x)	fmtconst (c_uimm16s4, x, 0, outf)
    441 #define uimm16s4d(x)	fmtconst (c_uimm16s4d, x, 0, outf)
    442 #define pcrel4(x)	fmtconst (c_pcrel4, x, pc, outf)
    443 #define pcrel8(x)	fmtconst (c_pcrel8, x, pc, outf)
    444 #define pcrel8s4(x)	fmtconst (c_pcrel8s4, x, pc, outf)
    445 #define pcrel10(x)	fmtconst (c_pcrel10, x, pc, outf)
    446 #define pcrel12(x)	fmtconst (c_pcrel12, x, pc, outf)
    447 #define negimm5s4(x)	fmtconst (c_negimm5s4, x, 0, outf)
    448 #define rimm16(x)	fmtconst (c_rimm16, x, 0, outf)
    449 #define huimm16(x)	fmtconst (c_huimm16, x, 0, outf)
    450 #define imm16(x)	fmtconst (c_imm16, x, 0, outf)
    451 #define imm16d(x)	fmtconst (c_imm16d, x, 0, outf)
    452 #define uimm2(x)	fmtconst (c_uimm2, x, 0, outf)
    453 #define uimm3(x)	fmtconst (c_uimm3, x, 0, outf)
    454 #define luimm16(x)	fmtconst (c_luimm16, x, 0, outf)
    455 #define uimm4(x)	fmtconst (c_uimm4, x, 0, outf)
    456 #define uimm5(x)	fmtconst (c_uimm5, x, 0, outf)
    457 #define imm16s2(x)	fmtconst (c_imm16s2, x, 0, outf)
    458 #define uimm8(x)	fmtconst (c_uimm8, x, 0, outf)
    459 #define imm16s4(x)	fmtconst (c_imm16s4, x, 0, outf)
    460 #define uimm4s2(x)	fmtconst (c_uimm4s2, x, 0, outf)
    461 #define uimm4s4(x)	fmtconst (c_uimm4s4, x, 0, outf)
    462 #define uimm4s4d(x)	fmtconst (c_uimm4s4d, x, 0, outf)
    463 #define lppcrel10(x)	fmtconst (c_lppcrel10, x, pc, outf)
    464 #define imm3(x)		fmtconst (c_imm3, x, 0, outf)
    465 #define imm4(x)		fmtconst (c_imm4, x, 0, outf)
    466 #define uimm8s4(x)	fmtconst (c_uimm8s4, x, 0, outf)
    467 #define imm5(x)		fmtconst (c_imm5, x, 0, outf)
    468 #define imm5d(x)	fmtconst (c_imm5d, x, 0, outf)
    469 #define imm6(x)		fmtconst (c_imm6, x, 0, outf)
    470 #define imm7(x)		fmtconst (c_imm7, x, 0, outf)
    471 #define imm7d(x)	fmtconst (c_imm7d, x, 0, outf)
    472 #define imm8(x)		fmtconst (c_imm8, x, 0, outf)
    473 #define pcrel24(x)	fmtconst (c_pcrel24, x, pc, outf)
    474 #define uimm16(x)	fmtconst (c_uimm16, x, 0, outf)
    475 #define uimm32(x)	fmtconst (c_uimm32, x, 0, outf)
    476 #define imm32(x)	fmtconst (c_imm32, x, 0, outf)
    477 #define huimm32(x)	fmtconst (c_huimm32, x, 0, outf)
    478 #define huimm32e(x)	fmtconst (c_huimm32e, x, 0, outf)
    479 #define imm7_val(x)	fmtconst_val (c_imm7, x, 0)
    480 #define imm16_val(x)	fmtconst_val (c_uimm16, x, 0)
    481 #define luimm16_val(x)	fmtconst_val (c_luimm16, x, 0)
    482 
    483 /* (arch.pm)arch_disassembler_functions.  */
    484 #ifndef OUTS
    485 #define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
    486 #endif
    487 #define OUT(p, txt, ...) (p)->fprintf_func ((p)->stream, txt, ## __VA_ARGS__)
    488 
    489 static void
    490 amod0 (int s0, int x0, disassemble_info *outf)
    491 {
    492   if (s0 == 1 && x0 == 0)
    493     OUTS (outf, " (S)");
    494   else if (s0 == 0 && x0 == 1)
    495     OUTS (outf, " (CO)");
    496   else if (s0 == 1 && x0 == 1)
    497     OUTS (outf, " (SCO)");
    498 }
    499 
    500 static void
    501 amod1 (int s0, int x0, disassemble_info *outf)
    502 {
    503   if (s0 == 0 && x0 == 0)
    504     OUTS (outf, " (NS)");
    505   else if (s0 == 1 && x0 == 0)
    506     OUTS (outf, " (S)");
    507 }
    508 
    509 static void
    510 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
    511 {
    512   if (s0 == 1 && x0 == 0 && aop0 == 0)
    513     OUTS (outf, " (S)");
    514   else if (s0 == 0 && x0 == 1 && aop0 == 0)
    515     OUTS (outf, " (CO)");
    516   else if (s0 == 1 && x0 == 1 && aop0 == 0)
    517     OUTS (outf, " (SCO)");
    518   else if (s0 == 0 && x0 == 0 && aop0 == 2)
    519     OUTS (outf, " (ASR)");
    520   else if (s0 == 1 && x0 == 0 && aop0 == 2)
    521     OUTS (outf, " (S, ASR)");
    522   else if (s0 == 0 && x0 == 1 && aop0 == 2)
    523     OUTS (outf, " (CO, ASR)");
    524   else if (s0 == 1 && x0 == 1 && aop0 == 2)
    525     OUTS (outf, " (SCO, ASR)");
    526   else if (s0 == 0 && x0 == 0 && aop0 == 3)
    527     OUTS (outf, " (ASL)");
    528   else if (s0 == 1 && x0 == 0 && aop0 == 3)
    529     OUTS (outf, " (S, ASL)");
    530   else if (s0 == 0 && x0 == 1 && aop0 == 3)
    531     OUTS (outf, " (CO, ASL)");
    532   else if (s0 == 1 && x0 == 1 && aop0 == 3)
    533     OUTS (outf, " (SCO, ASL)");
    534 }
    535 
    536 static void
    537 searchmod (int r0, disassemble_info *outf)
    538 {
    539   if (r0 == 0)
    540     OUTS (outf, "GT");
    541   else if (r0 == 1)
    542     OUTS (outf, "GE");
    543   else if (r0 == 2)
    544     OUTS (outf, "LT");
    545   else if (r0 == 3)
    546     OUTS (outf, "LE");
    547 }
    548 
    549 static void
    550 aligndir (int r0, disassemble_info *outf)
    551 {
    552   if (r0 == 1)
    553     OUTS (outf, " (R)");
    554 }
    555 
    556 static int
    557 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
    558 {
    559   const char *s0, *s1;
    560 
    561   if (h0)
    562     s0 = dregs_hi (src0);
    563   else
    564     s0 = dregs_lo (src0);
    565 
    566   if (h1)
    567     s1 = dregs_hi (src1);
    568   else
    569     s1 = dregs_lo (src1);
    570 
    571   OUTS (outf, s0);
    572   OUTS (outf, " * ");
    573   OUTS (outf, s1);
    574   return 0;
    575 }
    576 
    577 static int
    578 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
    579 {
    580   const char *a;
    581   const char *sop = "<unknown op>";
    582 
    583   if (which)
    584     a = "A1";
    585   else
    586     a = "A0";
    587 
    588   if (op == 3)
    589     {
    590       OUTS (outf, a);
    591       return 0;
    592     }
    593 
    594   switch (op)
    595     {
    596     case 0: sop = " = ";   break;
    597     case 1: sop = " += ";  break;
    598     case 2: sop = " -= ";  break;
    599     default: break;
    600     }
    601 
    602   OUTS (outf, a);
    603   OUTS (outf, sop);
    604   decode_multfunc (h0, h1, src0, src1, outf);
    605 
    606   return 0;
    607 }
    608 
    609 static void
    610 decode_optmode (int mod, int MM, disassemble_info *outf)
    611 {
    612   if (mod == 0 && MM == 0)
    613     return;
    614 
    615   OUTS (outf, " (");
    616 
    617   if (MM && !mod)
    618     {
    619       OUTS (outf, "M)");
    620       return;
    621     }
    622 
    623   if (MM)
    624     OUTS (outf, "M, ");
    625 
    626   if (mod == M_S2RND)
    627     OUTS (outf, "S2RND");
    628   else if (mod == M_T)
    629     OUTS (outf, "T");
    630   else if (mod == M_W32)
    631     OUTS (outf, "W32");
    632   else if (mod == M_FU)
    633     OUTS (outf, "FU");
    634   else if (mod == M_TFU)
    635     OUTS (outf, "TFU");
    636   else if (mod == M_IS)
    637     OUTS (outf, "IS");
    638   else if (mod == M_ISS2)
    639     OUTS (outf, "ISS2");
    640   else if (mod == M_IH)
    641     OUTS (outf, "IH");
    642   else if (mod == M_IU)
    643     OUTS (outf, "IU");
    644   else
    645     abort ();
    646 
    647   OUTS (outf, ")");
    648 }
    649 
    650 static struct saved_state
    651 {
    652   bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
    653   bu32 ax[2], aw[2];
    654   bu32 lt[2], lc[2], lb[2];
    655   bu32 rets;
    656 } saved_state;
    657 
    658 #define DREG(x)         (saved_state.dpregs[x])
    659 #define GREG(x, i)      DPREG ((x) | ((i) << 3))
    660 #define DPREG(x)        (saved_state.dpregs[x])
    661 #define DREG(x)         (saved_state.dpregs[x])
    662 #define PREG(x)         (saved_state.dpregs[(x) + 8])
    663 #define SPREG           PREG (6)
    664 #define FPREG           PREG (7)
    665 #define IREG(x)         (saved_state.iregs[x])
    666 #define MREG(x)         (saved_state.mregs[x])
    667 #define BREG(x)         (saved_state.bregs[x])
    668 #define LREG(x)         (saved_state.lregs[x])
    669 #define AXREG(x)        (saved_state.ax[x])
    670 #define AWREG(x)        (saved_state.aw[x])
    671 #define LCREG(x)        (saved_state.lc[x])
    672 #define LTREG(x)        (saved_state.lt[x])
    673 #define LBREG(x)        (saved_state.lb[x])
    674 #define RETSREG         (saved_state.rets)
    675 
    676 static bu32 *
    677 get_allreg (int grp, int reg)
    678 {
    679   int fullreg = (grp << 3) | reg;
    680   /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
    681      REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
    682      REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
    683      REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
    684      REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
    685      , , , , , , , ,
    686      REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
    687      REG_CYCLES2,
    688      REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
    689      REG_LASTREG */
    690   switch (fullreg >> 2)
    691     {
    692     case 0: case 1: return &DREG (reg);
    693     case 2: case 3: return &PREG (reg);
    694     case 4: return &IREG (reg & 3);
    695     case 5: return &MREG (reg & 3);
    696     case 6: return &BREG (reg & 3);
    697     case 7: return &LREG (reg & 3);
    698     default:
    699       switch (fullreg)
    700 	{
    701 	case 32: return &AXREG (0);
    702 	case 33: return &AWREG (0);
    703 	case 34: return &AXREG (1);
    704 	case 35: return &AWREG (1);
    705 	case 39: return &RETSREG;
    706 	case 48: return &LCREG (0);
    707 	case 49: return &LTREG (0);
    708 	case 50: return &LBREG (0);
    709 	case 51: return &LCREG (1);
    710 	case 52: return &LTREG (1);
    711 	case 53: return &LBREG (1);
    712 	}
    713     }
    714   abort ();
    715 }
    716 
    717 static int
    718 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
    719 {
    720   struct private *priv = outf->private_data;
    721   /* ProgCtrl
    722      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
    723      | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
    724      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
    725   int poprnd  = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
    726   int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
    727 
    728   if (prgfunc == 0 && poprnd == 0)
    729     OUTS (outf, "NOP");
    730   else if (priv->parallel)
    731     return 0;
    732   else if (prgfunc == 1 && poprnd == 0)
    733     OUTS (outf, "RTS");
    734   else if (prgfunc == 1 && poprnd == 1)
    735     OUTS (outf, "RTI");
    736   else if (prgfunc == 1 && poprnd == 2)
    737     OUTS (outf, "RTX");
    738   else if (prgfunc == 1 && poprnd == 3)
    739     OUTS (outf, "RTN");
    740   else if (prgfunc == 1 && poprnd == 4)
    741     OUTS (outf, "RTE");
    742   else if (prgfunc == 2 && poprnd == 0)
    743     OUTS (outf, "IDLE");
    744   else if (prgfunc == 2 && poprnd == 3)
    745     OUTS (outf, "CSYNC");
    746   else if (prgfunc == 2 && poprnd == 4)
    747     OUTS (outf, "SSYNC");
    748   else if (prgfunc == 2 && poprnd == 5)
    749     OUTS (outf, "EMUEXCPT");
    750   else if (prgfunc == 3 && IS_DREG (0, poprnd))
    751     {
    752       OUTS (outf, "CLI ");
    753       OUTS (outf, dregs (poprnd));
    754     }
    755   else if (prgfunc == 4 && IS_DREG (0, poprnd))
    756     {
    757       OUTS (outf, "STI ");
    758       OUTS (outf, dregs (poprnd));
    759     }
    760   else if (prgfunc == 5 && IS_PREG (1, poprnd))
    761     {
    762       OUTS (outf, "JUMP (");
    763       OUTS (outf, pregs (poprnd));
    764       OUTS (outf, ")");
    765     }
    766   else if (prgfunc == 6 && IS_PREG (1, poprnd))
    767     {
    768       OUTS (outf, "CALL (");
    769       OUTS (outf, pregs (poprnd));
    770       OUTS (outf, ")");
    771     }
    772   else if (prgfunc == 7 && IS_PREG (1, poprnd))
    773     {
    774       OUTS (outf, "CALL (PC + ");
    775       OUTS (outf, pregs (poprnd));
    776       OUTS (outf, ")");
    777     }
    778   else if (prgfunc == 8 && IS_PREG (1, poprnd))
    779     {
    780       OUTS (outf, "JUMP (PC + ");
    781       OUTS (outf, pregs (poprnd));
    782       OUTS (outf, ")");
    783     }
    784   else if (prgfunc == 9)
    785     {
    786       OUTS (outf, "RAISE ");
    787       OUTS (outf, uimm4 (poprnd));
    788     }
    789   else if (prgfunc == 10)
    790     {
    791       OUTS (outf, "EXCPT ");
    792       OUTS (outf, uimm4 (poprnd));
    793     }
    794   else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
    795     {
    796       OUTS (outf, "TESTSET (");
    797       OUTS (outf, pregs (poprnd));
    798       OUTS (outf, ")");
    799     }
    800   else
    801     return 0;
    802   return 2;
    803 }
    804 
    805 static int
    806 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
    807 {
    808   struct private *priv = outf->private_data;
    809   /* CaCTRL
    810      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
    811      | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
    812      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
    813   int a   = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
    814   int op  = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
    815   int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
    816 
    817   if (priv->parallel)
    818     return 0;
    819 
    820   if (a == 0 && op == 0)
    821     {
    822       OUTS (outf, "PREFETCH[");
    823       OUTS (outf, pregs (reg));
    824       OUTS (outf, "]");
    825     }
    826   else if (a == 0 && op == 1)
    827     {
    828       OUTS (outf, "FLUSHINV[");
    829       OUTS (outf, pregs (reg));
    830       OUTS (outf, "]");
    831     }
    832   else if (a == 0 && op == 2)
    833     {
    834       OUTS (outf, "FLUSH[");
    835       OUTS (outf, pregs (reg));
    836       OUTS (outf, "]");
    837     }
    838   else if (a == 0 && op == 3)
    839     {
    840       OUTS (outf, "IFLUSH[");
    841       OUTS (outf, pregs (reg));
    842       OUTS (outf, "]");
    843     }
    844   else if (a == 1 && op == 0)
    845     {
    846       OUTS (outf, "PREFETCH[");
    847       OUTS (outf, pregs (reg));
    848       OUTS (outf, "++]");
    849     }
    850   else if (a == 1 && op == 1)
    851     {
    852       OUTS (outf, "FLUSHINV[");
    853       OUTS (outf, pregs (reg));
    854       OUTS (outf, "++]");
    855     }
    856   else if (a == 1 && op == 2)
    857     {
    858       OUTS (outf, "FLUSH[");
    859       OUTS (outf, pregs (reg));
    860       OUTS (outf, "++]");
    861     }
    862   else if (a == 1 && op == 3)
    863     {
    864       OUTS (outf, "IFLUSH[");
    865       OUTS (outf, pregs (reg));
    866       OUTS (outf, "++]");
    867     }
    868   else
    869     return 0;
    870   return 2;
    871 }
    872 
    873 static int
    874 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
    875 {
    876   struct private *priv = outf->private_data;
    877   /* PushPopReg
    878      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
    879      | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
    880      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
    881   int W   = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
    882   int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
    883   int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
    884 
    885   if (priv->parallel)
    886     return 0;
    887 
    888   if (W == 0 && mostreg (reg, grp))
    889     {
    890       OUTS (outf, allregs (reg, grp));
    891       OUTS (outf, " = [SP++]");
    892     }
    893   else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
    894     {
    895       OUTS (outf, "[--SP] = ");
    896       OUTS (outf, allregs (reg, grp));
    897     }
    898   else
    899     return 0;
    900   return 2;
    901 }
    902 
    903 static int
    904 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
    905 {
    906   struct private *priv = outf->private_data;
    907   /* PushPopMultiple
    908      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
    909      | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
    910      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
    911   int p  = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
    912   int d  = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
    913   int W  = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
    914   int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
    915   int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
    916 
    917   if (priv->parallel)
    918     return 0;
    919 
    920   if (pr > 5)
    921     return 0;
    922 
    923   if (W == 1 && d == 1 && p == 1)
    924     {
    925       OUTS (outf, "[--SP] = (R7:");
    926       OUTS (outf, imm5d (dr));
    927       OUTS (outf, ", P5:");
    928       OUTS (outf, imm5d (pr));
    929       OUTS (outf, ")");
    930     }
    931   else if (W == 1 && d == 1 && p == 0 && pr == 0)
    932     {
    933       OUTS (outf, "[--SP] = (R7:");
    934       OUTS (outf, imm5d (dr));
    935       OUTS (outf, ")");
    936     }
    937   else if (W == 1 && d == 0 && p == 1 && dr == 0)
    938     {
    939       OUTS (outf, "[--SP] = (P5:");
    940       OUTS (outf, imm5d (pr));
    941       OUTS (outf, ")");
    942     }
    943   else if (W == 0 && d == 1 && p == 1)
    944     {
    945       OUTS (outf, "(R7:");
    946       OUTS (outf, imm5d (dr));
    947       OUTS (outf, ", P5:");
    948       OUTS (outf, imm5d (pr));
    949       OUTS (outf, ") = [SP++]");
    950     }
    951   else if (W == 0 && d == 1 && p == 0 && pr == 0)
    952     {
    953       OUTS (outf, "(R7:");
    954       OUTS (outf, imm5d (dr));
    955       OUTS (outf, ") = [SP++]");
    956     }
    957   else if (W == 0 && d == 0 && p == 1 && dr == 0)
    958     {
    959       OUTS (outf, "(P5:");
    960       OUTS (outf, imm5d (pr));
    961       OUTS (outf, ") = [SP++]");
    962     }
    963   else
    964     return 0;
    965   return 2;
    966 }
    967 
    968 static int
    969 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
    970 {
    971   struct private *priv = outf->private_data;
    972   /* ccMV
    973      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
    974      | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
    975      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
    976   int s  = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
    977   int d  = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
    978   int T  = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
    979   int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
    980   int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
    981 
    982   if (priv->parallel)
    983     return 0;
    984 
    985   if (T == 1)
    986     {
    987       OUTS (outf, "IF CC ");
    988       OUTS (outf, gregs (dst, d));
    989       OUTS (outf, " = ");
    990       OUTS (outf, gregs (src, s));
    991     }
    992   else if (T == 0)
    993     {
    994       OUTS (outf, "IF !CC ");
    995       OUTS (outf, gregs (dst, d));
    996       OUTS (outf, " = ");
    997       OUTS (outf, gregs (src, s));
    998     }
    999   else
   1000     return 0;
   1001   return 2;
   1002 }
   1003 
   1004 static int
   1005 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
   1006 {
   1007   struct private *priv = outf->private_data;
   1008   /* CCflag
   1009      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1010      | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
   1011      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1012   int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
   1013   int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
   1014   int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
   1015   int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
   1016   int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
   1017 
   1018   if (priv->parallel)
   1019     return 0;
   1020 
   1021   if (opc == 0 && I == 0 && G == 0)
   1022     {
   1023       OUTS (outf, "CC = ");
   1024       OUTS (outf, dregs (x));
   1025       OUTS (outf, " == ");
   1026       OUTS (outf, dregs (y));
   1027     }
   1028   else if (opc == 1 && I == 0 && G == 0)
   1029     {
   1030       OUTS (outf, "CC = ");
   1031       OUTS (outf, dregs (x));
   1032       OUTS (outf, " < ");
   1033       OUTS (outf, dregs (y));
   1034     }
   1035   else if (opc == 2 && I == 0 && G == 0)
   1036     {
   1037       OUTS (outf, "CC = ");
   1038       OUTS (outf, dregs (x));
   1039       OUTS (outf, " <= ");
   1040       OUTS (outf, dregs (y));
   1041     }
   1042   else if (opc == 3 && I == 0 && G == 0)
   1043     {
   1044       OUTS (outf, "CC = ");
   1045       OUTS (outf, dregs (x));
   1046       OUTS (outf, " < ");
   1047       OUTS (outf, dregs (y));
   1048       OUTS (outf, " (IU)");
   1049     }
   1050   else if (opc == 4 && I == 0 && G == 0)
   1051     {
   1052       OUTS (outf, "CC = ");
   1053       OUTS (outf, dregs (x));
   1054       OUTS (outf, " <= ");
   1055       OUTS (outf, dregs (y));
   1056       OUTS (outf, " (IU)");
   1057     }
   1058   else if (opc == 0 && I == 1 && G == 0)
   1059     {
   1060       OUTS (outf, "CC = ");
   1061       OUTS (outf, dregs (x));
   1062       OUTS (outf, " == ");
   1063       OUTS (outf, imm3 (y));
   1064     }
   1065   else if (opc == 1 && I == 1 && G == 0)
   1066     {
   1067       OUTS (outf, "CC = ");
   1068       OUTS (outf, dregs (x));
   1069       OUTS (outf, " < ");
   1070       OUTS (outf, imm3 (y));
   1071     }
   1072   else if (opc == 2 && I == 1 && G == 0)
   1073     {
   1074       OUTS (outf, "CC = ");
   1075       OUTS (outf, dregs (x));
   1076       OUTS (outf, " <= ");
   1077       OUTS (outf, imm3 (y));
   1078     }
   1079   else if (opc == 3 && I == 1 && G == 0)
   1080     {
   1081       OUTS (outf, "CC = ");
   1082       OUTS (outf, dregs (x));
   1083       OUTS (outf, " < ");
   1084       OUTS (outf, uimm3 (y));
   1085       OUTS (outf, " (IU)");
   1086     }
   1087   else if (opc == 4 && I == 1 && G == 0)
   1088     {
   1089       OUTS (outf, "CC = ");
   1090       OUTS (outf, dregs (x));
   1091       OUTS (outf, " <= ");
   1092       OUTS (outf, uimm3 (y));
   1093       OUTS (outf, " (IU)");
   1094     }
   1095   else if (opc == 0 && I == 0 && G == 1)
   1096     {
   1097       OUTS (outf, "CC = ");
   1098       OUTS (outf, pregs (x));
   1099       OUTS (outf, " == ");
   1100       OUTS (outf, pregs (y));
   1101     }
   1102   else if (opc == 1 && I == 0 && G == 1)
   1103     {
   1104       OUTS (outf, "CC = ");
   1105       OUTS (outf, pregs (x));
   1106       OUTS (outf, " < ");
   1107       OUTS (outf, pregs (y));
   1108     }
   1109   else if (opc == 2 && I == 0 && G == 1)
   1110     {
   1111       OUTS (outf, "CC = ");
   1112       OUTS (outf, pregs (x));
   1113       OUTS (outf, " <= ");
   1114       OUTS (outf, pregs (y));
   1115     }
   1116   else if (opc == 3 && I == 0 && G == 1)
   1117     {
   1118       OUTS (outf, "CC = ");
   1119       OUTS (outf, pregs (x));
   1120       OUTS (outf, " < ");
   1121       OUTS (outf, pregs (y));
   1122       OUTS (outf, " (IU)");
   1123     }
   1124   else if (opc == 4 && I == 0 && G == 1)
   1125     {
   1126       OUTS (outf, "CC = ");
   1127       OUTS (outf, pregs (x));
   1128       OUTS (outf, " <= ");
   1129       OUTS (outf, pregs (y));
   1130       OUTS (outf, " (IU)");
   1131     }
   1132   else if (opc == 0 && I == 1 && G == 1)
   1133     {
   1134       OUTS (outf, "CC = ");
   1135       OUTS (outf, pregs (x));
   1136       OUTS (outf, " == ");
   1137       OUTS (outf, imm3 (y));
   1138     }
   1139   else if (opc == 1 && I == 1 && G == 1)
   1140     {
   1141       OUTS (outf, "CC = ");
   1142       OUTS (outf, pregs (x));
   1143       OUTS (outf, " < ");
   1144       OUTS (outf, imm3 (y));
   1145     }
   1146   else if (opc == 2 && I == 1 && G == 1)
   1147     {
   1148       OUTS (outf, "CC = ");
   1149       OUTS (outf, pregs (x));
   1150       OUTS (outf, " <= ");
   1151       OUTS (outf, imm3 (y));
   1152     }
   1153   else if (opc == 3 && I == 1 && G == 1)
   1154     {
   1155       OUTS (outf, "CC = ");
   1156       OUTS (outf, pregs (x));
   1157       OUTS (outf, " < ");
   1158       OUTS (outf, uimm3 (y));
   1159       OUTS (outf, " (IU)");
   1160     }
   1161   else if (opc == 4 && I == 1 && G == 1)
   1162     {
   1163       OUTS (outf, "CC = ");
   1164       OUTS (outf, pregs (x));
   1165       OUTS (outf, " <= ");
   1166       OUTS (outf, uimm3 (y));
   1167       OUTS (outf, " (IU)");
   1168     }
   1169   else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
   1170     OUTS (outf, "CC = A0 == A1");
   1171 
   1172   else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
   1173     OUTS (outf, "CC = A0 < A1");
   1174 
   1175   else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
   1176     OUTS (outf, "CC = A0 <= A1");
   1177 
   1178   else
   1179     return 0;
   1180   return 2;
   1181 }
   1182 
   1183 static int
   1184 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
   1185 {
   1186   struct private *priv = outf->private_data;
   1187   /* CC2dreg
   1188      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1189      | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
   1190      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1191   int op  = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
   1192   int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
   1193 
   1194   if (priv->parallel)
   1195     return 0;
   1196 
   1197   if (op == 0)
   1198     {
   1199       OUTS (outf, dregs (reg));
   1200       OUTS (outf, " = CC");
   1201     }
   1202   else if (op == 1)
   1203     {
   1204       OUTS (outf, "CC = ");
   1205       OUTS (outf, dregs (reg));
   1206     }
   1207   else if (op == 3 && reg == 0)
   1208     OUTS (outf, "CC = !CC");
   1209   else
   1210     return 0;
   1211 
   1212   return 2;
   1213 }
   1214 
   1215 static int
   1216 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
   1217 {
   1218   struct private *priv = outf->private_data;
   1219   /* CC2stat
   1220      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1221      | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
   1222      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1223   int D    = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
   1224   int op   = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
   1225   int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
   1226 
   1227   const char *bitname = statbits (cbit);
   1228   const char * const op_names[] = { "", "|", "&", "^" } ;
   1229 
   1230   if (priv->parallel)
   1231     return 0;
   1232 
   1233   if (decode_statbits[cbit] == REG_LASTREG)
   1234     {
   1235       /* All ASTAT bits except CC may be operated on in hardware, but may
   1236          not have a dedicated insn, so still decode "valid" insns.  */
   1237       static char bitnames[64];
   1238       if (cbit != 5)
   1239 	sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
   1240       else
   1241 	return 0;
   1242 
   1243       bitname = bitnames;
   1244     }
   1245 
   1246   if (D == 0)
   1247     OUT (outf, "CC %s= %s", op_names[op], bitname);
   1248   else
   1249     OUT (outf, "%s %s= CC", bitname, op_names[op]);
   1250 
   1251   return 2;
   1252 }
   1253 
   1254 static int
   1255 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
   1256 {
   1257   struct private *priv = outf->private_data;
   1258   /* BRCC
   1259      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1260      | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
   1261      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1262   int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
   1263   int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
   1264   int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
   1265 
   1266   if (priv->parallel)
   1267     return 0;
   1268 
   1269   if (T == 1 && B == 1)
   1270     {
   1271       OUTS (outf, "IF CC JUMP 0x");
   1272       OUTS (outf, pcrel10 (offset));
   1273       OUTS (outf, " (BP)");
   1274     }
   1275   else if (T == 0 && B == 1)
   1276     {
   1277       OUTS (outf, "IF !CC JUMP 0x");
   1278       OUTS (outf, pcrel10 (offset));
   1279       OUTS (outf, " (BP)");
   1280     }
   1281   else if (T == 1)
   1282     {
   1283       OUTS (outf, "IF CC JUMP 0x");
   1284       OUTS (outf, pcrel10 (offset));
   1285     }
   1286   else if (T == 0)
   1287     {
   1288       OUTS (outf, "IF !CC JUMP 0x");
   1289       OUTS (outf, pcrel10 (offset));
   1290     }
   1291   else
   1292     return 0;
   1293 
   1294   return 2;
   1295 }
   1296 
   1297 static int
   1298 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
   1299 {
   1300   struct private *priv = outf->private_data;
   1301   /* UJUMP
   1302      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1303      | 0 | 0 | 1 | 0 |.offset........................................|
   1304      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1305   int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
   1306 
   1307   if (priv->parallel)
   1308     return 0;
   1309 
   1310   OUTS (outf, "JUMP.S 0x");
   1311   OUTS (outf, pcrel12 (offset));
   1312   return 2;
   1313 }
   1314 
   1315 static int
   1316 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
   1317 {
   1318   /* REGMV
   1319      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1320      | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
   1321      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1322   int gs  = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
   1323   int gd  = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
   1324   int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
   1325   int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
   1326 
   1327   /* Reserved slots cannot be a src/dst.  */
   1328   if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
   1329     goto invalid_move;
   1330 
   1331   /* Standard register moves  */
   1332   if ((gs < 2) ||                               /* Dregs/Pregs as source  */
   1333       (gd < 2) ||                               /* Dregs/Pregs as dest    */
   1334       (gs == 4 && src < 4) ||                   /* Accumulators as source */
   1335       (gd == 4 && dst < 4 && (gs < 4)) ||       /* Accumulators as dest   */
   1336       (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src  */
   1337       (gd == 7 && dst == 7))                    /* EMUDAT as dest         */
   1338     goto valid_move;
   1339 
   1340   /* dareg = dareg (IMBL) */
   1341   if (gs < 4 && gd < 4)
   1342     goto valid_move;
   1343 
   1344   /* USP can be src to sysregs, but not dagregs.  */
   1345   if ((gs == 7 && src == 0) && (gd >= 4))
   1346     goto valid_move;
   1347 
   1348   /* USP can move between genregs (only check Accumulators).  */
   1349   if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
   1350       ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
   1351     goto valid_move;
   1352 
   1353   /* Still here ?  Invalid reg pair.  */
   1354  invalid_move:
   1355   return 0;
   1356 
   1357  valid_move:
   1358   OUTS (outf, allregs (dst, gd));
   1359   OUTS (outf, " = ");
   1360   OUTS (outf, allregs (src, gs));
   1361   return 2;
   1362 }
   1363 
   1364 static int
   1365 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
   1366 {
   1367   /* ALU2op
   1368      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1369      | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
   1370      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1371   int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
   1372   int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
   1373   int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
   1374 
   1375   if (opc == 0)
   1376     {
   1377       OUTS (outf, dregs (dst));
   1378       OUTS (outf, " >>>= ");
   1379       OUTS (outf, dregs (src));
   1380     }
   1381   else if (opc == 1)
   1382     {
   1383       OUTS (outf, dregs (dst));
   1384       OUTS (outf, " >>= ");
   1385       OUTS (outf, dregs (src));
   1386     }
   1387   else if (opc == 2)
   1388     {
   1389       OUTS (outf, dregs (dst));
   1390       OUTS (outf, " <<= ");
   1391       OUTS (outf, dregs (src));
   1392     }
   1393   else if (opc == 3)
   1394     {
   1395       OUTS (outf, dregs (dst));
   1396       OUTS (outf, " *= ");
   1397       OUTS (outf, dregs (src));
   1398     }
   1399   else if (opc == 4)
   1400     {
   1401       OUTS (outf, dregs (dst));
   1402       OUTS (outf, " = (");
   1403       OUTS (outf, dregs (dst));
   1404       OUTS (outf, " + ");
   1405       OUTS (outf, dregs (src));
   1406       OUTS (outf, ") << 0x1");
   1407     }
   1408   else if (opc == 5)
   1409     {
   1410       OUTS (outf, dregs (dst));
   1411       OUTS (outf, " = (");
   1412       OUTS (outf, dregs (dst));
   1413       OUTS (outf, " + ");
   1414       OUTS (outf, dregs (src));
   1415       OUTS (outf, ") << 0x2");
   1416     }
   1417   else if (opc == 8)
   1418     {
   1419       OUTS (outf, "DIVQ (");
   1420       OUTS (outf, dregs (dst));
   1421       OUTS (outf, ", ");
   1422       OUTS (outf, dregs (src));
   1423       OUTS (outf, ")");
   1424     }
   1425   else if (opc == 9)
   1426     {
   1427       OUTS (outf, "DIVS (");
   1428       OUTS (outf, dregs (dst));
   1429       OUTS (outf, ", ");
   1430       OUTS (outf, dregs (src));
   1431       OUTS (outf, ")");
   1432     }
   1433   else if (opc == 10)
   1434     {
   1435       OUTS (outf, dregs (dst));
   1436       OUTS (outf, " = ");
   1437       OUTS (outf, dregs_lo (src));
   1438       OUTS (outf, " (X)");
   1439     }
   1440   else if (opc == 11)
   1441     {
   1442       OUTS (outf, dregs (dst));
   1443       OUTS (outf, " = ");
   1444       OUTS (outf, dregs_lo (src));
   1445       OUTS (outf, " (Z)");
   1446     }
   1447   else if (opc == 12)
   1448     {
   1449       OUTS (outf, dregs (dst));
   1450       OUTS (outf, " = ");
   1451       OUTS (outf, dregs_byte (src));
   1452       OUTS (outf, " (X)");
   1453     }
   1454   else if (opc == 13)
   1455     {
   1456       OUTS (outf, dregs (dst));
   1457       OUTS (outf, " = ");
   1458       OUTS (outf, dregs_byte (src));
   1459       OUTS (outf, " (Z)");
   1460     }
   1461   else if (opc == 14)
   1462     {
   1463       OUTS (outf, dregs (dst));
   1464       OUTS (outf, " = -");
   1465       OUTS (outf, dregs (src));
   1466     }
   1467   else if (opc == 15)
   1468     {
   1469       OUTS (outf, dregs (dst));
   1470       OUTS (outf, " =~ ");
   1471       OUTS (outf, dregs (src));
   1472     }
   1473   else
   1474     return 0;
   1475 
   1476   return 2;
   1477 }
   1478 
   1479 static int
   1480 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
   1481 {
   1482   /* PTR2op
   1483      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1484      | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
   1485      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1486   int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
   1487   int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
   1488   int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
   1489 
   1490   if (opc == 0)
   1491     {
   1492       OUTS (outf, pregs (dst));
   1493       OUTS (outf, " -= ");
   1494       OUTS (outf, pregs (src));
   1495     }
   1496   else if (opc == 1)
   1497     {
   1498       OUTS (outf, pregs (dst));
   1499       OUTS (outf, " = ");
   1500       OUTS (outf, pregs (src));
   1501       OUTS (outf, " << 0x2");
   1502     }
   1503   else if (opc == 3)
   1504     {
   1505       OUTS (outf, pregs (dst));
   1506       OUTS (outf, " = ");
   1507       OUTS (outf, pregs (src));
   1508       OUTS (outf, " >> 0x2");
   1509     }
   1510   else if (opc == 4)
   1511     {
   1512       OUTS (outf, pregs (dst));
   1513       OUTS (outf, " = ");
   1514       OUTS (outf, pregs (src));
   1515       OUTS (outf, " >> 0x1");
   1516     }
   1517   else if (opc == 5)
   1518     {
   1519       OUTS (outf, pregs (dst));
   1520       OUTS (outf, " += ");
   1521       OUTS (outf, pregs (src));
   1522       OUTS (outf, " (BREV)");
   1523     }
   1524   else if (opc == 6)
   1525     {
   1526       OUTS (outf, pregs (dst));
   1527       OUTS (outf, " = (");
   1528       OUTS (outf, pregs (dst));
   1529       OUTS (outf, " + ");
   1530       OUTS (outf, pregs (src));
   1531       OUTS (outf, ") << 0x1");
   1532     }
   1533   else if (opc == 7)
   1534     {
   1535       OUTS (outf, pregs (dst));
   1536       OUTS (outf, " = (");
   1537       OUTS (outf, pregs (dst));
   1538       OUTS (outf, " + ");
   1539       OUTS (outf, pregs (src));
   1540       OUTS (outf, ") << 0x2");
   1541     }
   1542   else
   1543     return 0;
   1544 
   1545   return 2;
   1546 }
   1547 
   1548 static int
   1549 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
   1550 {
   1551   struct private *priv = outf->private_data;
   1552   /* LOGI2op
   1553      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1554      | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
   1555      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1556   int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
   1557   int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
   1558   int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
   1559 
   1560   if (priv->parallel)
   1561     return 0;
   1562 
   1563   if (opc == 0)
   1564     {
   1565       OUTS (outf, "CC = !BITTST (");
   1566       OUTS (outf, dregs (dst));
   1567       OUTS (outf, ", ");
   1568       OUTS (outf, uimm5 (src));
   1569       OUTS (outf, ");\t\t/* bit");
   1570       OUTS (outf, imm7d (src));
   1571       OUTS (outf, " */");
   1572       priv->comment = TRUE;
   1573     }
   1574   else if (opc == 1)
   1575     {
   1576       OUTS (outf, "CC = BITTST (");
   1577       OUTS (outf, dregs (dst));
   1578       OUTS (outf, ", ");
   1579       OUTS (outf, uimm5 (src));
   1580       OUTS (outf, ");\t\t/* bit");
   1581       OUTS (outf, imm7d (src));
   1582       OUTS (outf, " */");
   1583       priv->comment = TRUE;
   1584     }
   1585   else if (opc == 2)
   1586     {
   1587       OUTS (outf, "BITSET (");
   1588       OUTS (outf, dregs (dst));
   1589       OUTS (outf, ", ");
   1590       OUTS (outf, uimm5 (src));
   1591       OUTS (outf, ");\t\t/* bit");
   1592       OUTS (outf, imm7d (src));
   1593       OUTS (outf, " */");
   1594       priv->comment = TRUE;
   1595     }
   1596   else if (opc == 3)
   1597     {
   1598       OUTS (outf, "BITTGL (");
   1599       OUTS (outf, dregs (dst));
   1600       OUTS (outf, ", ");
   1601       OUTS (outf, uimm5 (src));
   1602       OUTS (outf, ");\t\t/* bit");
   1603       OUTS (outf, imm7d (src));
   1604       OUTS (outf, " */");
   1605       priv->comment = TRUE;
   1606     }
   1607   else if (opc == 4)
   1608     {
   1609       OUTS (outf, "BITCLR (");
   1610       OUTS (outf, dregs (dst));
   1611       OUTS (outf, ", ");
   1612       OUTS (outf, uimm5 (src));
   1613       OUTS (outf, ");\t\t/* bit");
   1614       OUTS (outf, imm7d (src));
   1615       OUTS (outf, " */");
   1616       priv->comment = TRUE;
   1617     }
   1618   else if (opc == 5)
   1619     {
   1620       OUTS (outf, dregs (dst));
   1621       OUTS (outf, " >>>= ");
   1622       OUTS (outf, uimm5 (src));
   1623     }
   1624   else if (opc == 6)
   1625     {
   1626       OUTS (outf, dregs (dst));
   1627       OUTS (outf, " >>= ");
   1628       OUTS (outf, uimm5 (src));
   1629     }
   1630   else if (opc == 7)
   1631     {
   1632       OUTS (outf, dregs (dst));
   1633       OUTS (outf, " <<= ");
   1634       OUTS (outf, uimm5 (src));
   1635     }
   1636   else
   1637     return 0;
   1638 
   1639   return 2;
   1640 }
   1641 
   1642 static int
   1643 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
   1644 {
   1645   /* COMP3op
   1646      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1647      | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
   1648      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1649   int opc  = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
   1650   int dst  = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
   1651   int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
   1652   int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
   1653 
   1654   if (opc == 5 && src1 == src0)
   1655     {
   1656       OUTS (outf, pregs (dst));
   1657       OUTS (outf, " = ");
   1658       OUTS (outf, pregs (src0));
   1659       OUTS (outf, " << 0x1");
   1660     }
   1661   else if (opc == 1)
   1662     {
   1663       OUTS (outf, dregs (dst));
   1664       OUTS (outf, " = ");
   1665       OUTS (outf, dregs (src0));
   1666       OUTS (outf, " - ");
   1667       OUTS (outf, dregs (src1));
   1668     }
   1669   else if (opc == 2)
   1670     {
   1671       OUTS (outf, dregs (dst));
   1672       OUTS (outf, " = ");
   1673       OUTS (outf, dregs (src0));
   1674       OUTS (outf, " & ");
   1675       OUTS (outf, dregs (src1));
   1676     }
   1677   else if (opc == 3)
   1678     {
   1679       OUTS (outf, dregs (dst));
   1680       OUTS (outf, " = ");
   1681       OUTS (outf, dregs (src0));
   1682       OUTS (outf, " | ");
   1683       OUTS (outf, dregs (src1));
   1684     }
   1685   else if (opc == 4)
   1686     {
   1687       OUTS (outf, dregs (dst));
   1688       OUTS (outf, " = ");
   1689       OUTS (outf, dregs (src0));
   1690       OUTS (outf, " ^ ");
   1691       OUTS (outf, dregs (src1));
   1692     }
   1693   else if (opc == 5)
   1694     {
   1695       OUTS (outf, pregs (dst));
   1696       OUTS (outf, " = ");
   1697       OUTS (outf, pregs (src0));
   1698       OUTS (outf, " + ");
   1699       OUTS (outf, pregs (src1));
   1700     }
   1701   else if (opc == 6)
   1702     {
   1703       OUTS (outf, pregs (dst));
   1704       OUTS (outf, " = ");
   1705       OUTS (outf, pregs (src0));
   1706       OUTS (outf, " + (");
   1707       OUTS (outf, pregs (src1));
   1708       OUTS (outf, " << 0x1)");
   1709     }
   1710   else if (opc == 7)
   1711     {
   1712       OUTS (outf, pregs (dst));
   1713       OUTS (outf, " = ");
   1714       OUTS (outf, pregs (src0));
   1715       OUTS (outf, " + (");
   1716       OUTS (outf, pregs (src1));
   1717       OUTS (outf, " << 0x2)");
   1718     }
   1719   else if (opc == 0)
   1720     {
   1721       OUTS (outf, dregs (dst));
   1722       OUTS (outf, " = ");
   1723       OUTS (outf, dregs (src0));
   1724       OUTS (outf, " + ");
   1725       OUTS (outf, dregs (src1));
   1726     }
   1727   else
   1728     return 0;
   1729 
   1730   return 2;
   1731 }
   1732 
   1733 static int
   1734 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
   1735 {
   1736   struct private *priv = outf->private_data;
   1737   /* COMPI2opD
   1738      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1739      | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
   1740      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1741   int op  = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
   1742   int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
   1743   int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
   1744 
   1745   bu32 *pval = get_allreg (0, dst);
   1746 
   1747   if (priv->parallel)
   1748     return 0;
   1749 
   1750   /* Since we don't have 32-bit immediate loads, we allow the disassembler
   1751      to combine them, so it prints out the right values.
   1752      Here we keep track of the registers.  */
   1753   if (op == 0)
   1754     {
   1755       *pval = imm7_val (src);
   1756       if (src & 0x40)
   1757 	*pval |= 0xFFFFFF80;
   1758       else
   1759 	*pval &= 0x7F;
   1760     }
   1761 
   1762   if (op == 0)
   1763     {
   1764       OUTS (outf, dregs (dst));
   1765       OUTS (outf, " = ");
   1766       OUTS (outf, imm7 (src));
   1767       OUTS (outf, " (X);\t\t/*\t\t");
   1768       OUTS (outf, dregs (dst));
   1769       OUTS (outf, "=");
   1770       OUTS (outf, uimm32 (*pval));
   1771       OUTS (outf, "(");
   1772       OUTS (outf, imm32 (*pval));
   1773       OUTS (outf, ") */");
   1774       priv->comment = TRUE;
   1775     }
   1776   else if (op == 1)
   1777     {
   1778       OUTS (outf, dregs (dst));
   1779       OUTS (outf, " += ");
   1780       OUTS (outf, imm7 (src));
   1781       OUTS (outf, ";\t\t/* (");
   1782       OUTS (outf, imm7d (src));
   1783       OUTS (outf, ") */");
   1784       priv->comment = TRUE;
   1785     }
   1786   else
   1787     return 0;
   1788 
   1789   return 2;
   1790 }
   1791 
   1792 static int
   1793 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
   1794 {
   1795   struct private *priv = outf->private_data;
   1796   /* COMPI2opP
   1797      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1798      | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
   1799      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1800   int op  = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
   1801   int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
   1802   int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
   1803 
   1804   bu32 *pval = get_allreg (1, dst);
   1805 
   1806   if (priv->parallel)
   1807     return 0;
   1808 
   1809   if (op == 0)
   1810     {
   1811       *pval = imm7_val (src);
   1812       if (src & 0x40)
   1813 	*pval |= 0xFFFFFF80;
   1814       else
   1815 	*pval &= 0x7F;
   1816     }
   1817 
   1818   if (op == 0)
   1819     {
   1820       OUTS (outf, pregs (dst));
   1821       OUTS (outf, " = ");
   1822       OUTS (outf, imm7 (src));
   1823       OUTS (outf, " (X);\t\t/*\t\t");
   1824       OUTS (outf, pregs (dst));
   1825       OUTS (outf, "=");
   1826       OUTS (outf, uimm32 (*pval));
   1827       OUTS (outf, "(");
   1828       OUTS (outf, imm32 (*pval));
   1829       OUTS (outf, ") */");
   1830       priv->comment = TRUE;
   1831     }
   1832   else if (op == 1)
   1833     {
   1834       OUTS (outf, pregs (dst));
   1835       OUTS (outf, " += ");
   1836       OUTS (outf, imm7 (src));
   1837       OUTS (outf, ";\t\t/* (");
   1838       OUTS (outf, imm7d (src));
   1839       OUTS (outf, ") */");
   1840       priv->comment = TRUE;
   1841     }
   1842   else
   1843     return 0;
   1844 
   1845   return 2;
   1846 }
   1847 
   1848 static int
   1849 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
   1850 {
   1851   /* LDSTpmod
   1852      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1853      | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
   1854      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1855   int W   = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
   1856   int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
   1857   int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
   1858   int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
   1859   int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
   1860 
   1861   if (aop == 1 && W == 0 && idx == ptr)
   1862     {
   1863       OUTS (outf, dregs_lo (reg));
   1864       OUTS (outf, " = W[");
   1865       OUTS (outf, pregs (ptr));
   1866       OUTS (outf, "]");
   1867     }
   1868   else if (aop == 2 && W == 0 && idx == ptr)
   1869     {
   1870       OUTS (outf, dregs_hi (reg));
   1871       OUTS (outf, " = W[");
   1872       OUTS (outf, pregs (ptr));
   1873       OUTS (outf, "]");
   1874     }
   1875   else if (aop == 1 && W == 1 && idx == ptr)
   1876     {
   1877       OUTS (outf, "W[");
   1878       OUTS (outf, pregs (ptr));
   1879       OUTS (outf, "] = ");
   1880       OUTS (outf, dregs_lo (reg));
   1881     }
   1882   else if (aop == 2 && W == 1 && idx == ptr)
   1883     {
   1884       OUTS (outf, "W[");
   1885       OUTS (outf, pregs (ptr));
   1886       OUTS (outf, "] = ");
   1887       OUTS (outf, dregs_hi (reg));
   1888     }
   1889   else if (aop == 0 && W == 0)
   1890     {
   1891       OUTS (outf, dregs (reg));
   1892       OUTS (outf, " = [");
   1893       OUTS (outf, pregs (ptr));
   1894       OUTS (outf, " ++ ");
   1895       OUTS (outf, pregs (idx));
   1896       OUTS (outf, "]");
   1897     }
   1898   else if (aop == 1 && W == 0)
   1899     {
   1900       OUTS (outf, dregs_lo (reg));
   1901       OUTS (outf, " = W[");
   1902       OUTS (outf, pregs (ptr));
   1903       OUTS (outf, " ++ ");
   1904       OUTS (outf, pregs (idx));
   1905       OUTS (outf, "]");
   1906     }
   1907   else if (aop == 2 && W == 0)
   1908     {
   1909       OUTS (outf, dregs_hi (reg));
   1910       OUTS (outf, " = W[");
   1911       OUTS (outf, pregs (ptr));
   1912       OUTS (outf, " ++ ");
   1913       OUTS (outf, pregs (idx));
   1914       OUTS (outf, "]");
   1915     }
   1916   else if (aop == 3 && W == 0)
   1917     {
   1918       OUTS (outf, dregs (reg));
   1919       OUTS (outf, " = W[");
   1920       OUTS (outf, pregs (ptr));
   1921       OUTS (outf, " ++ ");
   1922       OUTS (outf, pregs (idx));
   1923       OUTS (outf, "] (Z)");
   1924     }
   1925   else if (aop == 3 && W == 1)
   1926     {
   1927       OUTS (outf, dregs (reg));
   1928       OUTS (outf, " = W[");
   1929       OUTS (outf, pregs (ptr));
   1930       OUTS (outf, " ++ ");
   1931       OUTS (outf, pregs (idx));
   1932       OUTS (outf, "] (X)");
   1933     }
   1934   else if (aop == 0 && W == 1)
   1935     {
   1936       OUTS (outf, "[");
   1937       OUTS (outf, pregs (ptr));
   1938       OUTS (outf, " ++ ");
   1939       OUTS (outf, pregs (idx));
   1940       OUTS (outf, "] = ");
   1941       OUTS (outf, dregs (reg));
   1942     }
   1943   else if (aop == 1 && W == 1)
   1944     {
   1945       OUTS (outf, "W[");
   1946       OUTS (outf, pregs (ptr));
   1947       OUTS (outf, " ++ ");
   1948       OUTS (outf, pregs (idx));
   1949       OUTS (outf, "] = ");
   1950       OUTS (outf, dregs_lo (reg));
   1951     }
   1952   else if (aop == 2 && W == 1)
   1953     {
   1954       OUTS (outf, "W[");
   1955       OUTS (outf, pregs (ptr));
   1956       OUTS (outf, " ++ ");
   1957       OUTS (outf, pregs (idx));
   1958       OUTS (outf, "] = ");
   1959       OUTS (outf, dregs_hi (reg));
   1960     }
   1961   else
   1962     return 0;
   1963 
   1964   return 2;
   1965 }
   1966 
   1967 static int
   1968 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
   1969 {
   1970   /* dagMODim
   1971      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   1972      | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
   1973      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   1974   int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
   1975   int m  = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
   1976   int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
   1977   int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
   1978 
   1979   if (op == 0 && br == 1)
   1980     {
   1981       OUTS (outf, iregs (i));
   1982       OUTS (outf, " += ");
   1983       OUTS (outf, mregs (m));
   1984       OUTS (outf, " (BREV)");
   1985     }
   1986   else if (op == 0)
   1987     {
   1988       OUTS (outf, iregs (i));
   1989       OUTS (outf, " += ");
   1990       OUTS (outf, mregs (m));
   1991     }
   1992   else if (op == 1 && br == 0)
   1993     {
   1994       OUTS (outf, iregs (i));
   1995       OUTS (outf, " -= ");
   1996       OUTS (outf, mregs (m));
   1997     }
   1998   else
   1999     return 0;
   2000 
   2001   return 2;
   2002 }
   2003 
   2004 static int
   2005 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
   2006 {
   2007   struct private *priv = outf->private_data;
   2008   /* dagMODik
   2009      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2010      | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
   2011      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2012   int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
   2013   int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
   2014 
   2015   if (op == 0)
   2016     {
   2017       OUTS (outf, iregs (i));
   2018       OUTS (outf, " += 0x2");
   2019     }
   2020   else if (op == 1)
   2021     {
   2022       OUTS (outf, iregs (i));
   2023       OUTS (outf, " -= 0x2");
   2024     }
   2025   else if (op == 2)
   2026     {
   2027       OUTS (outf, iregs (i));
   2028       OUTS (outf, " += 0x4");
   2029     }
   2030   else if (op == 3)
   2031     {
   2032       OUTS (outf, iregs (i));
   2033       OUTS (outf, " -= 0x4");
   2034     }
   2035   else
   2036     return 0;
   2037 
   2038   if (!priv->parallel)
   2039     {
   2040       OUTS (outf, ";\t\t/* (  ");
   2041       if (op == 0 || op == 1)
   2042 	OUTS (outf, "2");
   2043       else if (op == 2 || op == 3)
   2044 	OUTS (outf, "4");
   2045       OUTS (outf, ") */");
   2046       priv->comment = TRUE;
   2047     }
   2048 
   2049   return 2;
   2050 }
   2051 
   2052 static int
   2053 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
   2054 {
   2055   /* dspLDST
   2056      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2057      | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
   2058      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2059   int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
   2060   int m   = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
   2061   int W   = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
   2062   int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
   2063   int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
   2064 
   2065   if (aop == 0 && W == 0 && m == 0)
   2066     {
   2067       OUTS (outf, dregs (reg));
   2068       OUTS (outf, " = [");
   2069       OUTS (outf, iregs (i));
   2070       OUTS (outf, "++]");
   2071     }
   2072   else if (aop == 0 && W == 0 && m == 1)
   2073     {
   2074       OUTS (outf, dregs_lo (reg));
   2075       OUTS (outf, " = W[");
   2076       OUTS (outf, iregs (i));
   2077       OUTS (outf, "++]");
   2078     }
   2079   else if (aop == 0 && W == 0 && m == 2)
   2080     {
   2081       OUTS (outf, dregs_hi (reg));
   2082       OUTS (outf, " = W[");
   2083       OUTS (outf, iregs (i));
   2084       OUTS (outf, "++]");
   2085     }
   2086   else if (aop == 1 && W == 0 && m == 0)
   2087     {
   2088       OUTS (outf, dregs (reg));
   2089       OUTS (outf, " = [");
   2090       OUTS (outf, iregs (i));
   2091       OUTS (outf, "--]");
   2092     }
   2093   else if (aop == 1 && W == 0 && m == 1)
   2094     {
   2095       OUTS (outf, dregs_lo (reg));
   2096       OUTS (outf, " = W[");
   2097       OUTS (outf, iregs (i));
   2098       OUTS (outf, "--]");
   2099     }
   2100   else if (aop == 1 && W == 0 && m == 2)
   2101     {
   2102       OUTS (outf, dregs_hi (reg));
   2103       OUTS (outf, " = W[");
   2104       OUTS (outf, iregs (i));
   2105       OUTS (outf, "--]");
   2106     }
   2107   else if (aop == 2 && W == 0 && m == 0)
   2108     {
   2109       OUTS (outf, dregs (reg));
   2110       OUTS (outf, " = [");
   2111       OUTS (outf, iregs (i));
   2112       OUTS (outf, "]");
   2113     }
   2114   else if (aop == 2 && W == 0 && m == 1)
   2115     {
   2116       OUTS (outf, dregs_lo (reg));
   2117       OUTS (outf, " = W[");
   2118       OUTS (outf, iregs (i));
   2119       OUTS (outf, "]");
   2120     }
   2121   else if (aop == 2 && W == 0 && m == 2)
   2122     {
   2123       OUTS (outf, dregs_hi (reg));
   2124       OUTS (outf, " = W[");
   2125       OUTS (outf, iregs (i));
   2126       OUTS (outf, "]");
   2127     }
   2128   else if (aop == 0 && W == 1 && m == 0)
   2129     {
   2130       OUTS (outf, "[");
   2131       OUTS (outf, iregs (i));
   2132       OUTS (outf, "++] = ");
   2133       OUTS (outf, dregs (reg));
   2134     }
   2135   else if (aop == 0 && W == 1 && m == 1)
   2136     {
   2137       OUTS (outf, "W[");
   2138       OUTS (outf, iregs (i));
   2139       OUTS (outf, "++] = ");
   2140       OUTS (outf, dregs_lo (reg));
   2141     }
   2142   else if (aop == 0 && W == 1 && m == 2)
   2143     {
   2144       OUTS (outf, "W[");
   2145       OUTS (outf, iregs (i));
   2146       OUTS (outf, "++] = ");
   2147       OUTS (outf, dregs_hi (reg));
   2148     }
   2149   else if (aop == 1 && W == 1 && m == 0)
   2150     {
   2151       OUTS (outf, "[");
   2152       OUTS (outf, iregs (i));
   2153       OUTS (outf, "--] = ");
   2154       OUTS (outf, dregs (reg));
   2155     }
   2156   else if (aop == 1 && W == 1 && m == 1)
   2157     {
   2158       OUTS (outf, "W[");
   2159       OUTS (outf, iregs (i));
   2160       OUTS (outf, "--] = ");
   2161       OUTS (outf, dregs_lo (reg));
   2162     }
   2163   else if (aop == 1 && W == 1 && m == 2)
   2164     {
   2165       OUTS (outf, "W[");
   2166       OUTS (outf, iregs (i));
   2167       OUTS (outf, "--] = ");
   2168       OUTS (outf, dregs_hi (reg));
   2169     }
   2170   else if (aop == 2 && W == 1 && m == 0)
   2171     {
   2172       OUTS (outf, "[");
   2173       OUTS (outf, iregs (i));
   2174       OUTS (outf, "] = ");
   2175       OUTS (outf, dregs (reg));
   2176     }
   2177   else if (aop == 2 && W == 1 && m == 1)
   2178     {
   2179       OUTS (outf, "W[");
   2180       OUTS (outf, iregs (i));
   2181       OUTS (outf, "] = ");
   2182       OUTS (outf, dregs_lo (reg));
   2183     }
   2184   else if (aop == 2 && W == 1 && m == 2)
   2185     {
   2186       OUTS (outf, "W[");
   2187       OUTS (outf, iregs (i));
   2188       OUTS (outf, "] = ");
   2189       OUTS (outf, dregs_hi (reg));
   2190     }
   2191   else if (aop == 3 && W == 0)
   2192     {
   2193       OUTS (outf, dregs (reg));
   2194       OUTS (outf, " = [");
   2195       OUTS (outf, iregs (i));
   2196       OUTS (outf, " ++ ");
   2197       OUTS (outf, mregs (m));
   2198       OUTS (outf, "]");
   2199     }
   2200   else if (aop == 3 && W == 1)
   2201     {
   2202       OUTS (outf, "[");
   2203       OUTS (outf, iregs (i));
   2204       OUTS (outf, " ++ ");
   2205       OUTS (outf, mregs (m));
   2206       OUTS (outf, "] = ");
   2207       OUTS (outf, dregs (reg));
   2208     }
   2209   else
   2210     return 0;
   2211 
   2212   return 2;
   2213 }
   2214 
   2215 static int
   2216 decode_LDST_0 (TIword iw0, disassemble_info *outf)
   2217 {
   2218   /* LDST
   2219      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2220      | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
   2221      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2222   int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
   2223   int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
   2224   int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
   2225   int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
   2226   int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
   2227   int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
   2228 
   2229   if (aop == 0 && sz == 0 && Z == 0 && W == 0)
   2230     {
   2231       OUTS (outf, dregs (reg));
   2232       OUTS (outf, " = [");
   2233       OUTS (outf, pregs (ptr));
   2234       OUTS (outf, "++]");
   2235     }
   2236   else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
   2237     {
   2238       OUTS (outf, pregs (reg));
   2239       OUTS (outf, " = [");
   2240       OUTS (outf, pregs (ptr));
   2241       OUTS (outf, "++]");
   2242     }
   2243   else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
   2244     {
   2245       OUTS (outf, dregs (reg));
   2246       OUTS (outf, " = W[");
   2247       OUTS (outf, pregs (ptr));
   2248       OUTS (outf, "++] (Z)");
   2249     }
   2250   else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
   2251     {
   2252       OUTS (outf, dregs (reg));
   2253       OUTS (outf, " = W[");
   2254       OUTS (outf, pregs (ptr));
   2255       OUTS (outf, "++] (X)");
   2256     }
   2257   else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
   2258     {
   2259       OUTS (outf, dregs (reg));
   2260       OUTS (outf, " = B[");
   2261       OUTS (outf, pregs (ptr));
   2262       OUTS (outf, "++] (Z)");
   2263     }
   2264   else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
   2265     {
   2266       OUTS (outf, dregs (reg));
   2267       OUTS (outf, " = B[");
   2268       OUTS (outf, pregs (ptr));
   2269       OUTS (outf, "++] (X)");
   2270     }
   2271   else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
   2272     {
   2273       OUTS (outf, dregs (reg));
   2274       OUTS (outf, " = [");
   2275       OUTS (outf, pregs (ptr));
   2276       OUTS (outf, "--]");
   2277     }
   2278   else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
   2279     {
   2280       OUTS (outf, pregs (reg));
   2281       OUTS (outf, " = [");
   2282       OUTS (outf, pregs (ptr));
   2283       OUTS (outf, "--]");
   2284     }
   2285   else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
   2286     {
   2287       OUTS (outf, dregs (reg));
   2288       OUTS (outf, " = W[");
   2289       OUTS (outf, pregs (ptr));
   2290       OUTS (outf, "--] (Z)");
   2291     }
   2292   else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
   2293     {
   2294       OUTS (outf, dregs (reg));
   2295       OUTS (outf, " = W[");
   2296       OUTS (outf, pregs (ptr));
   2297       OUTS (outf, "--] (X)");
   2298     }
   2299   else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
   2300     {
   2301       OUTS (outf, dregs (reg));
   2302       OUTS (outf, " = B[");
   2303       OUTS (outf, pregs (ptr));
   2304       OUTS (outf, "--] (Z)");
   2305     }
   2306   else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
   2307     {
   2308       OUTS (outf, dregs (reg));
   2309       OUTS (outf, " = B[");
   2310       OUTS (outf, pregs (ptr));
   2311       OUTS (outf, "--] (X)");
   2312     }
   2313   else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
   2314     {
   2315       OUTS (outf, dregs (reg));
   2316       OUTS (outf, " = [");
   2317       OUTS (outf, pregs (ptr));
   2318       OUTS (outf, "]");
   2319     }
   2320   else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
   2321     {
   2322       OUTS (outf, pregs (reg));
   2323       OUTS (outf, " = [");
   2324       OUTS (outf, pregs (ptr));
   2325       OUTS (outf, "]");
   2326     }
   2327   else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
   2328     {
   2329       OUTS (outf, dregs (reg));
   2330       OUTS (outf, " = W[");
   2331       OUTS (outf, pregs (ptr));
   2332       OUTS (outf, "] (Z)");
   2333     }
   2334   else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
   2335     {
   2336       OUTS (outf, dregs (reg));
   2337       OUTS (outf, " = W[");
   2338       OUTS (outf, pregs (ptr));
   2339       OUTS (outf, "] (X)");
   2340     }
   2341   else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
   2342     {
   2343       OUTS (outf, dregs (reg));
   2344       OUTS (outf, " = B[");
   2345       OUTS (outf, pregs (ptr));
   2346       OUTS (outf, "] (Z)");
   2347     }
   2348   else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
   2349     {
   2350       OUTS (outf, dregs (reg));
   2351       OUTS (outf, " = B[");
   2352       OUTS (outf, pregs (ptr));
   2353       OUTS (outf, "] (X)");
   2354     }
   2355   else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
   2356     {
   2357       OUTS (outf, "[");
   2358       OUTS (outf, pregs (ptr));
   2359       OUTS (outf, "++] = ");
   2360       OUTS (outf, dregs (reg));
   2361     }
   2362   else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
   2363     {
   2364       OUTS (outf, "[");
   2365       OUTS (outf, pregs (ptr));
   2366       OUTS (outf, "++] = ");
   2367       OUTS (outf, pregs (reg));
   2368     }
   2369   else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
   2370     {
   2371       OUTS (outf, "W[");
   2372       OUTS (outf, pregs (ptr));
   2373       OUTS (outf, "++] = ");
   2374       OUTS (outf, dregs (reg));
   2375     }
   2376   else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
   2377     {
   2378       OUTS (outf, "B[");
   2379       OUTS (outf, pregs (ptr));
   2380       OUTS (outf, "++] = ");
   2381       OUTS (outf, dregs (reg));
   2382     }
   2383   else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
   2384     {
   2385       OUTS (outf, "[");
   2386       OUTS (outf, pregs (ptr));
   2387       OUTS (outf, "--] = ");
   2388       OUTS (outf, dregs (reg));
   2389     }
   2390   else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
   2391     {
   2392       OUTS (outf, "[");
   2393       OUTS (outf, pregs (ptr));
   2394       OUTS (outf, "--] = ");
   2395       OUTS (outf, pregs (reg));
   2396     }
   2397   else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
   2398     {
   2399       OUTS (outf, "W[");
   2400       OUTS (outf, pregs (ptr));
   2401       OUTS (outf, "--] = ");
   2402       OUTS (outf, dregs (reg));
   2403     }
   2404   else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
   2405     {
   2406       OUTS (outf, "B[");
   2407       OUTS (outf, pregs (ptr));
   2408       OUTS (outf, "--] = ");
   2409       OUTS (outf, dregs (reg));
   2410     }
   2411   else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
   2412     {
   2413       OUTS (outf, "[");
   2414       OUTS (outf, pregs (ptr));
   2415       OUTS (outf, "] = ");
   2416       OUTS (outf, dregs (reg));
   2417     }
   2418   else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
   2419     {
   2420       OUTS (outf, "[");
   2421       OUTS (outf, pregs (ptr));
   2422       OUTS (outf, "] = ");
   2423       OUTS (outf, pregs (reg));
   2424     }
   2425   else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
   2426     {
   2427       OUTS (outf, "W[");
   2428       OUTS (outf, pregs (ptr));
   2429       OUTS (outf, "] = ");
   2430       OUTS (outf, dregs (reg));
   2431     }
   2432   else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
   2433     {
   2434       OUTS (outf, "B[");
   2435       OUTS (outf, pregs (ptr));
   2436       OUTS (outf, "] = ");
   2437       OUTS (outf, dregs (reg));
   2438     }
   2439   else
   2440     return 0;
   2441 
   2442   return 2;
   2443 }
   2444 
   2445 static int
   2446 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
   2447 {
   2448   /* LDSTiiFP
   2449      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2450      | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
   2451      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2452   int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
   2453   int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
   2454   int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
   2455 
   2456   if (W == 0)
   2457     {
   2458       OUTS (outf, dpregs (reg));
   2459       OUTS (outf, " = [FP ");
   2460       OUTS (outf, negimm5s4 (offset));
   2461       OUTS (outf, "]");
   2462     }
   2463   else if (W == 1)
   2464     {
   2465       OUTS (outf, "[FP ");
   2466       OUTS (outf, negimm5s4 (offset));
   2467       OUTS (outf, "] = ");
   2468       OUTS (outf, dpregs (reg));
   2469     }
   2470   else
   2471     return 0;
   2472 
   2473   return 2;
   2474 }
   2475 
   2476 static int
   2477 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
   2478 {
   2479   /* LDSTii
   2480      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2481      | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
   2482      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2483   int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
   2484   int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
   2485   int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
   2486   int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
   2487   int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
   2488 
   2489   if (W == 0 && op == 0)
   2490     {
   2491       OUTS (outf, dregs (reg));
   2492       OUTS (outf, " = [");
   2493       OUTS (outf, pregs (ptr));
   2494       OUTS (outf, " + ");
   2495       OUTS (outf, uimm4s4 (offset));
   2496       OUTS (outf, "]");
   2497     }
   2498   else if (W == 0 && op == 1)
   2499     {
   2500       OUTS (outf, dregs (reg));
   2501       OUTS (outf, " = W[");
   2502       OUTS (outf, pregs (ptr));
   2503       OUTS (outf, " + ");
   2504       OUTS (outf, uimm4s2 (offset));
   2505       OUTS (outf, "] (Z)");
   2506     }
   2507   else if (W == 0 && op == 2)
   2508     {
   2509       OUTS (outf, dregs (reg));
   2510       OUTS (outf, " = W[");
   2511       OUTS (outf, pregs (ptr));
   2512       OUTS (outf, " + ");
   2513       OUTS (outf, uimm4s2 (offset));
   2514       OUTS (outf, "] (X)");
   2515     }
   2516   else if (W == 0 && op == 3)
   2517     {
   2518       OUTS (outf, pregs (reg));
   2519       OUTS (outf, " = [");
   2520       OUTS (outf, pregs (ptr));
   2521       OUTS (outf, " + ");
   2522       OUTS (outf, uimm4s4 (offset));
   2523       OUTS (outf, "]");
   2524     }
   2525   else if (W == 1 && op == 0)
   2526     {
   2527       OUTS (outf, "[");
   2528       OUTS (outf, pregs (ptr));
   2529       OUTS (outf, " + ");
   2530       OUTS (outf, uimm4s4 (offset));
   2531       OUTS (outf, "] = ");
   2532       OUTS (outf, dregs (reg));
   2533     }
   2534   else if (W == 1 && op == 1)
   2535     {
   2536       OUTS (outf, "W[");
   2537       OUTS (outf, pregs (ptr));
   2538       OUTS (outf, " + ");
   2539       OUTS (outf, uimm4s2 (offset));
   2540       OUTS (outf, "] = ");
   2541       OUTS (outf, dregs (reg));
   2542     }
   2543   else if (W == 1 && op == 3)
   2544     {
   2545       OUTS (outf, "[");
   2546       OUTS (outf, pregs (ptr));
   2547       OUTS (outf, " + ");
   2548       OUTS (outf, uimm4s4 (offset));
   2549       OUTS (outf, "] = ");
   2550       OUTS (outf, pregs (reg));
   2551     }
   2552   else
   2553     return 0;
   2554 
   2555   return 2;
   2556 }
   2557 
   2558 static int
   2559 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
   2560 {
   2561   struct private *priv = outf->private_data;
   2562   /* LoopSetup
   2563      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2564      | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
   2565      |.reg...........| - | - |.eoffset...............................|
   2566      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2567   int c   = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
   2568   int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
   2569   int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
   2570   int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
   2571   int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
   2572 
   2573   if (priv->parallel)
   2574     return 0;
   2575 
   2576   if (reg > 7)
   2577     return 0;
   2578 
   2579   if (rop == 0)
   2580     {
   2581       OUTS (outf, "LSETUP");
   2582       OUTS (outf, "(0x");
   2583       OUTS (outf, pcrel4 (soffset));
   2584       OUTS (outf, ", 0x");
   2585       OUTS (outf, lppcrel10 (eoffset));
   2586       OUTS (outf, ") ");
   2587       OUTS (outf, counters (c));
   2588     }
   2589   else if (rop == 1)
   2590     {
   2591       OUTS (outf, "LSETUP");
   2592       OUTS (outf, "(0x");
   2593       OUTS (outf, pcrel4 (soffset));
   2594       OUTS (outf, ", 0x");
   2595       OUTS (outf, lppcrel10 (eoffset));
   2596       OUTS (outf, ") ");
   2597       OUTS (outf, counters (c));
   2598       OUTS (outf, " = ");
   2599       OUTS (outf, pregs (reg));
   2600     }
   2601   else if (rop == 3)
   2602     {
   2603       OUTS (outf, "LSETUP");
   2604       OUTS (outf, "(0x");
   2605       OUTS (outf, pcrel4 (soffset));
   2606       OUTS (outf, ", 0x");
   2607       OUTS (outf, lppcrel10 (eoffset));
   2608       OUTS (outf, ") ");
   2609       OUTS (outf, counters (c));
   2610       OUTS (outf, " = ");
   2611       OUTS (outf, pregs (reg));
   2612       OUTS (outf, " >> 0x1");
   2613     }
   2614   else
   2615     return 0;
   2616 
   2617   return 4;
   2618 }
   2619 
   2620 static int
   2621 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
   2622 {
   2623   struct private *priv = outf->private_data;
   2624   /* LDIMMhalf
   2625      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2626      | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
   2627      |.hword.........................................................|
   2628      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2629   int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
   2630   int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
   2631   int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
   2632   int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
   2633   int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
   2634   int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
   2635 
   2636   bu32 *pval = get_allreg (grp, reg);
   2637 
   2638   if (priv->parallel)
   2639     return 0;
   2640 
   2641   /* Since we don't have 32-bit immediate loads, we allow the disassembler
   2642      to combine them, so it prints out the right values.
   2643      Here we keep track of the registers.  */
   2644   if (H == 0 && S == 1 && Z == 0)
   2645     {
   2646       /* regs = imm16 (x) */
   2647       *pval = imm16_val (hword);
   2648       if (hword & 0x8000)
   2649 	*pval |= 0xFFFF0000;
   2650       else
   2651 	*pval &= 0xFFFF;
   2652     }
   2653   else if (H == 0 && S == 0 && Z == 1)
   2654     {
   2655       /* regs = luimm16 (Z) */
   2656       *pval = luimm16_val (hword);
   2657       *pval &= 0xFFFF;
   2658     }
   2659   else if (H == 0 && S == 0 && Z == 0)
   2660     {
   2661       /* regs_lo = luimm16 */
   2662       *pval &= 0xFFFF0000;
   2663       *pval |= luimm16_val (hword);
   2664     }
   2665   else if (H == 1 && S == 0 && Z == 0)
   2666     {
   2667       /* regs_hi = huimm16 */
   2668       *pval &= 0xFFFF;
   2669       *pval |= luimm16_val (hword) << 16;
   2670     }
   2671 
   2672   /* Here we do the disassembly */
   2673   if (grp == 0 && H == 0 && S == 0 && Z == 0)
   2674     {
   2675       OUTS (outf, dregs_lo (reg));
   2676       OUTS (outf, " = ");
   2677       OUTS (outf, uimm16 (hword));
   2678     }
   2679   else if (grp == 0 && H == 1 && S == 0 && Z == 0)
   2680     {
   2681       OUTS (outf, dregs_hi (reg));
   2682       OUTS (outf, " = ");
   2683       OUTS (outf, uimm16 (hword));
   2684     }
   2685   else if (grp == 0 && H == 0 && S == 1 && Z == 0)
   2686     {
   2687       OUTS (outf, dregs (reg));
   2688       OUTS (outf, " = ");
   2689       OUTS (outf, imm16 (hword));
   2690       OUTS (outf, " (X)");
   2691     }
   2692   else if (H == 0 && S == 1 && Z == 0)
   2693     {
   2694       OUTS (outf, regs (reg, grp));
   2695       OUTS (outf, " = ");
   2696       OUTS (outf, imm16 (hword));
   2697       OUTS (outf, " (X)");
   2698     }
   2699   else if (H == 0 && S == 0 && Z == 1)
   2700     {
   2701       OUTS (outf, regs (reg, grp));
   2702       OUTS (outf, " = ");
   2703       OUTS (outf, uimm16 (hword));
   2704       OUTS (outf, " (Z)");
   2705     }
   2706   else if (H == 0 && S == 0 && Z == 0)
   2707     {
   2708       OUTS (outf, regs_lo (reg, grp));
   2709       OUTS (outf, " = ");
   2710       OUTS (outf, uimm16 (hword));
   2711     }
   2712   else if (H == 1 && S == 0 && Z == 0)
   2713     {
   2714       OUTS (outf, regs_hi (reg, grp));
   2715       OUTS (outf, " = ");
   2716       OUTS (outf, uimm16 (hword));
   2717     }
   2718   else
   2719     return 0;
   2720 
   2721   /* And we print out the 32-bit value if it is a pointer.  */
   2722   if (S == 0 && Z == 0)
   2723     {
   2724       OUTS (outf, ";\t\t/* (");
   2725       OUTS (outf, imm16d (hword));
   2726       OUTS (outf, ")\t");
   2727 
   2728       /* If it is an MMR, don't print the symbol.  */
   2729       if (*pval < 0xFFC00000 && grp == 1)
   2730 	{
   2731 	  OUTS (outf, regs (reg, grp));
   2732 	  OUTS (outf, "=0x");
   2733 	  OUTS (outf, huimm32e (*pval));
   2734 	}
   2735       else
   2736 	{
   2737 	  OUTS (outf, regs (reg, grp));
   2738 	  OUTS (outf, "=0x");
   2739 	  OUTS (outf, huimm32e (*pval));
   2740 	  OUTS (outf, "(");
   2741 	  OUTS (outf, imm32 (*pval));
   2742 	  OUTS (outf, ")");
   2743 	}
   2744 
   2745       OUTS (outf, " */");
   2746       priv->comment = TRUE;
   2747     }
   2748   if (S == 1 || Z == 1)
   2749     {
   2750       OUTS (outf, ";\t\t/*\t\t");
   2751       OUTS (outf, regs (reg, grp));
   2752       OUTS (outf, "=0x");
   2753       OUTS (outf, huimm32e (*pval));
   2754       OUTS (outf, "(");
   2755       OUTS (outf, imm32 (*pval));
   2756       OUTS (outf, ") */");
   2757       priv->comment = TRUE;
   2758     }
   2759   return 4;
   2760 }
   2761 
   2762 static int
   2763 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
   2764 {
   2765   struct private *priv = outf->private_data;
   2766   /* CALLa
   2767      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2768      | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
   2769      |.lsw...........................................................|
   2770      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2771   int S   = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
   2772   int lsw = ((iw1 >> 0) & 0xffff);
   2773   int msw = ((iw0 >> 0) & 0xff);
   2774 
   2775   if (priv->parallel)
   2776     return 0;
   2777 
   2778   if (S == 1)
   2779     OUTS (outf, "CALL 0x");
   2780   else if (S == 0)
   2781     OUTS (outf, "JUMP.L 0x");
   2782   else
   2783     return 0;
   2784 
   2785   OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
   2786   return 4;
   2787 }
   2788 
   2789 static int
   2790 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
   2791 {
   2792   /* LDSTidxI
   2793      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2794      | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
   2795      |.offset........................................................|
   2796      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2797   int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
   2798   int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
   2799   int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
   2800   int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
   2801   int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
   2802   int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
   2803 
   2804   if (W == 0 && sz == 0 && Z == 0)
   2805     {
   2806       OUTS (outf, dregs (reg));
   2807       OUTS (outf, " = [");
   2808       OUTS (outf, pregs (ptr));
   2809       OUTS (outf, " + ");
   2810       OUTS (outf, imm16s4 (offset));
   2811       OUTS (outf, "]");
   2812     }
   2813   else if (W == 0 && sz == 0 && Z == 1)
   2814     {
   2815       OUTS (outf, pregs (reg));
   2816       OUTS (outf, " = [");
   2817       OUTS (outf, pregs (ptr));
   2818       OUTS (outf, " + ");
   2819       OUTS (outf, imm16s4 (offset));
   2820       OUTS (outf, "]");
   2821     }
   2822   else if (W == 0 && sz == 1 && Z == 0)
   2823     {
   2824       OUTS (outf, dregs (reg));
   2825       OUTS (outf, " = W[");
   2826       OUTS (outf, pregs (ptr));
   2827       OUTS (outf, " + ");
   2828       OUTS (outf, imm16s2 (offset));
   2829       OUTS (outf, "] (Z)");
   2830     }
   2831   else if (W == 0 && sz == 1 && Z == 1)
   2832     {
   2833       OUTS (outf, dregs (reg));
   2834       OUTS (outf, " = W[");
   2835       OUTS (outf, pregs (ptr));
   2836       OUTS (outf, " + ");
   2837       OUTS (outf, imm16s2 (offset));
   2838       OUTS (outf, "] (X)");
   2839     }
   2840   else if (W == 0 && sz == 2 && Z == 0)
   2841     {
   2842       OUTS (outf, dregs (reg));
   2843       OUTS (outf, " = B[");
   2844       OUTS (outf, pregs (ptr));
   2845       OUTS (outf, " + ");
   2846       OUTS (outf, imm16 (offset));
   2847       OUTS (outf, "] (Z)");
   2848     }
   2849   else if (W == 0 && sz == 2 && Z == 1)
   2850     {
   2851       OUTS (outf, dregs (reg));
   2852       OUTS (outf, " = B[");
   2853       OUTS (outf, pregs (ptr));
   2854       OUTS (outf, " + ");
   2855       OUTS (outf, imm16 (offset));
   2856       OUTS (outf, "] (X)");
   2857     }
   2858   else if (W == 1 && sz == 0 && Z == 0)
   2859     {
   2860       OUTS (outf, "[");
   2861       OUTS (outf, pregs (ptr));
   2862       OUTS (outf, " + ");
   2863       OUTS (outf, imm16s4 (offset));
   2864       OUTS (outf, "] = ");
   2865       OUTS (outf, dregs (reg));
   2866     }
   2867   else if (W == 1 && sz == 0 && Z == 1)
   2868     {
   2869       OUTS (outf, "[");
   2870       OUTS (outf, pregs (ptr));
   2871       OUTS (outf, " + ");
   2872       OUTS (outf, imm16s4 (offset));
   2873       OUTS (outf, "] = ");
   2874       OUTS (outf, pregs (reg));
   2875     }
   2876   else if (W == 1 && sz == 1 && Z == 0)
   2877     {
   2878       OUTS (outf, "W[");
   2879       OUTS (outf, pregs (ptr));
   2880       OUTS (outf, " + ");
   2881       OUTS (outf, imm16s2 (offset));
   2882       OUTS (outf, "] = ");
   2883       OUTS (outf, dregs (reg));
   2884     }
   2885   else if (W == 1 && sz == 2 && Z == 0)
   2886     {
   2887       OUTS (outf, "B[");
   2888       OUTS (outf, pregs (ptr));
   2889       OUTS (outf, " + ");
   2890       OUTS (outf, imm16 (offset));
   2891       OUTS (outf, "] = ");
   2892       OUTS (outf, dregs (reg));
   2893     }
   2894   else
   2895     return 0;
   2896 
   2897   return 4;
   2898 }
   2899 
   2900 static int
   2901 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
   2902 {
   2903   struct private *priv = outf->private_data;
   2904   /* linkage
   2905      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2906      | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
   2907      |.framesize.....................................................|
   2908      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2909   int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
   2910   int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
   2911 
   2912   if (priv->parallel)
   2913     return 0;
   2914 
   2915   if (R == 0)
   2916     {
   2917       OUTS (outf, "LINK ");
   2918       OUTS (outf, uimm16s4 (framesize));
   2919       OUTS (outf, ";\t\t/* (");
   2920       OUTS (outf, uimm16s4d (framesize));
   2921       OUTS (outf, ") */");
   2922       priv->comment = TRUE;
   2923     }
   2924   else if (R == 1)
   2925     OUTS (outf, "UNLINK");
   2926   else
   2927     return 0;
   2928 
   2929   return 4;
   2930 }
   2931 
   2932 static int
   2933 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
   2934 {
   2935   /* dsp32mac
   2936      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   2937      | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
   2938      |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
   2939      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   2940   int op1  = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
   2941   int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
   2942   int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
   2943   int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
   2944   int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
   2945   int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
   2946   int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
   2947   int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
   2948   int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
   2949   int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
   2950   int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
   2951   int op0  = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
   2952   int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
   2953   int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
   2954 
   2955   if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
   2956     return 0;
   2957 
   2958   if (op1 == 3 && MM)
   2959     return 0;
   2960 
   2961   if ((w1 || w0) && mmod == M_W32)
   2962     return 0;
   2963 
   2964   if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
   2965     return 0;
   2966 
   2967   if (w1 == 1 || op1 != 3)
   2968     {
   2969       if (w1)
   2970 	OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
   2971 
   2972       if (op1 == 3)
   2973 	OUTS (outf, " = A1");
   2974       else
   2975 	{
   2976 	  if (w1)
   2977 	    OUTS (outf, " = (");
   2978 	  decode_macfunc (1, op1, h01, h11, src0, src1, outf);
   2979 	  if (w1)
   2980 	    OUTS (outf, ")");
   2981 	}
   2982 
   2983       if (w0 == 1 || op0 != 3)
   2984 	{
   2985 	  if (MM)
   2986 	    OUTS (outf, " (M)");
   2987 	  OUTS (outf, ", ");
   2988 	}
   2989     }
   2990 
   2991   if (w0 == 1 || op0 != 3)
   2992     {
   2993       /* Clear MM option since it only matters for MAC1, and if we made
   2994          it this far, we've already shown it or we want to ignore it.  */
   2995       MM = 0;
   2996 
   2997       if (w0)
   2998 	OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
   2999 
   3000       if (op0 == 3)
   3001 	OUTS (outf, " = A0");
   3002       else
   3003 	{
   3004 	  if (w0)
   3005 	    OUTS (outf, " = (");
   3006 	  decode_macfunc (0, op0, h00, h10, src0, src1, outf);
   3007 	  if (w0)
   3008 	    OUTS (outf, ")");
   3009 	}
   3010     }
   3011 
   3012   decode_optmode (mmod, MM, outf);
   3013 
   3014   return 4;
   3015 }
   3016 
   3017 static int
   3018 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
   3019 {
   3020   /* dsp32mult
   3021      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   3022      | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
   3023      |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
   3024      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   3025   int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
   3026   int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
   3027   int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
   3028   int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
   3029   int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
   3030   int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
   3031   int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
   3032   int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
   3033   int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
   3034   int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
   3035   int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
   3036   int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
   3037 
   3038   if (w1 == 0 && w0 == 0)
   3039     return 0;
   3040 
   3041   if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
   3042     return 0;
   3043 
   3044   if (w1)
   3045     {
   3046       OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
   3047       OUTS (outf, " = ");
   3048       decode_multfunc (h01, h11, src0, src1, outf);
   3049 
   3050       if (w0)
   3051 	{
   3052 	  if (MM)
   3053 	    OUTS (outf, " (M)");
   3054 	  MM = 0;
   3055 	  OUTS (outf, ", ");
   3056 	}
   3057     }
   3058 
   3059   if (w0)
   3060     {
   3061       OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
   3062       OUTS (outf, " = ");
   3063       decode_multfunc (h00, h10, src0, src1, outf);
   3064     }
   3065 
   3066   decode_optmode (mmod, MM, outf);
   3067   return 4;
   3068 }
   3069 
   3070 static int
   3071 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
   3072 {
   3073   /* dsp32alu
   3074      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   3075      | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
   3076      |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
   3077      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   3078   int s    = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
   3079   int x    = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
   3080   int aop  = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
   3081   int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
   3082   int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
   3083   int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
   3084   int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
   3085   int HL   = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
   3086   int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
   3087 
   3088   if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
   3089     {
   3090       OUTS (outf, "A0.L = ");
   3091       OUTS (outf, dregs_lo (src0));
   3092     }
   3093   else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
   3094     {
   3095       OUTS (outf, "A1.H = ");
   3096       OUTS (outf, dregs_hi (src0));
   3097     }
   3098   else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
   3099     {
   3100       OUTS (outf, "A1.L = ");
   3101       OUTS (outf, dregs_lo (src0));
   3102     }
   3103   else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
   3104     {
   3105       OUTS (outf, "A0.H = ");
   3106       OUTS (outf, dregs_hi (src0));
   3107     }
   3108   else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
   3109     {
   3110       OUTS (outf, dregs_hi (dst0));
   3111       OUTS (outf, " = ");
   3112       OUTS (outf, dregs (src0));
   3113       OUTS (outf, " - ");
   3114       OUTS (outf, dregs (src1));
   3115       OUTS (outf, " (RND20)");
   3116     }
   3117   else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
   3118     {
   3119       OUTS (outf, dregs_hi (dst0));
   3120       OUTS (outf, " = ");
   3121       OUTS (outf, dregs (src0));
   3122       OUTS (outf, " + ");
   3123       OUTS (outf, dregs (src1));
   3124       OUTS (outf, " (RND20)");
   3125     }
   3126   else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
   3127     {
   3128       OUTS (outf, dregs_lo (dst0));
   3129       OUTS (outf, " = ");
   3130       OUTS (outf, dregs (src0));
   3131       OUTS (outf, " - ");
   3132       OUTS (outf, dregs (src1));
   3133       OUTS (outf, " (RND12)");
   3134     }
   3135   else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
   3136     {
   3137       OUTS (outf, dregs_lo (dst0));
   3138       OUTS (outf, " = ");
   3139       OUTS (outf, dregs (src0));
   3140       OUTS (outf, " + ");
   3141       OUTS (outf, dregs (src1));
   3142       OUTS (outf, " (RND12)");
   3143     }
   3144   else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
   3145     {
   3146       OUTS (outf, dregs_lo (dst0));
   3147       OUTS (outf, " = ");
   3148       OUTS (outf, dregs (src0));
   3149       OUTS (outf, " - ");
   3150       OUTS (outf, dregs (src1));
   3151       OUTS (outf, " (RND20)");
   3152     }
   3153   else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
   3154     {
   3155       OUTS (outf, dregs_hi (dst0));
   3156       OUTS (outf, " = ");
   3157       OUTS (outf, dregs (src0));
   3158       OUTS (outf, " + ");
   3159       OUTS (outf, dregs (src1));
   3160       OUTS (outf, " (RND12)");
   3161     }
   3162   else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
   3163     {
   3164       OUTS (outf, dregs_lo (dst0));
   3165       OUTS (outf, " = ");
   3166       OUTS (outf, dregs (src0));
   3167       OUTS (outf, " + ");
   3168       OUTS (outf, dregs (src1));
   3169       OUTS (outf, " (RND20)");
   3170     }
   3171   else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
   3172     {
   3173       OUTS (outf, dregs_hi (dst0));
   3174       OUTS (outf, " = ");
   3175       OUTS (outf, dregs (src0));
   3176       OUTS (outf, " - ");
   3177       OUTS (outf, dregs (src1));
   3178       OUTS (outf, " (RND12)");
   3179     }
   3180   else if (HL == 1 && aop == 0 && aopcde == 2)
   3181     {
   3182       OUTS (outf, dregs_hi (dst0));
   3183       OUTS (outf, " = ");
   3184       OUTS (outf, dregs_lo (src0));
   3185       OUTS (outf, " + ");
   3186       OUTS (outf, dregs_lo (src1));
   3187       amod1 (s, x, outf);
   3188     }
   3189   else if (HL == 1 && aop == 1 && aopcde == 2)
   3190     {
   3191       OUTS (outf, dregs_hi (dst0));
   3192       OUTS (outf, " = ");
   3193       OUTS (outf, dregs_lo (src0));
   3194       OUTS (outf, " + ");
   3195       OUTS (outf, dregs_hi (src1));
   3196       amod1 (s, x, outf);
   3197     }
   3198   else if (HL == 1 && aop == 2 && aopcde == 2)
   3199     {
   3200       OUTS (outf, dregs_hi (dst0));
   3201       OUTS (outf, " = ");
   3202       OUTS (outf, dregs_hi (src0));
   3203       OUTS (outf, " + ");
   3204       OUTS (outf, dregs_lo (src1));
   3205       amod1 (s, x, outf);
   3206     }
   3207   else if (HL == 1 && aop == 3 && aopcde == 2)
   3208     {
   3209       OUTS (outf, dregs_hi (dst0));
   3210       OUTS (outf, " = ");
   3211       OUTS (outf, dregs_hi (src0));
   3212       OUTS (outf, " + ");
   3213       OUTS (outf, dregs_hi (src1));
   3214       amod1 (s, x, outf);
   3215     }
   3216   else if (HL == 0 && aop == 0 && aopcde == 3)
   3217     {
   3218       OUTS (outf, dregs_lo (dst0));
   3219       OUTS (outf, " = ");
   3220       OUTS (outf, dregs_lo (src0));
   3221       OUTS (outf, " - ");
   3222       OUTS (outf, dregs_lo (src1));
   3223       amod1 (s, x, outf);
   3224     }
   3225   else if (HL == 0 && aop == 1 && aopcde == 3)
   3226     {
   3227       OUTS (outf, dregs_lo (dst0));
   3228       OUTS (outf, " = ");
   3229       OUTS (outf, dregs_lo (src0));
   3230       OUTS (outf, " - ");
   3231       OUTS (outf, dregs_hi (src1));
   3232       amod1 (s, x, outf);
   3233     }
   3234   else if (HL == 0 && aop == 3 && aopcde == 2)
   3235     {
   3236       OUTS (outf, dregs_lo (dst0));
   3237       OUTS (outf, " = ");
   3238       OUTS (outf, dregs_hi (src0));
   3239       OUTS (outf, " + ");
   3240       OUTS (outf, dregs_hi (src1));
   3241       amod1 (s, x, outf);
   3242     }
   3243   else if (HL == 1 && aop == 0 && aopcde == 3)
   3244     {
   3245       OUTS (outf, dregs_hi (dst0));
   3246       OUTS (outf, " = ");
   3247       OUTS (outf, dregs_lo (src0));
   3248       OUTS (outf, " - ");
   3249       OUTS (outf, dregs_lo (src1));
   3250       amod1 (s, x, outf);
   3251     }
   3252   else if (HL == 1 && aop == 1 && aopcde == 3)
   3253     {
   3254       OUTS (outf, dregs_hi (dst0));
   3255       OUTS (outf, " = ");
   3256       OUTS (outf, dregs_lo (src0));
   3257       OUTS (outf, " - ");
   3258       OUTS (outf, dregs_hi (src1));
   3259       amod1 (s, x, outf);
   3260     }
   3261   else if (HL == 1 && aop == 2 && aopcde == 3)
   3262     {
   3263       OUTS (outf, dregs_hi (dst0));
   3264       OUTS (outf, " = ");
   3265       OUTS (outf, dregs_hi (src0));
   3266       OUTS (outf, " - ");
   3267       OUTS (outf, dregs_lo (src1));
   3268       amod1 (s, x, outf);
   3269     }
   3270   else if (HL == 1 && aop == 3 && aopcde == 3)
   3271     {
   3272       OUTS (outf, dregs_hi (dst0));
   3273       OUTS (outf, " = ");
   3274       OUTS (outf, dregs_hi (src0));
   3275       OUTS (outf, " - ");
   3276       OUTS (outf, dregs_hi (src1));
   3277       amod1 (s, x, outf);
   3278     }
   3279   else if (HL == 0 && aop == 2 && aopcde == 2)
   3280     {
   3281       OUTS (outf, dregs_lo (dst0));
   3282       OUTS (outf, " = ");
   3283       OUTS (outf, dregs_hi (src0));
   3284       OUTS (outf, " + ");
   3285       OUTS (outf, dregs_lo (src1));
   3286       amod1 (s, x, outf);
   3287     }
   3288   else if (HL == 0 && aop == 1 && aopcde == 2)
   3289     {
   3290       OUTS (outf, dregs_lo (dst0));
   3291       OUTS (outf, " = ");
   3292       OUTS (outf, dregs_lo (src0));
   3293       OUTS (outf, " + ");
   3294       OUTS (outf, dregs_hi (src1));
   3295       amod1 (s, x, outf);
   3296     }
   3297   else if (HL == 0 && aop == 2 && aopcde == 3)
   3298     {
   3299       OUTS (outf, dregs_lo (dst0));
   3300       OUTS (outf, " = ");
   3301       OUTS (outf, dregs_hi (src0));
   3302       OUTS (outf, " - ");
   3303       OUTS (outf, dregs_lo (src1));
   3304       amod1 (s, x, outf);
   3305     }
   3306   else if (HL == 0 && aop == 3 && aopcde == 3)
   3307     {
   3308       OUTS (outf, dregs_lo (dst0));
   3309       OUTS (outf, " = ");
   3310       OUTS (outf, dregs_hi (src0));
   3311       OUTS (outf, " - ");
   3312       OUTS (outf, dregs_hi (src1));
   3313       amod1 (s, x, outf);
   3314     }
   3315   else if (HL == 0 && aop == 0 && aopcde == 2)
   3316     {
   3317       OUTS (outf, dregs_lo (dst0));
   3318       OUTS (outf, " = ");
   3319       OUTS (outf, dregs_lo (src0));
   3320       OUTS (outf, " + ");
   3321       OUTS (outf, dregs_lo (src1));
   3322       amod1 (s, x, outf);
   3323     }
   3324   else if (aop == 0 && aopcde == 9 && s == 1)
   3325     {
   3326       OUTS (outf, "A0 = ");
   3327       OUTS (outf, dregs (src0));
   3328     }
   3329   else if (aop == 3 && aopcde == 11 && s == 0)
   3330     OUTS (outf, "A0 -= A1");
   3331 
   3332   else if (aop == 3 && aopcde == 11 && s == 1)
   3333     OUTS (outf, "A0 -= A1 (W32)");
   3334 
   3335   else if (aop == 1 && aopcde == 22 && HL == 1)
   3336     {
   3337       OUTS (outf, dregs (dst0));
   3338       OUTS (outf, " = BYTEOP2P (");
   3339       OUTS (outf, dregs (src0 + 1));
   3340       OUTS (outf, ":");
   3341       OUTS (outf, imm5d (src0));
   3342       OUTS (outf, ", ");
   3343       OUTS (outf, dregs (src1 + 1));
   3344       OUTS (outf, ":");
   3345       OUTS (outf, imm5d (src1));
   3346       OUTS (outf, ") (TH");
   3347       if (s == 1)
   3348 	OUTS (outf, ", R)");
   3349       else
   3350 	OUTS (outf, ")");
   3351     }
   3352   else if (aop == 1 && aopcde == 22 && HL == 0)
   3353     {
   3354       OUTS (outf, dregs (dst0));
   3355       OUTS (outf, " = BYTEOP2P (");
   3356       OUTS (outf, dregs (src0 + 1));
   3357       OUTS (outf, ":");
   3358       OUTS (outf, imm5d (src0));
   3359       OUTS (outf, ", ");
   3360       OUTS (outf, dregs (src1 + 1));
   3361       OUTS (outf, ":");
   3362       OUTS (outf, imm5d (src1));
   3363       OUTS (outf, ") (TL");
   3364       if (s == 1)
   3365 	OUTS (outf, ", R)");
   3366       else
   3367 	OUTS (outf, ")");
   3368     }
   3369   else if (aop == 0 && aopcde == 22 && HL == 1)
   3370     {
   3371       OUTS (outf, dregs (dst0));
   3372       OUTS (outf, " = BYTEOP2P (");
   3373       OUTS (outf, dregs (src0 + 1));
   3374       OUTS (outf, ":");
   3375       OUTS (outf, imm5d (src0));
   3376       OUTS (outf, ", ");
   3377       OUTS (outf, dregs (src1 + 1));
   3378       OUTS (outf, ":");
   3379       OUTS (outf, imm5d (src1));
   3380       OUTS (outf, ") (RNDH");
   3381       if (s == 1)
   3382 	OUTS (outf, ", R)");
   3383       else
   3384 	OUTS (outf, ")");
   3385     }
   3386   else if (aop == 0 && aopcde == 22 && HL == 0)
   3387     {
   3388       OUTS (outf, dregs (dst0));
   3389       OUTS (outf, " = BYTEOP2P (");
   3390       OUTS (outf, dregs (src0 + 1));
   3391       OUTS (outf, ":");
   3392       OUTS (outf, imm5d (src0));
   3393       OUTS (outf, ", ");
   3394       OUTS (outf, dregs (src1 + 1));
   3395       OUTS (outf, ":");
   3396       OUTS (outf, imm5d (src1));
   3397       OUTS (outf, ") (RNDL");
   3398       if (s == 1)
   3399 	OUTS (outf, ", R)");
   3400       else
   3401 	OUTS (outf, ")");
   3402     }
   3403   else if (aop == 0 && s == 0 && aopcde == 8)
   3404     OUTS (outf, "A0 = 0");
   3405 
   3406   else if (aop == 0 && s == 1 && aopcde == 8)
   3407     OUTS (outf, "A0 = A0 (S)");
   3408 
   3409   else if (aop == 1 && s == 0 && aopcde == 8)
   3410     OUTS (outf, "A1 = 0");
   3411 
   3412   else if (aop == 1 && s == 1 && aopcde == 8)
   3413     OUTS (outf, "A1 = A1 (S)");
   3414 
   3415   else if (aop == 2 && s == 0 && aopcde == 8)
   3416     OUTS (outf, "A1 = A0 = 0");
   3417 
   3418   else if (aop == 2 && s == 1 && aopcde == 8)
   3419     OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
   3420 
   3421   else if (aop == 3 && s == 0 && aopcde == 8)
   3422     OUTS (outf, "A0 = A1");
   3423 
   3424   else if (aop == 3 && s == 1 && aopcde == 8)
   3425     OUTS (outf, "A1 = A0");
   3426 
   3427   else if (aop == 1 && aopcde == 9 && s == 0)
   3428     {
   3429       OUTS (outf, "A0.X = ");
   3430       OUTS (outf, dregs_lo (src0));
   3431     }
   3432   else if (aop == 1 && HL == 0 && aopcde == 11)
   3433     {
   3434       OUTS (outf, dregs_lo (dst0));
   3435       OUTS (outf, " = (A0 += A1)");
   3436     }
   3437   else if (aop == 3 && HL == 0 && aopcde == 16)
   3438     OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
   3439 
   3440   else if (aop == 0 && aopcde == 23 && HL == 1)
   3441     {
   3442       OUTS (outf, dregs (dst0));
   3443       OUTS (outf, " = BYTEOP3P (");
   3444       OUTS (outf, dregs (src0 + 1));
   3445       OUTS (outf, ":");
   3446       OUTS (outf, imm5d (src0));
   3447       OUTS (outf, ", ");
   3448       OUTS (outf, dregs (src1 + 1));
   3449       OUTS (outf, ":");
   3450       OUTS (outf, imm5d (src1));
   3451       OUTS (outf, ") (HI");
   3452       if (s == 1)
   3453 	OUTS (outf, ", R)");
   3454       else
   3455 	OUTS (outf, ")");
   3456     }
   3457   else if (aop == 3 && aopcde == 9 && s == 0)
   3458     {
   3459       OUTS (outf, "A1.X = ");
   3460       OUTS (outf, dregs_lo (src0));
   3461     }
   3462   else if (aop == 1 && HL == 1 && aopcde == 16)
   3463     OUTS (outf, "A1 = ABS A1");
   3464 
   3465   else if (aop == 0 && HL == 1 && aopcde == 16)
   3466     OUTS (outf, "A1 = ABS A0");
   3467 
   3468   else if (aop == 2 && aopcde == 9 && s == 1)
   3469     {
   3470       OUTS (outf, "A1 = ");
   3471       OUTS (outf, dregs (src0));
   3472     }
   3473   else if (HL == 0 && aop == 3 && aopcde == 12)
   3474     {
   3475       OUTS (outf, dregs_lo (dst0));
   3476       OUTS (outf, " = ");
   3477       OUTS (outf, dregs (src0));
   3478       OUTS (outf, " (RND)");
   3479     }
   3480   else if (aop == 1 && HL == 0 && aopcde == 16)
   3481     OUTS (outf, "A0 = ABS A1");
   3482 
   3483   else if (aop == 0 && HL == 0 && aopcde == 16)
   3484     OUTS (outf, "A0 = ABS A0");
   3485 
   3486   else if (aop == 3 && HL == 0 && aopcde == 15)
   3487     {
   3488       OUTS (outf, dregs (dst0));
   3489       OUTS (outf, " = -");
   3490       OUTS (outf, dregs (src0));
   3491       OUTS (outf, " (V)");
   3492     }
   3493   else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
   3494     {
   3495       OUTS (outf, dregs (dst0));
   3496       OUTS (outf, " = -");
   3497       OUTS (outf, dregs (src0));
   3498       OUTS (outf, " (S)");
   3499     }
   3500   else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
   3501     {
   3502       OUTS (outf, dregs (dst0));
   3503       OUTS (outf, " = -");
   3504       OUTS (outf, dregs (src0));
   3505       OUTS (outf, " (NS)");
   3506     }
   3507   else if (aop == 1 && HL == 1 && aopcde == 11)
   3508     {
   3509       OUTS (outf, dregs_hi (dst0));
   3510       OUTS (outf, " = (A0 += A1)");
   3511     }
   3512   else if (aop == 2 && aopcde == 11 && s == 0)
   3513     OUTS (outf, "A0 += A1");
   3514 
   3515   else if (aop == 2 && aopcde == 11 && s == 1)
   3516     OUTS (outf, "A0 += A1 (W32)");
   3517 
   3518   else if (aop == 3 && HL == 0 && aopcde == 14)
   3519     OUTS (outf, "A1 = -A1, A0 = -A0");
   3520 
   3521   else if (HL == 1 && aop == 3 && aopcde == 12)
   3522     {
   3523       OUTS (outf, dregs_hi (dst0));
   3524       OUTS (outf, " = ");
   3525       OUTS (outf, dregs (src0));
   3526       OUTS (outf, " (RND)");
   3527     }
   3528   else if (aop == 0 && aopcde == 23 && HL == 0)
   3529     {
   3530       OUTS (outf, dregs (dst0));
   3531       OUTS (outf, " = BYTEOP3P (");
   3532       OUTS (outf, dregs (src0 + 1));
   3533       OUTS (outf, ":");
   3534       OUTS (outf, imm5d (src0));
   3535       OUTS (outf, ", ");
   3536       OUTS (outf, dregs (src1 + 1));
   3537       OUTS (outf, ":");
   3538       OUTS (outf, imm5d (src1));
   3539       OUTS (outf, ") (LO");
   3540       if (s == 1)
   3541 	OUTS (outf, ", R)");
   3542       else
   3543 	OUTS (outf, ")");
   3544     }
   3545   else if (aop == 0 && HL == 0 && aopcde == 14)
   3546     OUTS (outf, "A0 = -A0");
   3547 
   3548   else if (aop == 1 && HL == 0 && aopcde == 14)
   3549     OUTS (outf, "A0 = -A1");
   3550 
   3551   else if (aop == 0 && HL == 1 && aopcde == 14)
   3552     OUTS (outf, "A1 = -A0");
   3553 
   3554   else if (aop == 1 && HL == 1 && aopcde == 14)
   3555     OUTS (outf, "A1 = -A1");
   3556 
   3557   else if (aop == 0 && aopcde == 12)
   3558     {
   3559       OUTS (outf, dregs_hi (dst0));
   3560       OUTS (outf, " = ");
   3561       OUTS (outf, dregs_lo (dst0));
   3562       OUTS (outf, " = SIGN (");
   3563       OUTS (outf, dregs_hi (src0));
   3564       OUTS (outf, ") * ");
   3565       OUTS (outf, dregs_hi (src1));
   3566       OUTS (outf, " + SIGN (");
   3567       OUTS (outf, dregs_lo (src0));
   3568       OUTS (outf, ") * ");
   3569       OUTS (outf, dregs_lo (src1));
   3570     }
   3571   else if (aop == 2 && aopcde == 0)
   3572     {
   3573       OUTS (outf, dregs (dst0));
   3574       OUTS (outf, " = ");
   3575       OUTS (outf, dregs (src0));
   3576       OUTS (outf, " -|+ ");
   3577       OUTS (outf, dregs (src1));
   3578       amod0 (s, x, outf);
   3579     }
   3580   else if (aop == 1 && aopcde == 12)
   3581     {
   3582       OUTS (outf, dregs (dst1));
   3583       OUTS (outf, " = A1.L + A1.H, ");
   3584       OUTS (outf, dregs (dst0));
   3585       OUTS (outf, " = A0.L + A0.H");
   3586     }
   3587   else if (aop == 2 && aopcde == 4)
   3588     {
   3589       OUTS (outf, dregs (dst1));
   3590       OUTS (outf, " = ");
   3591       OUTS (outf, dregs (src0));
   3592       OUTS (outf, " + ");
   3593       OUTS (outf, dregs (src1));
   3594       OUTS (outf, ", ");
   3595       OUTS (outf, dregs (dst0));
   3596       OUTS (outf, " = ");
   3597       OUTS (outf, dregs (src0));
   3598       OUTS (outf, " - ");
   3599       OUTS (outf, dregs (src1));
   3600       amod1 (s, x, outf);
   3601     }
   3602   else if (HL == 0 && aopcde == 1)
   3603     {
   3604       OUTS (outf, dregs (dst1));
   3605       OUTS (outf, " = ");
   3606       OUTS (outf, dregs (src0));
   3607       OUTS (outf, " +|+ ");
   3608       OUTS (outf, dregs (src1));
   3609       OUTS (outf, ", ");
   3610       OUTS (outf, dregs (dst0));
   3611       OUTS (outf, " = ");
   3612       OUTS (outf, dregs (src0));
   3613       OUTS (outf, " -|- ");
   3614       OUTS (outf, dregs (src1));
   3615       amod0amod2 (s, x, aop, outf);
   3616     }
   3617   else if (aop == 0 && aopcde == 11)
   3618     {
   3619       OUTS (outf, dregs (dst0));
   3620       OUTS (outf, " = (A0 += A1)");
   3621     }
   3622   else if (aop == 0 && aopcde == 10)
   3623     {
   3624       OUTS (outf, dregs_lo (dst0));
   3625       OUTS (outf, " = A0.X");
   3626     }
   3627   else if (aop == 1 && aopcde == 10)
   3628     {
   3629       OUTS (outf, dregs_lo (dst0));
   3630       OUTS (outf, " = A1.X");
   3631     }
   3632   else if (aop == 1 && aopcde == 0)
   3633     {
   3634       OUTS (outf, dregs (dst0));
   3635       OUTS (outf, " = ");
   3636       OUTS (outf, dregs (src0));
   3637       OUTS (outf, " +|- ");
   3638       OUTS (outf, dregs (src1));
   3639       amod0 (s, x, outf);
   3640     }
   3641   else if (aop == 3 && aopcde == 0)
   3642     {
   3643       OUTS (outf, dregs (dst0));
   3644       OUTS (outf, " = ");
   3645       OUTS (outf, dregs (src0));
   3646       OUTS (outf, " -|- ");
   3647       OUTS (outf, dregs (src1));
   3648       amod0 (s, x, outf);
   3649     }
   3650   else if (aop == 1 && aopcde == 4)
   3651     {
   3652       OUTS (outf, dregs (dst0));
   3653       OUTS (outf, " = ");
   3654       OUTS (outf, dregs (src0));
   3655       OUTS (outf, " - ");
   3656       OUTS (outf, dregs (src1));
   3657       amod1 (s, x, outf);
   3658     }
   3659   else if (aop == 0 && aopcde == 17)
   3660     {
   3661       OUTS (outf, dregs (dst1));
   3662       OUTS (outf, " = A1 + A0, ");
   3663       OUTS (outf, dregs (dst0));
   3664       OUTS (outf, " = A1 - A0");
   3665       amod1 (s, x, outf);
   3666     }
   3667   else if (aop == 1 && aopcde == 17)
   3668     {
   3669       OUTS (outf, dregs (dst1));
   3670       OUTS (outf, " = A0 + A1, ");
   3671       OUTS (outf, dregs (dst0));
   3672       OUTS (outf, " = A0 - A1");
   3673       amod1 (s, x, outf);
   3674     }
   3675   else if (aop == 0 && aopcde == 18)
   3676     {
   3677       OUTS (outf, "SAA (");
   3678       OUTS (outf, dregs (src0 + 1));
   3679       OUTS (outf, ":");
   3680       OUTS (outf, imm5d (src0));
   3681       OUTS (outf, ", ");
   3682       OUTS (outf, dregs (src1 + 1));
   3683       OUTS (outf, ":");
   3684       OUTS (outf, imm5d (src1));
   3685       OUTS (outf, ")");
   3686       aligndir (s, outf);
   3687     }
   3688   else if (aop == 3 && aopcde == 18)
   3689     OUTS (outf, "DISALGNEXCPT");
   3690 
   3691   else if (aop == 0 && aopcde == 20)
   3692     {
   3693       OUTS (outf, dregs (dst0));
   3694       OUTS (outf, " = BYTEOP1P (");
   3695       OUTS (outf, dregs (src0 + 1));
   3696       OUTS (outf, ":");
   3697       OUTS (outf, imm5d (src0));
   3698       OUTS (outf, ", ");
   3699       OUTS (outf, dregs (src1 + 1));
   3700       OUTS (outf, ":");
   3701       OUTS (outf, imm5d (src1));
   3702       OUTS (outf, ")");
   3703       aligndir (s, outf);
   3704     }
   3705   else if (aop == 1 && aopcde == 20)
   3706     {
   3707       OUTS (outf, dregs (dst0));
   3708       OUTS (outf, " = BYTEOP1P (");
   3709       OUTS (outf, dregs (src0 + 1));
   3710       OUTS (outf, ":");
   3711       OUTS (outf, imm5d (src0));
   3712       OUTS (outf, ", ");
   3713       OUTS (outf, dregs (src1 + 1));
   3714       OUTS (outf, ":");
   3715       OUTS (outf, imm5d (src1));
   3716       OUTS (outf, ") (T");
   3717       if (s == 1)
   3718 	OUTS (outf, ", R)");
   3719       else
   3720 	OUTS (outf, ")");
   3721     }
   3722   else if (aop == 0 && aopcde == 21)
   3723     {
   3724       OUTS (outf, "(");
   3725       OUTS (outf, dregs (dst1));
   3726       OUTS (outf, ", ");
   3727       OUTS (outf, dregs (dst0));
   3728       OUTS (outf, ") = BYTEOP16P (");
   3729       OUTS (outf, dregs (src0 + 1));
   3730       OUTS (outf, ":");
   3731       OUTS (outf, imm5d (src0));
   3732       OUTS (outf, ", ");
   3733       OUTS (outf, dregs (src1 + 1));
   3734       OUTS (outf, ":");
   3735       OUTS (outf, imm5d (src1));
   3736       OUTS (outf, ")");
   3737       aligndir (s, outf);
   3738     }
   3739   else if (aop == 1 && aopcde == 21)
   3740     {
   3741       OUTS (outf, "(");
   3742       OUTS (outf, dregs (dst1));
   3743       OUTS (outf, ", ");
   3744       OUTS (outf, dregs (dst0));
   3745       OUTS (outf, ") = BYTEOP16M (");
   3746       OUTS (outf, dregs (src0 + 1));
   3747       OUTS (outf, ":");
   3748       OUTS (outf, imm5d (src0));
   3749       OUTS (outf, ", ");
   3750       OUTS (outf, dregs (src1 + 1));
   3751       OUTS (outf, ":");
   3752       OUTS (outf, imm5d (src1));
   3753       OUTS (outf, ")");
   3754       aligndir (s, outf);
   3755     }
   3756   else if (aop == 2 && aopcde == 7)
   3757     {
   3758       OUTS (outf, dregs (dst0));
   3759       OUTS (outf, " = ABS ");
   3760       OUTS (outf, dregs (src0));
   3761     }
   3762   else if (aop == 1 && aopcde == 7)
   3763     {
   3764       OUTS (outf, dregs (dst0));
   3765       OUTS (outf, " = MIN (");
   3766       OUTS (outf, dregs (src0));
   3767       OUTS (outf, ", ");
   3768       OUTS (outf, dregs (src1));
   3769       OUTS (outf, ")");
   3770     }
   3771   else if (aop == 0 && aopcde == 7)
   3772     {
   3773       OUTS (outf, dregs (dst0));
   3774       OUTS (outf, " = MAX (");
   3775       OUTS (outf, dregs (src0));
   3776       OUTS (outf, ", ");
   3777       OUTS (outf, dregs (src1));
   3778       OUTS (outf, ")");
   3779     }
   3780   else if (aop == 2 && aopcde == 6)
   3781     {
   3782       OUTS (outf, dregs (dst0));
   3783       OUTS (outf, " = ABS ");
   3784       OUTS (outf, dregs (src0));
   3785       OUTS (outf, " (V)");
   3786     }
   3787   else if (aop == 1 && aopcde == 6)
   3788     {
   3789       OUTS (outf, dregs (dst0));
   3790       OUTS (outf, " = MIN (");
   3791       OUTS (outf, dregs (src0));
   3792       OUTS (outf, ", ");
   3793       OUTS (outf, dregs (src1));
   3794       OUTS (outf, ") (V)");
   3795     }
   3796   else if (aop == 0 && aopcde == 6)
   3797     {
   3798       OUTS (outf, dregs (dst0));
   3799       OUTS (outf, " = MAX (");
   3800       OUTS (outf, dregs (src0));
   3801       OUTS (outf, ", ");
   3802       OUTS (outf, dregs (src1));
   3803       OUTS (outf, ") (V)");
   3804     }
   3805   else if (HL == 1 && aopcde == 1)
   3806     {
   3807       OUTS (outf, dregs (dst1));
   3808       OUTS (outf, " = ");
   3809       OUTS (outf, dregs (src0));
   3810       OUTS (outf, " +|- ");
   3811       OUTS (outf, dregs (src1));
   3812       OUTS (outf, ", ");
   3813       OUTS (outf, dregs (dst0));
   3814       OUTS (outf, " = ");
   3815       OUTS (outf, dregs (src0));
   3816       OUTS (outf, " -|+ ");
   3817       OUTS (outf, dregs (src1));
   3818       amod0amod2 (s, x, aop, outf);
   3819     }
   3820   else if (aop == 0 && aopcde == 4)
   3821     {
   3822       OUTS (outf, dregs (dst0));
   3823       OUTS (outf, " = ");
   3824       OUTS (outf, dregs (src0));
   3825       OUTS (outf, " + ");
   3826       OUTS (outf, dregs (src1));
   3827       amod1 (s, x, outf);
   3828     }
   3829   else if (aop == 0 && aopcde == 0)
   3830     {
   3831       OUTS (outf, dregs (dst0));
   3832       OUTS (outf, " = ");
   3833       OUTS (outf, dregs (src0));
   3834       OUTS (outf, " +|+ ");
   3835       OUTS (outf, dregs (src1));
   3836       amod0 (s, x, outf);
   3837     }
   3838   else if (aop == 0 && aopcde == 24)
   3839     {
   3840       OUTS (outf, dregs (dst0));
   3841       OUTS (outf, " = BYTEPACK (");
   3842       OUTS (outf, dregs (src0));
   3843       OUTS (outf, ", ");
   3844       OUTS (outf, dregs (src1));
   3845       OUTS (outf, ")");
   3846     }
   3847   else if (aop == 1 && aopcde == 24)
   3848     {
   3849       OUTS (outf, "(");
   3850       OUTS (outf, dregs (dst1));
   3851       OUTS (outf, ", ");
   3852       OUTS (outf, dregs (dst0));
   3853       OUTS (outf, ") = BYTEUNPACK ");
   3854       OUTS (outf, dregs (src0 + 1));
   3855       OUTS (outf, ":");
   3856       OUTS (outf, imm5d (src0));
   3857       aligndir (s, outf);
   3858     }
   3859   else if (aopcde == 13)
   3860     {
   3861       OUTS (outf, "(");
   3862       OUTS (outf, dregs (dst1));
   3863       OUTS (outf, ", ");
   3864       OUTS (outf, dregs (dst0));
   3865       OUTS (outf, ") = SEARCH ");
   3866       OUTS (outf, dregs (src0));
   3867       OUTS (outf, " (");
   3868       searchmod (aop, outf);
   3869       OUTS (outf, ")");
   3870     }
   3871   else
   3872     return 0;
   3873 
   3874   return 4;
   3875 }
   3876 
   3877 static int
   3878 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
   3879 {
   3880   /* dsp32shift
   3881      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   3882      | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
   3883      |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
   3884      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   3885   int HLs  = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
   3886   int sop  = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
   3887   int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
   3888   int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
   3889   int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
   3890   int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
   3891   const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
   3892 
   3893   if (HLs == 0 && sop == 0 && sopcde == 0)
   3894     {
   3895       OUTS (outf, dregs_lo (dst0));
   3896       OUTS (outf, " = ASHIFT ");
   3897       OUTS (outf, dregs_lo (src1));
   3898       OUTS (outf, " BY ");
   3899       OUTS (outf, dregs_lo (src0));
   3900     }
   3901   else if (HLs == 1 && sop == 0 && sopcde == 0)
   3902     {
   3903       OUTS (outf, dregs_lo (dst0));
   3904       OUTS (outf, " = ASHIFT ");
   3905       OUTS (outf, dregs_hi (src1));
   3906       OUTS (outf, " BY ");
   3907       OUTS (outf, dregs_lo (src0));
   3908     }
   3909   else if (HLs == 2 && sop == 0 && sopcde == 0)
   3910     {
   3911       OUTS (outf, dregs_hi (dst0));
   3912       OUTS (outf, " = ASHIFT ");
   3913       OUTS (outf, dregs_lo (src1));
   3914       OUTS (outf, " BY ");
   3915       OUTS (outf, dregs_lo (src0));
   3916     }
   3917   else if (HLs == 3 && sop == 0 && sopcde == 0)
   3918     {
   3919       OUTS (outf, dregs_hi (dst0));
   3920       OUTS (outf, " = ASHIFT ");
   3921       OUTS (outf, dregs_hi (src1));
   3922       OUTS (outf, " BY ");
   3923       OUTS (outf, dregs_lo (src0));
   3924     }
   3925   else if (HLs == 0 && sop == 1 && sopcde == 0)
   3926     {
   3927       OUTS (outf, dregs_lo (dst0));
   3928       OUTS (outf, " = ASHIFT ");
   3929       OUTS (outf, dregs_lo (src1));
   3930       OUTS (outf, " BY ");
   3931       OUTS (outf, dregs_lo (src0));
   3932       OUTS (outf, " (S)");
   3933     }
   3934   else if (HLs == 1 && sop == 1 && sopcde == 0)
   3935     {
   3936       OUTS (outf, dregs_lo (dst0));
   3937       OUTS (outf, " = ASHIFT ");
   3938       OUTS (outf, dregs_hi (src1));
   3939       OUTS (outf, " BY ");
   3940       OUTS (outf, dregs_lo (src0));
   3941       OUTS (outf, " (S)");
   3942     }
   3943   else if (HLs == 2 && sop == 1 && sopcde == 0)
   3944     {
   3945       OUTS (outf, dregs_hi (dst0));
   3946       OUTS (outf, " = ASHIFT ");
   3947       OUTS (outf, dregs_lo (src1));
   3948       OUTS (outf, " BY ");
   3949       OUTS (outf, dregs_lo (src0));
   3950       OUTS (outf, " (S)");
   3951     }
   3952   else if (HLs == 3 && sop == 1 && sopcde == 0)
   3953     {
   3954       OUTS (outf, dregs_hi (dst0));
   3955       OUTS (outf, " = ASHIFT ");
   3956       OUTS (outf, dregs_hi (src1));
   3957       OUTS (outf, " BY ");
   3958       OUTS (outf, dregs_lo (src0));
   3959       OUTS (outf, " (S)");
   3960     }
   3961   else if (sop == 2 && sopcde == 0)
   3962     {
   3963       OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
   3964       OUTS (outf, " = LSHIFT ");
   3965       OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
   3966       OUTS (outf, " BY ");
   3967       OUTS (outf, dregs_lo (src0));
   3968     }
   3969   else if (sop == 0 && sopcde == 3)
   3970     {
   3971       OUTS (outf, acc01);
   3972       OUTS (outf, " = ASHIFT ");
   3973       OUTS (outf, acc01);
   3974       OUTS (outf, " BY ");
   3975       OUTS (outf, dregs_lo (src0));
   3976     }
   3977   else if (sop == 1 && sopcde == 3)
   3978     {
   3979       OUTS (outf, acc01);
   3980       OUTS (outf, " = LSHIFT ");
   3981       OUTS (outf, acc01);
   3982       OUTS (outf, " BY ");
   3983       OUTS (outf, dregs_lo (src0));
   3984     }
   3985   else if (sop == 2 && sopcde == 3)
   3986     {
   3987       OUTS (outf, acc01);
   3988       OUTS (outf, " = ROT ");
   3989       OUTS (outf, acc01);
   3990       OUTS (outf, " BY ");
   3991       OUTS (outf, dregs_lo (src0));
   3992     }
   3993   else if (sop == 3 && sopcde == 3)
   3994     {
   3995       OUTS (outf, dregs (dst0));
   3996       OUTS (outf, " = ROT ");
   3997       OUTS (outf, dregs (src1));
   3998       OUTS (outf, " BY ");
   3999       OUTS (outf, dregs_lo (src0));
   4000     }
   4001   else if (sop == 1 && sopcde == 1)
   4002     {
   4003       OUTS (outf, dregs (dst0));
   4004       OUTS (outf, " = ASHIFT ");
   4005       OUTS (outf, dregs (src1));
   4006       OUTS (outf, " BY ");
   4007       OUTS (outf, dregs_lo (src0));
   4008       OUTS (outf, " (V, S)");
   4009     }
   4010   else if (sop == 0 && sopcde == 1)
   4011     {
   4012       OUTS (outf, dregs (dst0));
   4013       OUTS (outf, " = ASHIFT ");
   4014       OUTS (outf, dregs (src1));
   4015       OUTS (outf, " BY ");
   4016       OUTS (outf, dregs_lo (src0));
   4017       OUTS (outf, " (V)");
   4018     }
   4019   else if (sop == 0 && sopcde == 2)
   4020     {
   4021       OUTS (outf, dregs (dst0));
   4022       OUTS (outf, " = ASHIFT ");
   4023       OUTS (outf, dregs (src1));
   4024       OUTS (outf, " BY ");
   4025       OUTS (outf, dregs_lo (src0));
   4026     }
   4027   else if (sop == 1 && sopcde == 2)
   4028     {
   4029       OUTS (outf, dregs (dst0));
   4030       OUTS (outf, " = ASHIFT ");
   4031       OUTS (outf, dregs (src1));
   4032       OUTS (outf, " BY ");
   4033       OUTS (outf, dregs_lo (src0));
   4034       OUTS (outf, " (S)");
   4035     }
   4036   else if (sop == 2 && sopcde == 2)
   4037     {
   4038       OUTS (outf, dregs (dst0));
   4039       OUTS (outf, " = LSHIFT ");
   4040       OUTS (outf, dregs (src1));
   4041       OUTS (outf, " BY ");
   4042       OUTS (outf, dregs_lo (src0));
   4043     }
   4044   else if (sop == 3 && sopcde == 2)
   4045     {
   4046       OUTS (outf, dregs (dst0));
   4047       OUTS (outf, " = ROT ");
   4048       OUTS (outf, dregs (src1));
   4049       OUTS (outf, " BY ");
   4050       OUTS (outf, dregs_lo (src0));
   4051     }
   4052   else if (sop == 2 && sopcde == 1)
   4053     {
   4054       OUTS (outf, dregs (dst0));
   4055       OUTS (outf, " = LSHIFT ");
   4056       OUTS (outf, dregs (src1));
   4057       OUTS (outf, " BY ");
   4058       OUTS (outf, dregs_lo (src0));
   4059       OUTS (outf, " (V)");
   4060     }
   4061   else if (sop == 0 && sopcde == 4)
   4062     {
   4063       OUTS (outf, dregs (dst0));
   4064       OUTS (outf, " = PACK (");
   4065       OUTS (outf, dregs_lo (src1));
   4066       OUTS (outf, ", ");
   4067       OUTS (outf, dregs_lo (src0));
   4068       OUTS (outf, ")");
   4069     }
   4070   else if (sop == 1 && sopcde == 4)
   4071     {
   4072       OUTS (outf, dregs (dst0));
   4073       OUTS (outf, " = PACK (");
   4074       OUTS (outf, dregs_lo (src1));
   4075       OUTS (outf, ", ");
   4076       OUTS (outf, dregs_hi (src0));
   4077       OUTS (outf, ")");
   4078     }
   4079   else if (sop == 2 && sopcde == 4)
   4080     {
   4081       OUTS (outf, dregs (dst0));
   4082       OUTS (outf, " = PACK (");
   4083       OUTS (outf, dregs_hi (src1));
   4084       OUTS (outf, ", ");
   4085       OUTS (outf, dregs_lo (src0));
   4086       OUTS (outf, ")");
   4087     }
   4088   else if (sop == 3 && sopcde == 4)
   4089     {
   4090       OUTS (outf, dregs (dst0));
   4091       OUTS (outf, " = PACK (");
   4092       OUTS (outf, dregs_hi (src1));
   4093       OUTS (outf, ", ");
   4094       OUTS (outf, dregs_hi (src0));
   4095       OUTS (outf, ")");
   4096     }
   4097   else if (sop == 0 && sopcde == 5)
   4098     {
   4099       OUTS (outf, dregs_lo (dst0));
   4100       OUTS (outf, " = SIGNBITS ");
   4101       OUTS (outf, dregs (src1));
   4102     }
   4103   else if (sop == 1 && sopcde == 5)
   4104     {
   4105       OUTS (outf, dregs_lo (dst0));
   4106       OUTS (outf, " = SIGNBITS ");
   4107       OUTS (outf, dregs_lo (src1));
   4108     }
   4109   else if (sop == 2 && sopcde == 5)
   4110     {
   4111       OUTS (outf, dregs_lo (dst0));
   4112       OUTS (outf, " = SIGNBITS ");
   4113       OUTS (outf, dregs_hi (src1));
   4114     }
   4115   else if (sop == 0 && sopcde == 6)
   4116     {
   4117       OUTS (outf, dregs_lo (dst0));
   4118       OUTS (outf, " = SIGNBITS A0");
   4119     }
   4120   else if (sop == 1 && sopcde == 6)
   4121     {
   4122       OUTS (outf, dregs_lo (dst0));
   4123       OUTS (outf, " = SIGNBITS A1");
   4124     }
   4125   else if (sop == 3 && sopcde == 6)
   4126     {
   4127       OUTS (outf, dregs_lo (dst0));
   4128       OUTS (outf, " = ONES ");
   4129       OUTS (outf, dregs (src1));
   4130     }
   4131   else if (sop == 0 && sopcde == 7)
   4132     {
   4133       OUTS (outf, dregs_lo (dst0));
   4134       OUTS (outf, " = EXPADJ (");
   4135       OUTS (outf, dregs (src1));
   4136       OUTS (outf, ", ");
   4137       OUTS (outf, dregs_lo (src0));
   4138       OUTS (outf, ")");
   4139     }
   4140   else if (sop == 1 && sopcde == 7)
   4141     {
   4142       OUTS (outf, dregs_lo (dst0));
   4143       OUTS (outf, " = EXPADJ (");
   4144       OUTS (outf, dregs (src1));
   4145       OUTS (outf, ", ");
   4146       OUTS (outf, dregs_lo (src0));
   4147       OUTS (outf, ") (V)");
   4148     }
   4149   else if (sop == 2 && sopcde == 7)
   4150     {
   4151       OUTS (outf, dregs_lo (dst0));
   4152       OUTS (outf, " = EXPADJ (");
   4153       OUTS (outf, dregs_lo (src1));
   4154       OUTS (outf, ", ");
   4155       OUTS (outf, dregs_lo (src0));
   4156       OUTS (outf, ")");
   4157     }
   4158   else if (sop == 3 && sopcde == 7)
   4159     {
   4160       OUTS (outf, dregs_lo (dst0));
   4161       OUTS (outf, " = EXPADJ (");
   4162       OUTS (outf, dregs_hi (src1));
   4163       OUTS (outf, ", ");
   4164       OUTS (outf, dregs_lo (src0));
   4165       OUTS (outf, ")");
   4166     }
   4167   else if (sop == 0 && sopcde == 8)
   4168     {
   4169       OUTS (outf, "BITMUX (");
   4170       OUTS (outf, dregs (src0));
   4171       OUTS (outf, ", ");
   4172       OUTS (outf, dregs (src1));
   4173       OUTS (outf, ", A0) (ASR)");
   4174     }
   4175   else if (sop == 1 && sopcde == 8)
   4176     {
   4177       OUTS (outf, "BITMUX (");
   4178       OUTS (outf, dregs (src0));
   4179       OUTS (outf, ", ");
   4180       OUTS (outf, dregs (src1));
   4181       OUTS (outf, ", A0) (ASL)");
   4182     }
   4183   else if (sop == 0 && sopcde == 9)
   4184     {
   4185       OUTS (outf, dregs_lo (dst0));
   4186       OUTS (outf, " = VIT_MAX (");
   4187       OUTS (outf, dregs (src1));
   4188       OUTS (outf, ") (ASL)");
   4189     }
   4190   else if (sop == 1 && sopcde == 9)
   4191     {
   4192       OUTS (outf, dregs_lo (dst0));
   4193       OUTS (outf, " = VIT_MAX (");
   4194       OUTS (outf, dregs (src1));
   4195       OUTS (outf, ") (ASR)");
   4196     }
   4197   else if (sop == 2 && sopcde == 9)
   4198     {
   4199       OUTS (outf, dregs (dst0));
   4200       OUTS (outf, " = VIT_MAX (");
   4201       OUTS (outf, dregs (src1));
   4202       OUTS (outf, ", ");
   4203       OUTS (outf, dregs (src0));
   4204       OUTS (outf, ") (ASL)");
   4205     }
   4206   else if (sop == 3 && sopcde == 9)
   4207     {
   4208       OUTS (outf, dregs (dst0));
   4209       OUTS (outf, " = VIT_MAX (");
   4210       OUTS (outf, dregs (src1));
   4211       OUTS (outf, ", ");
   4212       OUTS (outf, dregs (src0));
   4213       OUTS (outf, ") (ASR)");
   4214     }
   4215   else if (sop == 0 && sopcde == 10)
   4216     {
   4217       OUTS (outf, dregs (dst0));
   4218       OUTS (outf, " = EXTRACT (");
   4219       OUTS (outf, dregs (src1));
   4220       OUTS (outf, ", ");
   4221       OUTS (outf, dregs_lo (src0));
   4222       OUTS (outf, ") (Z)");
   4223     }
   4224   else if (sop == 1 && sopcde == 10)
   4225     {
   4226       OUTS (outf, dregs (dst0));
   4227       OUTS (outf, " = EXTRACT (");
   4228       OUTS (outf, dregs (src1));
   4229       OUTS (outf, ", ");
   4230       OUTS (outf, dregs_lo (src0));
   4231       OUTS (outf, ") (X)");
   4232     }
   4233   else if (sop == 2 && sopcde == 10)
   4234     {
   4235       OUTS (outf, dregs (dst0));
   4236       OUTS (outf, " = DEPOSIT (");
   4237       OUTS (outf, dregs (src1));
   4238       OUTS (outf, ", ");
   4239       OUTS (outf, dregs (src0));
   4240       OUTS (outf, ")");
   4241     }
   4242   else if (sop == 3 && sopcde == 10)
   4243     {
   4244       OUTS (outf, dregs (dst0));
   4245       OUTS (outf, " = DEPOSIT (");
   4246       OUTS (outf, dregs (src1));
   4247       OUTS (outf, ", ");
   4248       OUTS (outf, dregs (src0));
   4249       OUTS (outf, ") (X)");
   4250     }
   4251   else if (sop == 0 && sopcde == 11)
   4252     {
   4253       OUTS (outf, dregs_lo (dst0));
   4254       OUTS (outf, " = CC = BXORSHIFT (A0, ");
   4255       OUTS (outf, dregs (src0));
   4256       OUTS (outf, ")");
   4257     }
   4258   else if (sop == 1 && sopcde == 11)
   4259     {
   4260       OUTS (outf, dregs_lo (dst0));
   4261       OUTS (outf, " = CC = BXOR (A0, ");
   4262       OUTS (outf, dregs (src0));
   4263       OUTS (outf, ")");
   4264     }
   4265   else if (sop == 0 && sopcde == 12)
   4266     OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
   4267 
   4268   else if (sop == 1 && sopcde == 12)
   4269     {
   4270       OUTS (outf, dregs_lo (dst0));
   4271       OUTS (outf, " = CC = BXOR (A0, A1, CC)");
   4272     }
   4273   else if (sop == 0 && sopcde == 13)
   4274     {
   4275       OUTS (outf, dregs (dst0));
   4276       OUTS (outf, " = ALIGN8 (");
   4277       OUTS (outf, dregs (src1));
   4278       OUTS (outf, ", ");
   4279       OUTS (outf, dregs (src0));
   4280       OUTS (outf, ")");
   4281     }
   4282   else if (sop == 1 && sopcde == 13)
   4283     {
   4284       OUTS (outf, dregs (dst0));
   4285       OUTS (outf, " = ALIGN16 (");
   4286       OUTS (outf, dregs (src1));
   4287       OUTS (outf, ", ");
   4288       OUTS (outf, dregs (src0));
   4289       OUTS (outf, ")");
   4290     }
   4291   else if (sop == 2 && sopcde == 13)
   4292     {
   4293       OUTS (outf, dregs (dst0));
   4294       OUTS (outf, " = ALIGN24 (");
   4295       OUTS (outf, dregs (src1));
   4296       OUTS (outf, ", ");
   4297       OUTS (outf, dregs (src0));
   4298       OUTS (outf, ")");
   4299     }
   4300   else
   4301     return 0;
   4302 
   4303   return 4;
   4304 }
   4305 
   4306 static int
   4307 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
   4308 {
   4309   /* dsp32shiftimm
   4310      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   4311      | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
   4312      |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
   4313      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   4314   int src1     = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
   4315   int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
   4316   int bit8     = ((iw1 >> 8) & 0x1);
   4317   int immag    = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
   4318   int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
   4319   int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
   4320   int sopcde   = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
   4321   int HLs      = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
   4322 
   4323   if (sop == 0 && sopcde == 0)
   4324     {
   4325       OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
   4326       OUTS (outf, " = ");
   4327       OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
   4328       OUTS (outf, " >>> ");
   4329       OUTS (outf, uimm4 (newimmag));
   4330     }
   4331   else if (sop == 1 && sopcde == 0 && bit8 == 0)
   4332     {
   4333       OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
   4334       OUTS (outf, " = ");
   4335       OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
   4336       OUTS (outf, " << ");
   4337       OUTS (outf, uimm4 (immag));
   4338       OUTS (outf, " (S)");
   4339     }
   4340   else if (sop == 1 && sopcde == 0 && bit8 == 1)
   4341     {
   4342       OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
   4343       OUTS (outf, " = ");
   4344       OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
   4345       OUTS (outf, " >>> ");
   4346       OUTS (outf, uimm4 (newimmag));
   4347       OUTS (outf, " (S)");
   4348     }
   4349   else if (sop == 2 && sopcde == 0 && bit8 == 0)
   4350     {
   4351       OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
   4352       OUTS (outf, " = ");
   4353       OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
   4354       OUTS (outf, " << ");
   4355       OUTS (outf, uimm4 (immag));
   4356     }
   4357   else if (sop == 2 && sopcde == 0 && bit8 == 1)
   4358     {
   4359       OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
   4360       OUTS (outf, " = ");
   4361       OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
   4362       OUTS (outf, " >> ");
   4363       OUTS (outf, uimm4 (newimmag));
   4364     }
   4365   else if (sop == 2 && sopcde == 3 && HLs == 1)
   4366     {
   4367       OUTS (outf, "A1 = ROT A1 BY ");
   4368       OUTS (outf, imm6 (immag));
   4369     }
   4370   else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
   4371     {
   4372       OUTS (outf, "A0 = A0 << ");
   4373       OUTS (outf, uimm5 (immag));
   4374     }
   4375   else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
   4376     {
   4377       OUTS (outf, "A0 = A0 >>> ");
   4378       OUTS (outf, uimm5 (newimmag));
   4379     }
   4380   else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
   4381     {
   4382       OUTS (outf, "A1 = A1 << ");
   4383       OUTS (outf, uimm5 (immag));
   4384     }
   4385   else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
   4386     {
   4387       OUTS (outf, "A1 = A1 >>> ");
   4388       OUTS (outf, uimm5 (newimmag));
   4389     }
   4390   else if (sop == 1 && sopcde == 3 && HLs == 0)
   4391     {
   4392       OUTS (outf, "A0 = A0 >> ");
   4393       OUTS (outf, uimm5 (newimmag));
   4394     }
   4395   else if (sop == 1 && sopcde == 3 && HLs == 1)
   4396     {
   4397       OUTS (outf, "A1 = A1 >> ");
   4398       OUTS (outf, uimm5 (newimmag));
   4399     }
   4400   else if (sop == 2 && sopcde == 3 && HLs == 0)
   4401     {
   4402       OUTS (outf, "A0 = ROT A0 BY ");
   4403       OUTS (outf, imm6 (immag));
   4404     }
   4405   else if (sop == 1 && sopcde == 1 && bit8 == 0)
   4406     {
   4407       OUTS (outf, dregs (dst0));
   4408       OUTS (outf, " = ");
   4409       OUTS (outf, dregs (src1));
   4410       OUTS (outf, " << ");
   4411       OUTS (outf, uimm5 (immag));
   4412       OUTS (outf, " (V, S)");
   4413     }
   4414   else if (sop == 1 && sopcde == 1 && bit8 == 1)
   4415     {
   4416       OUTS (outf, dregs (dst0));
   4417       OUTS (outf, " = ");
   4418       OUTS (outf, dregs (src1));
   4419       OUTS (outf, " >>> ");
   4420       OUTS (outf, imm5 (-immag));
   4421       OUTS (outf, " (V, S)");
   4422     }
   4423   else if (sop == 2 && sopcde == 1 && bit8 == 1)
   4424     {
   4425       OUTS (outf, dregs (dst0));
   4426       OUTS (outf, " = ");
   4427       OUTS (outf, dregs (src1));
   4428       OUTS (outf, " >> ");
   4429       OUTS (outf, uimm5 (newimmag));
   4430       OUTS (outf, " (V)");
   4431     }
   4432   else if (sop == 2 && sopcde == 1 && bit8 == 0)
   4433     {
   4434       OUTS (outf, dregs (dst0));
   4435       OUTS (outf, " = ");
   4436       OUTS (outf, dregs (src1));
   4437       OUTS (outf, " << ");
   4438       OUTS (outf, imm5 (immag));
   4439       OUTS (outf, " (V)");
   4440     }
   4441   else if (sop == 0 && sopcde == 1)
   4442     {
   4443       OUTS (outf, dregs (dst0));
   4444       OUTS (outf, " = ");
   4445       OUTS (outf, dregs (src1));
   4446       OUTS (outf, " >>> ");
   4447       OUTS (outf, uimm5 (newimmag));
   4448       OUTS (outf, " (V)");
   4449     }
   4450   else if (sop == 1 && sopcde == 2)
   4451     {
   4452       OUTS (outf, dregs (dst0));
   4453       OUTS (outf, " = ");
   4454       OUTS (outf, dregs (src1));
   4455       OUTS (outf, " << ");
   4456       OUTS (outf, uimm5 (immag));
   4457       OUTS (outf, " (S)");
   4458     }
   4459   else if (sop == 2 && sopcde == 2 && bit8 == 1)
   4460     {
   4461       OUTS (outf, dregs (dst0));
   4462       OUTS (outf, " = ");
   4463       OUTS (outf, dregs (src1));
   4464       OUTS (outf, " >> ");
   4465       OUTS (outf, uimm5 (newimmag));
   4466     }
   4467   else if (sop == 2 && sopcde == 2 && bit8 == 0)
   4468     {
   4469       OUTS (outf, dregs (dst0));
   4470       OUTS (outf, " = ");
   4471       OUTS (outf, dregs (src1));
   4472       OUTS (outf, " << ");
   4473       OUTS (outf, uimm5 (immag));
   4474     }
   4475   else if (sop == 3 && sopcde == 2)
   4476     {
   4477       OUTS (outf, dregs (dst0));
   4478       OUTS (outf, " = ROT ");
   4479       OUTS (outf, dregs (src1));
   4480       OUTS (outf, " BY ");
   4481       OUTS (outf, imm6 (immag));
   4482     }
   4483   else if (sop == 0 && sopcde == 2)
   4484     {
   4485       OUTS (outf, dregs (dst0));
   4486       OUTS (outf, " = ");
   4487       OUTS (outf, dregs (src1));
   4488       OUTS (outf, " >>> ");
   4489       OUTS (outf, uimm5 (newimmag));
   4490     }
   4491   else
   4492     return 0;
   4493 
   4494   return 4;
   4495 }
   4496 
   4497 static int
   4498 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
   4499 {
   4500   struct private *priv = outf->private_data;
   4501   /* pseudoDEBUG
   4502      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   4503      | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
   4504      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   4505   int fn  = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
   4506   int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
   4507   int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
   4508 
   4509   if (priv->parallel)
   4510     return 0;
   4511 
   4512   if (reg == 0 && fn == 3)
   4513     OUTS (outf, "DBG A0");
   4514 
   4515   else if (reg == 1 && fn == 3)
   4516     OUTS (outf, "DBG A1");
   4517 
   4518   else if (reg == 3 && fn == 3)
   4519     OUTS (outf, "ABORT");
   4520 
   4521   else if (reg == 4 && fn == 3)
   4522     OUTS (outf, "HLT");
   4523 
   4524   else if (reg == 5 && fn == 3)
   4525     OUTS (outf, "DBGHALT");
   4526 
   4527   else if (reg == 6 && fn == 3)
   4528     {
   4529       OUTS (outf, "DBGCMPLX (");
   4530       OUTS (outf, dregs (grp));
   4531       OUTS (outf, ")");
   4532     }
   4533   else if (reg == 7 && fn == 3)
   4534     OUTS (outf, "DBG");
   4535 
   4536   else if (grp == 0 && fn == 2)
   4537     {
   4538       OUTS (outf, "OUTC ");
   4539       OUTS (outf, dregs (reg));
   4540     }
   4541   else if (fn == 0)
   4542     {
   4543       OUTS (outf, "DBG ");
   4544       OUTS (outf, allregs (reg, grp));
   4545     }
   4546   else if (fn == 1)
   4547     {
   4548       OUTS (outf, "PRNT ");
   4549       OUTS (outf, allregs (reg, grp));
   4550     }
   4551   else
   4552     return 0;
   4553 
   4554   return 2;
   4555 }
   4556 
   4557 static int
   4558 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
   4559 {
   4560   struct private *priv = outf->private_data;
   4561   /* psedoOChar
   4562      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   4563      | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
   4564      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   4565   int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
   4566 
   4567   if (priv->parallel)
   4568     return 0;
   4569 
   4570   OUTS (outf, "OUTC ");
   4571   OUTS (outf, uimm8 (ch));
   4572 
   4573   return 2;
   4574 }
   4575 
   4576 static int
   4577 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
   4578 {
   4579   struct private *priv = outf->private_data;
   4580   /* pseudodbg_assert
   4581      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
   4582      | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
   4583      |.expected......................................................|
   4584      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   4585   int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
   4586   int dbgop    = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
   4587   int grp      = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
   4588   int regtest  = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
   4589 
   4590   if (priv->parallel)
   4591     return 0;
   4592 
   4593   if (dbgop == 0)
   4594     {
   4595       OUTS (outf, "DBGA (");
   4596       OUTS (outf, regs_lo (regtest, grp));
   4597       OUTS (outf, ", ");
   4598       OUTS (outf, uimm16 (expected));
   4599       OUTS (outf, ")");
   4600     }
   4601   else if (dbgop == 1)
   4602     {
   4603       OUTS (outf, "DBGA (");
   4604       OUTS (outf, regs_hi (regtest, grp));
   4605       OUTS (outf, ", ");
   4606       OUTS (outf, uimm16 (expected));
   4607       OUTS (outf, ")");
   4608     }
   4609   else if (dbgop == 2)
   4610     {
   4611       OUTS (outf, "DBGAL (");
   4612       OUTS (outf, allregs (regtest, grp));
   4613       OUTS (outf, ", ");
   4614       OUTS (outf, uimm16 (expected));
   4615       OUTS (outf, ")");
   4616     }
   4617   else if (dbgop == 3)
   4618     {
   4619       OUTS (outf, "DBGAH (");
   4620       OUTS (outf, allregs (regtest, grp));
   4621       OUTS (outf, ", ");
   4622       OUTS (outf, uimm16 (expected));
   4623       OUTS (outf, ")");
   4624     }
   4625   else
   4626     return 0;
   4627   return 4;
   4628 }
   4629 
   4630 static int
   4631 ifetch (bfd_vma pc, disassemble_info *outf, TIword *iw)
   4632 {
   4633   bfd_byte buf[2];
   4634   int status;
   4635 
   4636   status = (*outf->read_memory_func) (pc, buf, 2, outf);
   4637   if (status != 0)
   4638     {
   4639       (*outf->memory_error_func) (status, pc, outf);
   4640       return -1;
   4641     }
   4642 
   4643   *iw = bfd_getl16 (buf);
   4644   return 0;
   4645 }
   4646 
   4647 static int
   4648 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
   4649 {
   4650   struct private *priv = outf->private_data;
   4651   TIword iw0;
   4652   TIword iw1;
   4653   int rv = 0;
   4654 
   4655   /* The PC must be 16-bit aligned.  */
   4656   if (pc & 1)
   4657     {
   4658       OUTS (outf, "ILLEGAL (UNALIGNED)");
   4659       /* For people dumping data, just re-align the return value.  */
   4660       return 1;
   4661     }
   4662 
   4663   if (ifetch (pc, outf, &iw0))
   4664     return -1;
   4665   priv->iw0 = iw0;
   4666 
   4667   if ((iw0 & 0xc000) == 0xc000)
   4668     {
   4669       /* 32-bit insn.  */
   4670       if (ifetch (pc + 2, outf, &iw1))
   4671 	return -1;
   4672     }
   4673   else
   4674     /* 16-bit insn.  */
   4675     iw1 = 0;
   4676 
   4677   if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
   4678     {
   4679       if (priv->parallel)
   4680 	{
   4681 	  OUTS (outf, "ILLEGAL");
   4682 	  return 0;
   4683 	}
   4684       OUTS (outf, "MNOP");
   4685       return 4;
   4686     }
   4687   else if ((iw0 & 0xff00) == 0x0000)
   4688     rv = decode_ProgCtrl_0 (iw0, outf);
   4689   else if ((iw0 & 0xffc0) == 0x0240)
   4690     rv = decode_CaCTRL_0 (iw0, outf);
   4691   else if ((iw0 & 0xff80) == 0x0100)
   4692     rv = decode_PushPopReg_0 (iw0, outf);
   4693   else if ((iw0 & 0xfe00) == 0x0400)
   4694     rv = decode_PushPopMultiple_0 (iw0, outf);
   4695   else if ((iw0 & 0xfe00) == 0x0600)
   4696     rv = decode_ccMV_0 (iw0, outf);
   4697   else if ((iw0 & 0xf800) == 0x0800)
   4698     rv = decode_CCflag_0 (iw0, outf);
   4699   else if ((iw0 & 0xffe0) == 0x0200)
   4700     rv = decode_CC2dreg_0 (iw0, outf);
   4701   else if ((iw0 & 0xff00) == 0x0300)
   4702     rv = decode_CC2stat_0 (iw0, outf);
   4703   else if ((iw0 & 0xf000) == 0x1000)
   4704     rv = decode_BRCC_0 (iw0, pc, outf);
   4705   else if ((iw0 & 0xf000) == 0x2000)
   4706     rv = decode_UJUMP_0 (iw0, pc, outf);
   4707   else if ((iw0 & 0xf000) == 0x3000)
   4708     rv = decode_REGMV_0 (iw0, outf);
   4709   else if ((iw0 & 0xfc00) == 0x4000)
   4710     rv = decode_ALU2op_0 (iw0, outf);
   4711   else if ((iw0 & 0xfe00) == 0x4400)
   4712     rv = decode_PTR2op_0 (iw0, outf);
   4713   else if ((iw0 & 0xf800) == 0x4800)
   4714     rv = decode_LOGI2op_0 (iw0, outf);
   4715   else if ((iw0 & 0xf000) == 0x5000)
   4716     rv = decode_COMP3op_0 (iw0, outf);
   4717   else if ((iw0 & 0xf800) == 0x6000)
   4718     rv = decode_COMPI2opD_0 (iw0, outf);
   4719   else if ((iw0 & 0xf800) == 0x6800)
   4720     rv = decode_COMPI2opP_0 (iw0, outf);
   4721   else if ((iw0 & 0xf000) == 0x8000)
   4722     rv = decode_LDSTpmod_0 (iw0, outf);
   4723   else if ((iw0 & 0xff60) == 0x9e60)
   4724     rv = decode_dagMODim_0 (iw0, outf);
   4725   else if ((iw0 & 0xfff0) == 0x9f60)
   4726     rv = decode_dagMODik_0 (iw0, outf);
   4727   else if ((iw0 & 0xfc00) == 0x9c00)
   4728     rv = decode_dspLDST_0 (iw0, outf);
   4729   else if ((iw0 & 0xf000) == 0x9000)
   4730     rv = decode_LDST_0 (iw0, outf);
   4731   else if ((iw0 & 0xfc00) == 0xb800)
   4732     rv = decode_LDSTiiFP_0 (iw0, outf);
   4733   else if ((iw0 & 0xe000) == 0xA000)
   4734     rv = decode_LDSTii_0 (iw0, outf);
   4735   else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
   4736     rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
   4737   else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
   4738     rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
   4739   else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
   4740     rv = decode_CALLa_0 (iw0, iw1, pc, outf);
   4741   else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
   4742     rv = decode_LDSTidxI_0 (iw0, iw1, outf);
   4743   else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
   4744     rv = decode_linkage_0 (iw0, iw1, outf);
   4745   else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
   4746     rv = decode_dsp32mac_0 (iw0, iw1, outf);
   4747   else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
   4748     rv = decode_dsp32mult_0 (iw0, iw1, outf);
   4749   else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
   4750     rv = decode_dsp32alu_0 (iw0, iw1, outf);
   4751   else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
   4752     rv = decode_dsp32shift_0 (iw0, iw1, outf);
   4753   else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
   4754     rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
   4755   else if ((iw0 & 0xff00) == 0xf800)
   4756     rv = decode_pseudoDEBUG_0 (iw0, outf);
   4757   else if ((iw0 & 0xFF00) == 0xF900)
   4758     rv = decode_pseudoOChar_0 (iw0, outf);
   4759   else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
   4760     rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
   4761 
   4762   if (rv == 0)
   4763     OUTS (outf, "ILLEGAL");
   4764 
   4765   return rv;
   4766 }
   4767 
   4768 int
   4769 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
   4770 {
   4771   struct private priv;
   4772   int count;
   4773 
   4774   priv.parallel = FALSE;
   4775   priv.comment = FALSE;
   4776   outf->private_data = &priv;
   4777 
   4778   count = _print_insn_bfin (pc, outf);
   4779   if (count == -1)
   4780     return -1;
   4781 
   4782   /* Proper display of multiple issue instructions.  */
   4783 
   4784   if (count == 4 && (priv.iw0 & 0xc000) == 0xc000 && (priv.iw0 & BIT_MULTI_INS)
   4785       && ((priv.iw0 & 0xe800) != 0xe800 /* Not Linkage.  */ ))
   4786     {
   4787       bfd_boolean legal = TRUE;
   4788       int len;
   4789 
   4790       priv.parallel = TRUE;
   4791       OUTS (outf, " || ");
   4792       len = _print_insn_bfin (pc + 4, outf);
   4793       if (len == -1)
   4794 	return -1;
   4795       OUTS (outf, " || ");
   4796       if (len != 2)
   4797 	legal = FALSE;
   4798       len = _print_insn_bfin (pc + 6, outf);
   4799       if (len == -1)
   4800 	return -1;
   4801       if (len != 2)
   4802 	legal = FALSE;
   4803 
   4804       if (legal)
   4805 	count = 8;
   4806       else
   4807 	{
   4808 	  OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
   4809 	  priv.comment = TRUE;
   4810 	  count = 0;
   4811 	}
   4812     }
   4813 
   4814   if (!priv.comment)
   4815     OUTS (outf, ";");
   4816 
   4817   if (count == 0)
   4818     return 2;
   4819 
   4820   return count;
   4821 }
   4822