| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| pcrel.d | 9 ( 0: e9 30 12 00 00[ ]*jmp 1235 .*1: R_386_PC32 \*ABS\*| 0: e9 2f 12 00 00[ ]*jmp 1234 .*1: DISP32 \*ABS\*)
12 ( 5: e9 fc ff ff ff[ ]*jmp 6 .*6: R_386_PC32 ext| 5: e9 f6 ff ff ff[ ]*jmp 0 .*6: DISP32 ext)
13 ( a: e9 fc ff ff ff[ ]*jmp b .*b: R_386_PC32 weak| a: e9 f1 ff ff ff[ ]*jmp 0 .*b: DISP32 weak)
14 ( f: e9 fc ff ff ff[ ]*jmp 10 .*10: R_386_PC32 comm| f: e9 ec ff ff ff[ ]*jmp 0 .*10: DISP32 comm| f: e9 f0 ff ff ff jmp 4 .*10: DISP32 comm.*)
17 (1b: e9 72 98 00 00[ ]*jmp 9892 .*1c: R_386_PC32 \*ABS\*|18: e9 59 98 00 00[ ]*jmp 9876 .*19: DISP32 \*ABS\*)
20 (2a: e9 fc ff ff ff[ ]*jmp 2b .*2b: R_386_PC32 \.data|27: e9 d4 00 00 00[ ]*jmp 100 .*28: DISP32 \.data.*|27: e9 d4 ff ff ff jmp 0 .*28: DISP32 \.data)
21 (2f: e9 00 00 00 00[ ]*jmp 34 .*30: R_386_PC32 \.data|2c: e9 d3 00 00 00[ ]*jmp 104 .*2d: DISP32 \.data.*|2c: e9 d3 ff ff ff jmp 4 .*2d: DISP32 \.data
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| i386-opc.tbl | 25 mov, 2, 0xa0, None, 1, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword }
26 mov, 2, 0x88, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixOk=3, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
30 mov, 2, 0xc6, 0x0, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixOk=3, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
38 mov, 2, 0x8c, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2, Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
40 mov, 2, 0x8c, None, 1, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg3, Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
42 mov, 2, 0x8e, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg2 }
44 mov, 2, 0x8e, None, 1, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg3 }
56 movbe, 2, 0x0f38f0, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
57 movbe, 2, 0x0f38f1, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
62 movsbl, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32
[all...] |
| i386-gen.c | 283 "Disp32" },
331 "Disp16|Disp32" },
333 "Disp8|Disp16|Disp32|Disp32S|Disp64" },
343 "Imm32|Imm32S|Disp32" },
347 "Imm32|Imm32S|Imm64|Disp32" },
349 "Imm32|Imm32S|Imm64|Disp32|Disp64" },
544 BITFIELD (Disp32),
[all...] |
| i386-opc.h | 670 Disp32,
770 unsigned int disp32:1; member in struct:i386_operand_type::__anon116489
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/h8300/ |
| pr3134.d | 2 # name: Check that both encodings of mov.l (disp32) are accepted (PR 3134)
|
| /toolchain/binutils/binutils-2.25/include/aout/ |
| reloc.h | 54 "DISP16", "DISP32", "WDISP30", "WDISP22", \
|
| /toolchain/binutils/binutils-2.25/bfd/ |
| coff-we32k.c | 53 HOWTO(R_PCRLONG, 0, 2, 32, TRUE, 0, complain_overflow_signed, 0, "DISP32", TRUE, 0xffffffff,0xffffffff, FALSE),
|
| coff-apollo.c | 42 HOWTO (R_PCRLONG, 0, 2, 32, TRUE, 0, complain_overflow_signed, 0, "DISP32", TRUE, 0xffffffff,0xffffffff, FALSE),
|
| coff-x86_64.c | 270 "DISP32+1", /* name */
283 "DISP32+2", /* name */
296 "DISP32+3", /* name */
309 "DISP32+4", /* name */
322 "DISP32+5", /* name */
|
| mach-o-x86-64.c | 80 NULL, "DISP32",
|
| mach-o-i386.c | 80 NULL, "DISP32",
|
| aout-arm.c | 80 HOWTO (6, 0, 2, 32, TRUE, 0, complain_overflow_signed, 0, "DISP32", TRUE,
|
| coff-i860.c | 269 "DISP32", /* name */
|
| coff-m68k.c | 103 HOWTO (R_PCRLONG, 0, 2, 32, TRUE, 0, complain_overflow_signed, RELOC_SPECIAL_FN, "DISP32", TRUE, 0xffffffff,0xffffffff, FALSE),
|
| nlm32-i386.c | 60 "DISP32", /* Name. */
|
| /external/elfutils/backends/ |
| sparc_reloc.def | 37 RELOC_TYPE (DISP32, REL)
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86CodeEmitter.cpp | 475 (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode
503 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
505 if (BaseReg == 0 || // [disp32] in X86-32 mode
506 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
514 // encoding for [EBP] with no displacement means [disp32] so we handle it
528 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
546 // Emit the normal disp32 encoding.
557 // Emit the normal disp32 encoding...
571 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-mcore.c | 67 #define DISP32 2
94 { 2048, -2046, C12_LEN, C(COND_JUMP, DISP32) }, /* DISP12 */
95 { 0, 0, C32_LEN, 0 }, /* DISP32 */
100 { 2048, -2046, U12_LEN, C(UNCD_JUMP, DISP32) }, /* DISP12 */
101 { 0, 0, U32_LEN, 0 }, /* DISP32 */
181 md_relax_table[C (UNCD_JUMP, DISP32)].rlx_length,
1458 md_relax_table[C (COND_JUMP, DISP32)].rlx_length,
[all...] |
| tc-i386-intel.c | 862 i.types[0].bitfield.disp32 = 0;
888 i.types[this_operand].bitfield.disp32 = 1;
896 i.types[this_operand].bitfield.disp32 = 1;
|
| tc-i386.c | 1684 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; variable
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 253 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
292 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
295 if (BaseReg == 0) { // [disp32] in X86-32 mode
303 // encoding for [EBP] with no displacement means [disp32] so we handle it
317 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
336 // Emit the normal disp32 encoding.
350 // Emit the normal disp32 encoding.
364 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 363 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
481 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
484 if (BaseReg == 0) { // [disp32] in X86-32 mode
492 // encoding for [EBP] with no displacement means [disp32] so we handle it
517 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
541 // Emit the normal disp32 encoding.
560 // Emit the normal disp32 encoding.
574 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
[all...] |
| /external/google-breakpad/src/third_party/libdisasm/ |
| ia32_invariant.c | 24 /* if (MODRM.MOD_NODISP && MODRM.RM_NOREG) then just disp32 */
|
| ia32_modrm.c | 17 /* if (MODRM.MOD_NODISP && MODRM.RM_NOREG) then just disp32 */
|
| /external/swiftshader/third_party/subzero/src/ |
| IceTargetLoweringX8632Traits.h | 118 int32_t disp32() const { function in class:Ice::X8632::TargetX8632Traits::Operand
122 llvm::report_fatal_error("Unexpected call to disp32()");
[all...] |
