| /external/vixl/test/aarch32/config/ |
| cond-sp-sp-operand-imm7-t32.json | 28 // MNEMONIC{<c>}.N <Rd>, SP #<imm7>
32 "Add", // ADD{<c>}{<q>} {SP}, SP, #<imm7> ; T2
33 "Sub" // SUB{<c>}{<q>} {SP}, SP, #<imm7> ; T1
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| ldst-reg-pair.s | 45 // a variety of values for the imm7 field
46 .irp imm7, -64, -31, -1, 0, 15, 63
49 op3_offset \op, \reg, "(\imm7*\size)"
53 op3_post_ind \op, \reg, "(\imm7*\size)"
57 op3_pre_ind \op, \reg, "(\imm7*\size)"
|
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 1121 Instr Assembler::ImmLSPair(int imm7, LSDataSize size) {
1122 DCHECK(((imm7 >> size) << size) == imm7);
1123 int scaled_imm7 = imm7 >> size;
1147 Instr Assembler::ImmHint(int imm7) {
1148 DCHECK(is_uint7(imm7));
1149 return imm7 << ImmHint_offset;
[all...] |
| assembler-arm64.h | [all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| maverick.c | 124 imm7 (func_arg *arg, insn_data *data) function
125 #define imm7 { imm7 } macro
205 signed immediate generated with imm7. */
208 mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| README.txt | 82 | Ks7 | imm7 | |
83 | KN7 | -imm7 | |
|
| BlackfinInstrInfo.td | 82 def imm7 : PatLeaf<(imm), [{return isInt<7>(N->getSExtValue());}]>;
191 [(set DP:$dst, imm7:$src)]>;
754 [(set D:$dst, (add D:$src1, imm7:$src2))]>;
[all...] |
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 644 unsigned imm7 = 0; local
646 imm7 = fieldFromInstruction(insn, 0, 7);
655 // Decode RS1 | IMM7.
657 MI.addOperand(MCOperand::createImm(imm7));
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| bfin-parse.y | 215 #define imm7(x) EXPR_VALUE (x)
242 if (imm7 (reg2) != reg1->regno - 1)
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| p8-scalar_vector_conversions.ll | 685 ; CHECK-DAG: li [[IMM7:[0-9]+]], 7
686 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
696 ; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7
697 ; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]]
719 ; CHECK-DAG: li [[IMM7:[0-9]+]], 7
720 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
730 ; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7
731 ; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]]
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-sp-sp-operand-imm7-t32.cc | 228 #include "aarch32/traces/assembler-cond-sp-sp-operand-imm7-t32-add.h"
229 #include "aarch32/traces/assembler-cond-sp-sp-operand-imm7-t32-sub.h"
|
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| nds32.h | 111 #define N16_TYPE37(op4, rt3, ls, imm7) \
113 | __MF (imm7, 0, 7) | __MF (ls, 7, 1))
|
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 295 // sub sp, sp, #imm7
|
| ARMInstrThumb.td | 389 // ADD sp, sp, #<imm7>
399 // SUB sp, sp, #<imm7>
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 234 // sub sp, sp, #imm7
|
| ARMInstrThumb.td | 327 // ADD sp, sp, #<imm7>
337 // SUB sp, sp, #<imm7>
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| bfin-dis.c | 94 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
470 #define imm7(x) fmtconst (c_imm7, x, 0, outf) macro
[all...] |
| aarch64-asm.c | 544 /* simm (imm9 or imm7) */
[all...] |
| aarch64-dis.c | 891 /* simm (imm9 or imm7) */
[all...] |
| aarch64-opc.c | 181 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | 7180 UInt imm7 = INSN(11,5); local
[all...] |
| /external/vixl/tools/ |
| generate_tests.py | 649 'test/aarch32/config/cond-sp-sp-operand-imm7-t32.json',
|
| /external/vixl/src/aarch32/ |
| assembler-aarch32.cc | [all...] |
| disasm-aarch32.cc | [all...] |
