| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| intel_regions.c | 111 uint32_t tiling, drm_intel_bo *buffer)
125 region->tiling = tiling;
133 uint32_t tiling,
147 &tiling, &aligned_pitch, flags);
152 aligned_pitch, tiling, buffer);
183 uint32_t bit_6_swizzle, tiling; local
188 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle);
190 fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
197 width, height, pitch, tiling, buffer)
218 uint32_t bit_6_swizzle, tiling; local
291 uint32_t tiling = region->tiling; local
324 uint32_t tiling = region->tiling; local
[all...] |
| /external/mesa3d/src/intel/isl/ |
| isl_gen9.c | 30 * for the standard tiling formats Yf and Ys.
35 enum isl_tiling tiling,
41 assert(isl_tiling_is_std_y(tiling));
44 const uint32_t is_Ys = tiling == ISL_TILING_Ys;
49 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
59 * Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment
86 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
102 enum isl_tiling tiling,
124 * Surface Layout and Tiling > 2D Surfaces]:
146 * Tiling" section under Common Surface Formats for the table o
[all...] |
| isl_gen4.h | 36 enum isl_tiling tiling,
42 enum isl_tiling tiling,
|
| isl_gen6.h | 36 enum isl_tiling tiling,
42 enum isl_tiling tiling,
|
| isl_gen7.h | 41 enum isl_tiling tiling,
47 enum isl_tiling tiling,
|
| isl_gen8.h | 36 enum isl_tiling tiling,
42 enum isl_tiling tiling,
|
| isl.c | 128 enum isl_tiling tiling,
135 if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) {
139 * This really only works on legacy X and Y tiling formats.
141 assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0);
143 return isl_tiling_get_info(dev, tiling, format_bpb / 3, tile_info);
146 switch (tiling) {
190 bool is_Ys = tiling == ISL_TILING_Ys;
203 * 128bpb format. The tiling has the same physical dimensions as
204 * Y-tiling but actually has two HiZ columns per Y-tiled column
1192 enum isl_tiling tiling; local
[all...] |
| isl_gen7.c | 30 enum isl_tiling tiling,
86 if (tiling == ISL_TILING_LINEAR)
174 * @brief Filter out tiling flags that are incompatible with the surface.
181 * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling
209 /* Separate stencil requires W tiling, and W tiling requires separate
245 /* FINISHME[SKL]: Y tiling for display surfaces */
262 * As usual, though, stencil is special and requires W-tiling.
272 /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1,
323 enum isl_tiling tiling)
[all...] |
| isl_storage_image.c | 246 switch (surf->tiling) {
253 param->tiling[0] = isl_log2u(512 / cpp);
254 param->tiling[1] = isl_log2u(8);
269 * one arranged in X-major order just like is the case for X-tiling.
271 param->tiling[0] = isl_log2u(16 / cpp);
272 param->tiling[1] = isl_log2u(32);
284 assert(!"Unhandled storage image tiling");
289 * brw_fs_surface_builder.cpp) handles this as a sort of tiling with
292 param->tiling[2] = (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D ?
|
| /frameworks/base/graphics/java/android/graphics/ |
| BitmapShader.java | 23 * mirrored by setting the tiling mode.
40 * @param tileX The tiling mode for x to draw the bitmap in.
41 * @param tileY The tiling mode for y to draw the bitmap in.
|
| /external/skia/src/gpu/vk/ |
| GrVkImage.h | 98 void setNewResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling);
115 Resource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling)
120 , fImageTiling(tiling) {}
155 BorrowedResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling)
156 : Resource(image, alloc, tiling) {
|
| /external/vulkan-validation-layers/loader/ |
| extensions.c | 35 VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags,
44 unwrapped_phys_dev, format, type, tiling, usage, flags,
51 VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags,
72 phys_dev->phys_dev, format, type, tiling, usage, flags,
77 phys_dev->phys_dev, format, type, tiling, usage, flags,
|
| /external/mesa3d/src/gallium/drivers/ilo/core/ |
| ilo_builder_blt.h | 57 enum gen_surface_tiling tiling; member in struct:gen6_blt_xy_bo
174 if (dst->tiling != GEN6_TILING_NONE) {
177 assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y);
178 dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512;
278 if (dst->tiling != GEN6_TILING_NONE) {
281 assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y);
282 dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512;
287 if (src->tiling != GEN6_TILING_NONE)
[all...] |
| /external/mesa3d/docs/specs/ |
| WL_create_wayland_buffer_from_image.spec | 82 format or tiling mode or that the buffer is in memory that is inaccessible
88 this include for example unsupported tiling modes?
93 unsupported tiling modes, inaccessible memory or an unsupported pixel
|
| /external/pdfium/core/fpdfapi/page/ |
| cpdf_pattern.h | 20 enum PatternType { TILING = 1, SHADING };
|
| /external/mesa3d/src/gallium/winsys/intel/drm/ |
| intel_drm_winsys.c | 95 uint32_t tiling = I915_TILING_X, swizzle; local
99 "address swizzling test", 64, 64, 4, &tiling, &pitch, 0);
101 drm_intel_bo_get_tiling(bo, &tiling, &swizzle);
309 enum intel_tiling_mode *tiling,
350 *tiling = real_tiling;
359 enum intel_tiling_mode tiling,
490 enum intel_tiling_mode tiling,
493 uint32_t real_tiling = tiling;
496 switch (tiling) {
510 if (err || real_tiling != tiling) {
[all...] |
| /external/libdrm/tegra/ |
| tegra.h | 61 struct drm_tegra_bo_tiling *tiling);
63 const struct drm_tegra_bo_tiling *tiling);
|
| tegra.c | 341 struct drm_tegra_bo_tiling *tiling)
358 if (tiling) {
359 tiling->mode = args.mode;
360 tiling->value = args.value;
367 const struct drm_tegra_bo_tiling *tiling)
378 args.mode = tiling->mode;
379 args.value = tiling->value;
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| intel_tiled_memcpy.h | 46 uint32_t tiling,
55 uint32_t tiling,
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_winsys.h | 160 * the tiling mode provide in *tiling. If tiling is no possible, *tiling will
167 enum i915_winsys_buffer_tile *tiling,
180 enum i915_winsys_buffer_tile *tiling,
|
| /external/deqp/external/vulkancts/modules/vulkan/ycbcr/ |
| vktYCbCrFormatTests.cpp | 78 VkImageTiling tiling,
92 tiling,
230 VkImageTiling tiling; member in struct:vkt::ycbcr::__anon16855::TestParameters
243 , tiling (tiling_)
252 , tiling (VK_IMAGE_TILING_OPTIMAL)
277 checkImageSupport(context, params.format, params.flags, params.tiling);
305 const VkImageTiling tiling = params.tiling; local
308 const Unique<VkImage> image (createTestImage(vkd, device, format, size, createFlags, tiling, mappedMemory ? VK_IMAGE_LAYOUT_PREINITIALIZED : VK_IMAGE_LAYOUT_UNDEFINED));
507 const VkImageTiling tiling = tilings[tilingNdx].value local
[all...] |
| /external/mesa3d/src/gallium/drivers/ilo/ |
| ilo_resource.c | 220 winsys_to_surface_tiling(enum intel_tiling_mode tiling)
222 switch (tiling) {
230 assert(!"unknown tiling");
236 surface_to_winsys_tiling(enum gen_surface_tiling tiling)
238 switch (tiling) {
246 assert(!"unknown tiling");
300 /* set the tiling for transfer and export */
301 if (bo && (tex->image.tiling == GEN6_TILING_X ||
302 tex->image.tiling == GEN6_TILING_Y)) {
303 const enum intel_tiling_mode tiling local
442 enum intel_tiling_mode tiling; local
579 enum intel_tiling_mode tiling; local
[all...] |
| ilo_blitter_blt.c | 252 /* no W-tiling nor separate stencil support */
253 if (dst_tex->image.tiling == GEN8_TILING_W || dst_tex->separate_s8)
265 dst.tiling = dst_tex->image.tiling;
269 dst_tex->vma.bo, dst_tex->image.tiling, NULL, GEN6_TILING_NONE);
312 /* no W-tiling nor separate stencil support */
313 if (dst_tex->image.tiling == GEN8_TILING_W || dst_tex->separate_s8 ||
314 src_tex->image.tiling == GEN8_TILING_W || src_tex->separate_s8)
354 dst.tiling = dst_tex->image.tiling;
[all...] |
| /external/mesa3d/src/intel/vulkan/ |
| anv_gem.c | 176 uint32_t gem_handle, uint32_t stride, uint32_t tiling)
186 .tiling_mode = tiling,
214 anv_gem_get_bit6_swizzle(int fd, uint32_t tiling)
236 .tiling_mode = tiling,
237 .stride = tiling == I915_TILING_X ? 512 : 128,
244 assert(!"Failed to set BO tiling");
253 assert(!"Failed to get BO tiling");
|
| /external/libdrm/intel/ |
| intel_bufmgr_priv.h | 82 * Valid tiling formats are:
87 * Note the tiling format may be rejected; callers should check the
89 * may have been rounded up to accommodate for tiling restrictions.
225 * Ask that the buffer be placed in tiling mode
227 * \param buf Buffer to set tiling mode for
228 * \param tiling_mode desired, and returned tiling mode
234 * Get the current tiling (and resulting swizzling) mode for the bo.
236 * \param buf Buffer to get tiling mode for
237 * \param tiling_mode returned tiling mode
|
