1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __VMWGFX_DRM_H__ 20 #define __VMWGFX_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 #endif 24 #define DRM_VMW_MAX_SURFACE_FACES 6 25 #define DRM_VMW_MAX_MIP_LEVELS 24 26 #define DRM_VMW_GET_PARAM 0 27 #define DRM_VMW_ALLOC_DMABUF 1 28 #define DRM_VMW_UNREF_DMABUF 2 29 #define DRM_VMW_CURSOR_BYPASS 3 30 #define DRM_VMW_CONTROL_STREAM 4 31 #define DRM_VMW_CLAIM_STREAM 5 32 #define DRM_VMW_UNREF_STREAM 6 33 #define DRM_VMW_CREATE_CONTEXT 7 34 #define DRM_VMW_UNREF_CONTEXT 8 35 #define DRM_VMW_CREATE_SURFACE 9 36 #define DRM_VMW_UNREF_SURFACE 10 37 #define DRM_VMW_REF_SURFACE 11 38 #define DRM_VMW_EXECBUF 12 39 #define DRM_VMW_GET_3D_CAP 13 40 #define DRM_VMW_FENCE_WAIT 14 41 #define DRM_VMW_FENCE_SIGNALED 15 42 #define DRM_VMW_FENCE_UNREF 16 43 #define DRM_VMW_FENCE_EVENT 17 44 #define DRM_VMW_PRESENT 18 45 #define DRM_VMW_PRESENT_READBACK 19 46 #define DRM_VMW_UPDATE_LAYOUT 20 47 #define DRM_VMW_CREATE_SHADER 21 48 #define DRM_VMW_UNREF_SHADER 22 49 #define DRM_VMW_GB_SURFACE_CREATE 23 50 #define DRM_VMW_GB_SURFACE_REF 24 51 #define DRM_VMW_SYNCCPU 25 52 #define DRM_VMW_CREATE_EXTENDED_CONTEXT 26 53 #define DRM_VMW_PARAM_NUM_STREAMS 0 54 #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 55 #define DRM_VMW_PARAM_3D 2 56 #define DRM_VMW_PARAM_HW_CAPS 3 57 #define DRM_VMW_PARAM_FIFO_CAPS 4 58 #define DRM_VMW_PARAM_MAX_FB_SIZE 5 59 #define DRM_VMW_PARAM_FIFO_HW_VERSION 6 60 #define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 61 #define DRM_VMW_PARAM_3D_CAPS_SIZE 8 62 #define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 63 #define DRM_VMW_PARAM_MAX_MOB_SIZE 10 64 #define DRM_VMW_PARAM_SCREEN_TARGET 11 65 #define DRM_VMW_PARAM_DX 12 66 enum drm_vmw_handle_type { 67 DRM_VMW_HANDLE_LEGACY = 0, 68 DRM_VMW_HANDLE_PRIME = 1 69 }; 70 struct drm_vmw_getparam_arg { 71 __u64 value; 72 __u32 param; 73 __u32 pad64; 74 }; 75 struct drm_vmw_context_arg { 76 __s32 cid; 77 __u32 pad64; 78 }; 79 struct drm_vmw_surface_create_req { 80 __u32 flags; 81 __u32 format; 82 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES]; 83 __u64 size_addr; 84 __s32 shareable; 85 __s32 scanout; 86 }; 87 struct drm_vmw_surface_arg { 88 __s32 sid; 89 enum drm_vmw_handle_type handle_type; 90 }; 91 struct drm_vmw_size { 92 __u32 width; 93 __u32 height; 94 __u32 depth; 95 __u32 pad64; 96 }; 97 union drm_vmw_surface_create_arg { 98 struct drm_vmw_surface_arg rep; 99 struct drm_vmw_surface_create_req req; 100 }; 101 union drm_vmw_surface_reference_arg { 102 struct drm_vmw_surface_create_req rep; 103 struct drm_vmw_surface_arg req; 104 }; 105 #define DRM_VMW_EXECBUF_VERSION 2 106 struct drm_vmw_execbuf_arg { 107 __u64 commands; 108 __u32 command_size; 109 __u32 throttle_us; 110 __u64 fence_rep; 111 __u32 version; 112 __u32 flags; 113 __u32 context_handle; 114 __u32 pad64; 115 }; 116 struct drm_vmw_fence_rep { 117 __u32 handle; 118 __u32 mask; 119 __u32 seqno; 120 __u32 passed_seqno; 121 __u32 pad64; 122 __s32 error; 123 }; 124 struct drm_vmw_alloc_dmabuf_req { 125 __u32 size; 126 __u32 pad64; 127 }; 128 struct drm_vmw_dmabuf_rep { 129 __u64 map_handle; 130 __u32 handle; 131 __u32 cur_gmr_id; 132 __u32 cur_gmr_offset; 133 __u32 pad64; 134 }; 135 union drm_vmw_alloc_dmabuf_arg { 136 struct drm_vmw_alloc_dmabuf_req req; 137 struct drm_vmw_dmabuf_rep rep; 138 }; 139 struct drm_vmw_unref_dmabuf_arg { 140 __u32 handle; 141 __u32 pad64; 142 }; 143 struct drm_vmw_rect { 144 __s32 x; 145 __s32 y; 146 __u32 w; 147 __u32 h; 148 }; 149 struct drm_vmw_control_stream_arg { 150 __u32 stream_id; 151 __u32 enabled; 152 __u32 flags; 153 __u32 color_key; 154 __u32 handle; 155 __u32 offset; 156 __s32 format; 157 __u32 size; 158 __u32 width; 159 __u32 height; 160 __u32 pitch[3]; 161 __u32 pad64; 162 struct drm_vmw_rect src; 163 struct drm_vmw_rect dst; 164 }; 165 #define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) 166 #define DRM_VMW_CURSOR_BYPASS_FLAGS (1) 167 struct drm_vmw_cursor_bypass_arg { 168 __u32 flags; 169 __u32 crtc_id; 170 __s32 xpos; 171 __s32 ypos; 172 __s32 xhot; 173 __s32 yhot; 174 }; 175 struct drm_vmw_stream_arg { 176 __u32 stream_id; 177 __u32 pad64; 178 }; 179 struct drm_vmw_get_3d_cap_arg { 180 __u64 buffer; 181 __u32 max_size; 182 __u32 pad64; 183 }; 184 #define DRM_VMW_FENCE_FLAG_EXEC (1 << 0) 185 #define DRM_VMW_FENCE_FLAG_QUERY (1 << 1) 186 #define DRM_VMW_WAIT_OPTION_UNREF (1 << 0) 187 struct drm_vmw_fence_wait_arg { 188 __u32 handle; 189 __s32 cookie_valid; 190 __u64 kernel_cookie; 191 __u64 timeout_us; 192 __s32 lazy; 193 __s32 flags; 194 __s32 wait_options; 195 __s32 pad64; 196 }; 197 struct drm_vmw_fence_signaled_arg { 198 __u32 handle; 199 __u32 flags; 200 __s32 signaled; 201 __u32 passed_seqno; 202 __u32 signaled_flags; 203 __u32 pad64; 204 }; 205 struct drm_vmw_fence_arg { 206 __u32 handle; 207 __u32 pad64; 208 }; 209 #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 210 struct drm_vmw_event_fence { 211 struct drm_event base; 212 __u64 user_data; 213 __u32 tv_sec; 214 __u32 tv_usec; 215 }; 216 #define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0) 217 struct drm_vmw_fence_event_arg { 218 __u64 fence_rep; 219 __u64 user_data; 220 __u32 handle; 221 __u32 flags; 222 }; 223 struct drm_vmw_present_arg { 224 __u32 fb_id; 225 __u32 sid; 226 __s32 dest_x; 227 __s32 dest_y; 228 __u64 clips_ptr; 229 __u32 num_clips; 230 __u32 pad64; 231 }; 232 struct drm_vmw_present_readback_arg { 233 __u32 fb_id; 234 __u32 num_clips; 235 __u64 clips_ptr; 236 __u64 fence_rep; 237 }; 238 struct drm_vmw_update_layout_arg { 239 __u32 num_outputs; 240 __u32 pad64; 241 __u64 rects; 242 }; 243 enum drm_vmw_shader_type { 244 drm_vmw_shader_type_vs = 0, 245 drm_vmw_shader_type_ps, 246 }; 247 struct drm_vmw_shader_create_arg { 248 enum drm_vmw_shader_type shader_type; 249 __u32 size; 250 __u32 buffer_handle; 251 __u32 shader_handle; 252 __u64 offset; 253 }; 254 struct drm_vmw_shader_arg { 255 __u32 handle; 256 __u32 pad64; 257 }; 258 enum drm_vmw_surface_flags { 259 drm_vmw_surface_flag_shareable = (1 << 0), 260 drm_vmw_surface_flag_scanout = (1 << 1), 261 drm_vmw_surface_flag_create_buffer = (1 << 2) 262 }; 263 struct drm_vmw_gb_surface_create_req { 264 __u32 svga3d_flags; 265 __u32 format; 266 __u32 mip_levels; 267 enum drm_vmw_surface_flags drm_surface_flags; 268 __u32 multisample_count; 269 __u32 autogen_filter; 270 __u32 buffer_handle; 271 __u32 array_size; 272 struct drm_vmw_size base_size; 273 }; 274 struct drm_vmw_gb_surface_create_rep { 275 __u32 handle; 276 __u32 backup_size; 277 __u32 buffer_handle; 278 __u32 buffer_size; 279 __u64 buffer_map_handle; 280 }; 281 union drm_vmw_gb_surface_create_arg { 282 struct drm_vmw_gb_surface_create_rep rep; 283 struct drm_vmw_gb_surface_create_req req; 284 }; 285 struct drm_vmw_gb_surface_ref_rep { 286 struct drm_vmw_gb_surface_create_req creq; 287 struct drm_vmw_gb_surface_create_rep crep; 288 }; 289 union drm_vmw_gb_surface_reference_arg { 290 struct drm_vmw_gb_surface_ref_rep rep; 291 struct drm_vmw_surface_arg req; 292 }; 293 enum drm_vmw_synccpu_flags { 294 drm_vmw_synccpu_read = (1 << 0), 295 drm_vmw_synccpu_write = (1 << 1), 296 drm_vmw_synccpu_dontblock = (1 << 2), 297 drm_vmw_synccpu_allow_cs = (1 << 3) 298 }; 299 enum drm_vmw_synccpu_op { 300 drm_vmw_synccpu_grab, 301 drm_vmw_synccpu_release 302 }; 303 struct drm_vmw_synccpu_arg { 304 enum drm_vmw_synccpu_op op; 305 enum drm_vmw_synccpu_flags flags; 306 __u32 handle; 307 __u32 pad64; 308 }; 309 enum drm_vmw_extended_context { 310 drm_vmw_context_legacy, 311 drm_vmw_context_dx 312 }; 313 union drm_vmw_extended_context_arg { 314 enum drm_vmw_extended_context req; 315 struct drm_vmw_context_arg rep; 316 }; 317 #ifdef __cplusplus 318 #endif 319 #endif 320
