1 /*++ 2 3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> 4 5 This program and the accompanying materials are licensed and made available under 7 the terms and conditions of the BSD License that accompanies this distribution. 9 The full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php. 13 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 19 21 23 24 **/ 25 26 #include <Library/SpiFlash.H> 27 28 #define FLASH_SIZE 0x300000 29 #define FLASH_DEVICE_BASE_ADDRESS (0xFFFFFFFF-FLASH_SIZE+1) 30 31 // 32 // Serial Flash device initialization data table provided to the 33 // Intel(R) SPI Host Controller Compatibility Interface. 34 // 35 SPI_INIT_TABLE mInitTable[] = { 36 { 37 SF_VENDOR_ID_WINBOND, // VendorId 38 SF_DEVICE_ID0_W25QXX, // DeviceId 0 39 SF_DEVICE_ID1_W25Q64, // DeviceId 1 40 { 41 SF_INST_WREN, // Prefix Opcode 0: Write Enable 42 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register 43 }, 44 { 45 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 46 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 47 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 48 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 49 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 50 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 51 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 52 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 53 }, 54 55 // 56 // The offset of the start of the BIOS image in flash. This value is platform specific 57 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 58 // 59 ((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)), 60 61 // 62 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 63 // 64 FLASH_SIZE 65 }, 66 { 67 SF_VENDOR_ID_ATMEL, // VendorId 68 SF_DEVICE_ID0_AT25DF321A, // DeviceId 0 69 SF_DEVICE_ID1_AT25DF321A, // DeviceId 1 70 { 71 SF_INST_WREN, // Prefix Opcode 0: Write Enable 72 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR). 73 }, 74 { 75 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 76 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 77 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 78 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 79 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 80 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB) 81 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 82 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 83 }, 84 85 // 86 // The offset of the start of the BIOS image in flash. This value is platform specific 87 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 88 // 89 ((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE - FLASH_SIZE : (UINTN) (-1)), 90 91 // 92 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 93 // 94 FLASH_SIZE 95 }, 96 { 97 SF_VENDOR_ID_ATMEL, // VendorId 98 SF_DEVICE_ID0_AT26DF321, // DeviceId 0 99 SF_DEVICE_ID1_AT26DF321, // DeviceId 1 100 { 101 SF_INST_WREN, // Prefix Opcode 0: Write Enable 102 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR). 103 }, 104 { 105 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 106 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 107 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 108 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 109 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 110 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB) 111 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 112 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 113 }, 114 115 // 116 // The offset of the start of the BIOS image in flash. This value is platform specific 117 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 118 // 119 ((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE - FLASH_SIZE : (UINTN) (-1)), 120 121 // 122 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 123 // 124 FLASH_SIZE 125 }, 126 { 127 SF_VENDOR_ID_ATMEL, // VendorId 128 SF_DEVICE_ID0_AT25DF641, // DeviceId 0 129 SF_DEVICE_ID1_AT25DF641, // DeviceId 1 130 { 131 SF_INST_WREN, // Prefix Opcode 0: Write Enable 132 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR). 133 }, 134 { 135 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 136 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 137 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 138 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 139 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 140 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB) 141 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 142 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 143 }, 144 145 // 146 // The offset of the start of the BIOS image in flash. This value is platform specific 147 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 148 // 149 ((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE - FLASH_SIZE : (UINTN) (-1)), 150 151 // 152 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 153 // 154 FLASH_SIZE 155 }, 156 { 157 SF_VENDOR_ID_WINBOND, // VendorId 158 SF_DEVICE_ID0_W25QXX, // DeviceId 0 159 SF_DEVICE_ID1_W25Q16, // DeviceId 1 160 { 161 SF_INST_WREN, // Prefix Opcode 0: Write Enable 162 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register 163 }, 164 { 165 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 166 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 167 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 168 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 169 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 170 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 171 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 172 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 173 }, 174 175 // 176 // The offset of the start of the BIOS image in flash. This value is platform specific 177 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 178 // 179 ((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)), 180 181 // 182 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 183 // 184 FLASH_SIZE 185 }, 186 { 187 SF_VENDOR_ID_WINBOND, // VendorId 188 SF_DEVICE_ID0_W25QXX, // DeviceId 0 189 SF_DEVICE_ID1_W25Q32, // DeviceId 1 190 { 191 SF_INST_WREN, // Prefix Opcode 0: Write Enable 192 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register. 193 }, 194 { 195 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 196 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 197 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 198 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 199 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 200 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 201 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 202 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 203 }, 204 205 // 206 // The offset of the start of the BIOS image in flash. This value is platform specific 207 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 208 // 209 ((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)), 210 211 // 212 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 213 // 214 FLASH_SIZE 215 }, 216 { 217 SF_VENDOR_ID_WINBOND, // VendorId 218 SF_DEVICE_ID0_W25XXX, // DeviceId 0 219 SF_DEVICE_ID1_W25X32, // DeviceId 1 220 { 221 SF_INST_WREN, // Prefix Opcode 0: Write Enable 222 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register 223 }, 224 { 225 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 226 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 227 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 228 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 229 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 230 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 231 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 232 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 233 }, 234 235 // 236 // The offset of the start of the BIOS image in flash. This value is platform specific 237 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 238 // 239 ((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE - FLASH_SIZE : (UINTN) (-1)), 240 241 // 242 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 243 // 244 FLASH_SIZE 245 }, 246 { 247 SF_VENDOR_ID_WINBOND, // VendorId 248 SF_DEVICE_ID0_W25XXX, // DeviceId 0 249 SF_DEVICE_ID1_W25X64, // DeviceId 1 250 { 251 SF_INST_WREN, // Prefix Opcode 0: Write Enable 252 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register 253 }, 254 { 255 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 256 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 257 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 258 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 259 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 260 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 261 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 262 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 263 }, 264 265 // 266 // The offset of the start of the BIOS image in flash. This value is platform specific 267 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 268 // 269 ((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE - FLASH_SIZE : (UINTN) (-1)), 270 271 // 272 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 273 // 274 FLASH_SIZE 275 }, 276 { 277 SF_VENDOR_ID_WINBOND, // VendorId 278 SF_DEVICE_ID0_W25QXX, // DeviceId 0 279 SF_DEVICE_ID1_W25Q128, // DeviceId 1 280 { 281 SF_INST_WREN, // Prefix Opcode 0: Write Enable 282 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register 283 }, 284 { 285 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 286 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 287 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 288 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 289 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 290 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 291 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 292 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 293 }, 294 295 // 296 // The offset of the start of the BIOS image in flash. This value is platform specific 297 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 298 // 299 ((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)), 300 301 // 302 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 303 // 304 FLASH_SIZE 305 }, 306 { 307 SF_VENDOR_ID_MACRONIX, // VendorId 308 SF_DEVICE_ID0_MX25LXX, // DeviceId 0 309 SF_DEVICE_ID1_MX25L16, // DeviceId 1 310 { 311 SF_INST_WREN, // Prefix Opcode 0: Write Enable 312 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR). 313 }, 314 { 315 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 316 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 317 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 318 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 319 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 320 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 321 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 322 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 323 }, 324 325 // 326 // The offset of the start of the BIOS image in flash. This value is platform specific 327 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 328 // 329 ((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE - FLASH_SIZE : (UINTN) (-1)), 330 331 // 332 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 333 // 334 FLASH_SIZE 335 }, 336 { 337 SF_VENDOR_ID_MACRONIX, // VendorId 338 SF_DEVICE_ID0_MX25LXX, // DeviceId 0 339 SF_DEVICE_ID1_MX25L32, // DeviceId 1 340 { 341 SF_INST_WREN, // Prefix Opcode 0: Write Enable 342 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR). 343 }, 344 { 345 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 346 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 347 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 348 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 349 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 350 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 351 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 352 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 353 }, 354 355 // 356 // The offset of the start of the BIOS image in flash. This value is platform specific 357 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 358 // 359 ((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE - FLASH_SIZE : (UINTN) (-1)), 360 361 // 362 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 363 // 364 FLASH_SIZE 365 }, 366 { 367 SF_VENDOR_ID_MACRONIX, // VendorId 368 SF_DEVICE_ID0_MX25LXX, // DeviceId 0 369 SF_DEVICE_ID1_MX25L64, // DeviceId 1 370 { 371 SF_INST_WREN, // Prefix Opcode 0: Write Enable 372 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR) 373 }, 374 { 375 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 376 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 377 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 378 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 379 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 380 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 381 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 382 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 383 }, 384 385 // 386 // The offset of the start of the BIOS image in flash. This value is platform specific 387 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 388 // 389 ((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE - FLASH_SIZE : (UINTN) (-1)), 390 391 // 392 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 393 // 394 FLASH_SIZE 395 }, 396 { 397 SF_VENDOR_ID_MACRONIX, // VendorId 398 SF_DEVICE_ID0_MX25LXX, // DeviceId 0 399 SF_DEVICE_ID1_MX25L128, // DeviceId 1 400 { 401 SF_INST_WREN, // Prefix Opcode 0: Write Enable 402 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR) 403 }, 404 { 405 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 406 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 407 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 408 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 409 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 410 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 411 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 412 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 413 }, 414 415 // 416 // The offset of the start of the BIOS image in flash. This value is platform specific 417 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 418 // 419 ((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)), 420 421 // 422 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 423 // 424 FLASH_SIZE 425 }, 426 { 427 SF_VENDOR_ID_MACRONIX, // VendorId 428 SF_DEVICE_ID0_MX25UXX, // DeviceId 0 429 SF_DEVICE_ID1_MX25U6435F, // DeviceId 1 430 { 431 SF_INST_WREN, // Prefix Opcode 0: Write Enable 432 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR) 433 }, 434 { 435 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 436 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 437 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 438 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters 439 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 440 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 441 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 442 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 443 }, 444 445 // 446 // The offset of the start of the BIOS image in flash. This value is platform specific 447 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 448 // 449 ((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)), 450 451 // 452 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 453 // 454 FLASH_SIZE 455 }, 456 { 457 SF_VENDOR_ID_SST, // VendorId 458 SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0 459 SF_DEVICE_ID1_SST25VF016B,// DeviceId 1 460 { 461 SF_INST_WREN, // Prefix Opcode 0: Write Enable 462 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register 463 }, 464 { 465 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 466 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read 467 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 468 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 469 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 470 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB) 471 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 472 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 473 }, 474 475 // 476 // The offset of the start of the BIOS image in flash. This value is platform specific 477 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 478 // 479 ((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE - FLASH_SIZE : (UINTN) (-1)), 480 481 // 482 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 483 // 484 FLASH_SIZE 485 }, 486 { 487 SF_VENDOR_ID_SST, // VendorId 488 SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0 489 SF_DEVICE_ID1_SST25VF064C,// DeviceId 1 490 { 491 SF_INST_WREN, // Prefix Opcode 0: Write Enable 492 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register 493 }, 494 { 495 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 496 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read 497 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 498 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 499 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 500 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB) 501 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 502 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 503 }, 504 505 // 506 // The offset of the start of the BIOS image in flash. This value is platform specific 507 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 508 // 509 ((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE - FLASH_SIZE : (UINTN) (-1)), 510 511 // 512 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 513 // 514 FLASH_SIZE 515 }, 516 { 517 // 518 // Minnow2 SPI type 519 // 520 SF_VENDOR_ID_NUMONYX, // VendorId 521 SF_DEVICE_ID0_N25Q064, // DeviceId 0 522 SF_DEVICE_ID1_N25Q064, // DeviceId 1 523 { 524 SF_INST_WREN, // Prefix Opcode 0: Write Enable 525 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR) 526 }, 527 { 528 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle20MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 529 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read 530 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle20MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 531 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle20MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 532 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 533 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 534 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle20MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 535 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle20MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 536 }, 537 538 // 539 // The offset of the start of the BIOS image in flash. This value is platform specific 540 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 541 // 542 ((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)), 543 544 // 545 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 546 // 547 FLASH_SIZE 548 }, 549 { 550 SF_VENDOR_ID_NUMONYX, // VendorId 551 SF_DEVICE_ID0_M25PXXX, // DeviceId 0 552 SF_DEVICE_ID1_M25PX16, // DeviceId 1 553 { 554 SF_INST_WREN, // Prefix Opcode 0: Write Enable 555 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR). 556 }, 557 { 558 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 559 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 560 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 561 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 562 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 563 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 564 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 565 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 566 }, 567 568 // 569 // The offset of the start of the BIOS image in flash. This value is platform specific 570 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 571 // 572 ((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE - FLASH_SIZE : (UINTN) (-1)), 573 574 // 575 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 576 // 577 FLASH_SIZE 578 }, 579 { 580 SF_VENDOR_ID_NUMONYX, // VendorId 581 SF_DEVICE_ID0_N25QXXX, // DeviceId 0 582 SF_DEVICE_ID1_N25Q032, // DeviceId 1 583 { 584 SF_INST_WREN, // Prefix Opcode 0: Write Enable 585 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR). 586 }, 587 { 588 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 589 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 590 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 591 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 592 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 593 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 594 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 595 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 596 }, 597 598 // 599 // The offset of the start of the BIOS image in flash. This value is platform specific 600 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 601 // 602 ((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE - FLASH_SIZE : (UINTN) (-1)), 603 604 // 605 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 606 // 607 FLASH_SIZE 608 }, 609 { 610 SF_VENDOR_ID_NUMONYX, // VendorId 611 SF_DEVICE_ID0_M25PXXX, // DeviceId 0 612 SF_DEVICE_ID1_M25PX32, // DeviceId 1 613 { 614 SF_INST_WREN, // Prefix Opcode 0: Write Enable 615 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR). 616 }, 617 { 618 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 619 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 620 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 621 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 622 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 623 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 624 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 625 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 626 }, 627 628 // 629 // The offset of the start of the BIOS image in flash. This value is platform specific 630 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 631 // 632 ((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE - FLASH_SIZE : (UINTN) (-1)), 633 634 // 635 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 636 // 637 FLASH_SIZE 638 }, 639 { 640 SF_VENDOR_ID_NUMONYX, // VendorId 641 SF_DEVICE_ID0_M25PXXX, // DeviceId 0 642 SF_DEVICE_ID1_M25PX64, // DeviceId 1 643 { 644 SF_INST_WREN, // Prefix Opcode 0: Write Enable 645 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR) 646 }, 647 { 648 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 649 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 650 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 651 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 652 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 653 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 654 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 655 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 656 }, 657 658 // 659 // The offset of the start of the BIOS image in flash. This value is platform specific 660 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 661 // 662 ((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE - FLASH_SIZE : (UINTN) (-1)), 663 664 // 665 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 666 // 667 FLASH_SIZE 668 }, 669 { 670 SF_VENDOR_ID_NUMONYX, // VendorId 671 SF_DEVICE_ID0_N25QXXX, // DeviceId 0 672 SF_DEVICE_ID1_N25Q128, // DeviceId 1 673 { 674 SF_INST_WREN, // Prefix Opcode 0: Write Enable 675 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR) 676 }, 677 { 678 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 679 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 680 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 681 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 682 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 683 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 684 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 685 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 686 }, 687 688 // 689 // The offset of the start of the BIOS image in flash. This value is platform specific 690 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 691 // 692 ((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)), 693 694 // 695 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 696 // 697 FLASH_SIZE 698 }, 699 { 700 SF_VENDOR_ID_EON, // VendorId 701 SF_DEVICE_ID0_EN25QXX, // DeviceId 0 702 SF_DEVICE_ID1_EN25Q16, // DeviceId 1 703 { 704 SF_INST_WREN, // Prefix Opcode 0: Write Enable 705 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR) 706 }, 707 { 708 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 709 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 710 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 711 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 712 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 713 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 714 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 715 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 716 }, 717 718 // 719 // The offset of the start of the BIOS image in flash. This value is platform specific 720 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 721 // 722 ((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)), 723 724 // 725 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 726 // 727 FLASH_SIZE 728 }, 729 { 730 SF_VENDOR_ID_EON, // VendorId 731 SF_DEVICE_ID0_EN25QXX, // DeviceId 0 732 SF_DEVICE_ID1_EN25Q32, // DeviceId 1 733 { 734 SF_INST_WREN, // Prefix Opcode 0: Write Enable 735 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR) 736 }, 737 { 738 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 739 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read 740 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 741 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 742 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 743 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 744 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 745 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 746 }, 747 748 // 749 // The offset of the start of the BIOS image in flash. This value is platform specific 750 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 751 // 752 ((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)), 753 754 // 755 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 756 // 757 FLASH_SIZE 758 }, 759 { 760 SF_VENDOR_ID_EON, // VendorId 761 SF_DEVICE_ID0_EN25QXX, // DeviceId 0 762 SF_DEVICE_ID1_EN25Q64, // DeviceId 1 763 { 764 SF_INST_WREN, // Prefix Opcode 0: Write Enable 765 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR). 766 }, 767 { 768 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 769 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 770 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 771 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 772 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 773 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 774 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 775 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 776 }, 777 778 // 779 // The offset of the start of the BIOS image in flash. This value is platform specific 780 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 781 // 782 ((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)), 783 784 // 785 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 786 // 787 FLASH_SIZE 788 }, 789 { 790 SF_VENDOR_ID_EON, // VendorId 791 SF_DEVICE_ID0_EN25QXX, // DeviceId 0 792 SF_DEVICE_ID1_EN25Q128, // DeviceId 1 793 { 794 SF_INST_WREN, // Prefix Opcode 0: Write Enable 795 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR) 796 }, 797 { 798 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 799 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 800 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 801 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 802 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 803 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 804 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 805 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 806 }, 807 808 // 809 // The offset of the start of the BIOS image in flash. This value is platform specific 810 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 811 // 812 ((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)), 813 814 // 815 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 816 // 817 FLASH_SIZE 818 }, 819 { 820 SF_VENDOR_ID_AMIC, // VendorId 821 SF_DEVICE_ID0_A25L016, // DeviceId 0 822 SF_DEVICE_ID1_A25L016, // DeviceId 1 823 { 824 SF_INST_WREN, // Prefix Opcode 0: Write Enable 825 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR) 826 }, 827 { 828 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID 829 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read 830 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register 831 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable 832 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB) 833 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB 834 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program 835 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register 836 }, 837 838 // 839 // The offset of the start of the BIOS image in flash. This value is platform specific 840 // and depends on the system flash map. If BIOS size is bigger than flash return -1. 841 // 842 ((AMIC_A25L16_SIZE >= FLASH_SIZE) ? AMIC_A25L16_SIZE - FLASH_SIZE : (UINTN) (-1)), 843 844 // 845 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map. 846 // 847 FLASH_SIZE 848 } 849 }; 850
