1 /* tc-m32r.c -- Assembler for the Renesas M32R. 2 Copyright (C) 1996-2014 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 19 Boston, MA 02110-1301, USA. */ 20 21 #include "as.h" 22 #include "safe-ctype.h" 23 #include "subsegs.h" 24 #include "symcat.h" 25 #include "opcodes/m32r-desc.h" 26 #include "opcodes/m32r-opc.h" 27 #include "cgen.h" 28 #include "elf/m32r.h" 29 30 /* Linked list of symbols that are debugging symbols to be defined as the 31 beginning of the current instruction. */ 32 typedef struct sym_link 33 { 34 struct sym_link *next; 35 symbolS *symbol; 36 } sym_linkS; 37 38 static sym_linkS *debug_sym_link = (sym_linkS *) 0; 39 40 /* Structure to hold all of the different components describing 41 an individual instruction. */ 42 typedef struct 43 { 44 const CGEN_INSN *insn; 45 const CGEN_INSN *orig_insn; 46 CGEN_FIELDS fields; 47 #if CGEN_INT_INSN_P 48 CGEN_INSN_INT buffer[1]; 49 #define INSN_VALUE(buf) (*(buf)) 50 #else 51 unsigned char buffer[CGEN_MAX_INSN_SIZE]; 52 #define INSN_VALUE(buf) (buf) 53 #endif 54 char *addr; 55 fragS *frag; 56 int num_fixups; 57 fixS *fixups[GAS_CGEN_MAX_FIXUPS]; 58 int indices[MAX_OPERAND_INSTANCES]; 59 sym_linkS *debug_sym_link; 60 } 61 m32r_insn; 62 63 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit 64 boundary (i.e. was the first of two 16 bit insns). */ 65 static m32r_insn prev_insn; 66 67 /* Non-zero if we've seen a relaxable insn since the last 32 bit 68 alignment request. */ 69 static int seen_relaxable_p = 0; 70 71 /* Non-zero if we are generating PIC code. */ 72 int pic_code; 73 74 /* Non-zero if -relax specified, in which case sufficient relocs are output 75 for the linker to do relaxing. 76 We do simple forms of relaxing internally, but they are always done. 77 This flag does not apply to them. */ 78 static int m32r_relax; 79 80 /* Non-zero if warn when a high/shigh reloc has no matching low reloc. 81 Each high/shigh reloc must be paired with it's low cousin in order to 82 properly calculate the addend in a relocatable link (since there is a 83 potential carry from the low to the high/shigh). 84 This option is off by default though for user-written assembler code it 85 might make sense to make the default be on (i.e. have gcc pass a flag 86 to turn it off). This warning must not be on for GCC created code as 87 optimization may delete the low but not the high/shigh (at least we 88 shouldn't assume or require it to). */ 89 static int warn_unmatched_high = 0; 90 91 /* 1 if -m32rx has been specified, in which case support for 92 the extended M32RX instruction set should be enabled. 93 2 if -m32r2 has been specified, in which case support for 94 the extended M32R2 instruction set should be enabled. */ 95 static int enable_m32rx = 0; /* Default to M32R. */ 96 97 /* Non-zero if -m32rx -hidden has been specified, in which case support for 98 the special M32RX instruction set should be enabled. */ 99 static int enable_special = 0; 100 101 /* Non-zero if -bitinst has been specified, in which case support 102 for extended M32R bit-field instruction set should be enabled. */ 103 static int enable_special_m32r = 1; 104 105 /* Non-zero if -float has been specified, in which case support for 106 extended M32R floating point instruction set should be enabled. */ 107 static int enable_special_float = 0; 108 109 /* Non-zero if the programmer should be warned when an explicit parallel 110 instruction might have constraint violations. */ 111 static int warn_explicit_parallel_conflicts = 1; 112 113 /* Non-zero if the programmer should not receive any messages about 114 parallel instruction with potential or real constraint violations. 115 The ability to suppress these messages is intended only for hardware 116 vendors testing the chip. It superceedes 117 warn_explicit_parallel_conflicts. */ 118 static int ignore_parallel_conflicts = 0; 119 120 /* Non-zero if insns can be made parallel. */ 121 static int use_parallel = 0; 122 123 /* Non-zero if optimizations should be performed. */ 124 static int optimize; 125 126 /* m32r er_flags. */ 127 static int m32r_flags = 0; 128 129 /* Stuff for .scomm symbols. */ 130 static segT sbss_section; 131 static asection scom_section; 132 static asymbol scom_symbol; 133 134 const char comment_chars[] = ";"; 135 const char line_comment_chars[] = "#"; 136 const char line_separator_chars[] = "!"; 137 const char EXP_CHARS[] = "eE"; 138 const char FLT_CHARS[] = "dD"; 139 140 /* Relocations against symbols are done in two 141 parts, with a HI relocation and a LO relocation. Each relocation 142 has only 16 bits of space to store an addend. This means that in 143 order for the linker to handle carries correctly, it must be able 144 to locate both the HI and the LO relocation. This means that the 145 relocations must appear in order in the relocation table. 146 147 In order to implement this, we keep track of each unmatched HI 148 relocation. We then sort them so that they immediately precede the 149 corresponding LO relocation. */ 150 151 struct m32r_hi_fixup 152 { 153 /* Next HI fixup. */ 154 struct m32r_hi_fixup *next; 155 156 /* This fixup. */ 157 fixS *fixp; 158 159 /* The section this fixup is in. */ 160 segT seg; 161 }; 162 163 /* The list of unmatched HI relocs. */ 164 165 static struct m32r_hi_fixup *m32r_hi_fixup_list; 166 167 struct 169 { 170 enum bfd_architecture bfd_mach; 171 int mach_flags; 172 } mach_table[] = 173 { 174 { bfd_mach_m32r, (1<<MACH_M32R) }, 175 { bfd_mach_m32rx, (1<<MACH_M32RX) }, 176 { bfd_mach_m32r2, (1<<MACH_M32R2) } 177 }; 178 179 static void 180 allow_m32rx (int on) 181 { 182 enable_m32rx = on; 183 184 if (stdoutput != NULL) 185 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach); 186 187 if (gas_cgen_cpu_desc != NULL) 188 gas_cgen_cpu_desc->machs = mach_table[on].mach_flags; 189 } 190 191 #define M32R_SHORTOPTS "O::K:" 193 194 const char *md_shortopts = M32R_SHORTOPTS; 195 196 enum md_option_enums 197 { 198 OPTION_M32R = OPTION_MD_BASE, 199 OPTION_M32RX, 200 OPTION_M32R2, 201 OPTION_BIG, 202 OPTION_LITTLE, 203 OPTION_PARALLEL, 204 OPTION_NO_PARALLEL, 205 OPTION_WARN_PARALLEL, 206 OPTION_NO_WARN_PARALLEL, 207 OPTION_IGNORE_PARALLEL, 208 OPTION_NO_IGNORE_PARALLEL, 209 OPTION_SPECIAL, 210 OPTION_SPECIAL_M32R, 211 OPTION_NO_SPECIAL_M32R, 212 OPTION_SPECIAL_FLOAT, 213 OPTION_WARN_UNMATCHED, 214 OPTION_NO_WARN_UNMATCHED 215 }; 216 217 struct option md_longopts[] = 218 { 219 {"m32r", no_argument, NULL, OPTION_M32R}, 220 {"m32rx", no_argument, NULL, OPTION_M32RX}, 221 {"m32r2", no_argument, NULL, OPTION_M32R2}, 222 {"big", no_argument, NULL, OPTION_BIG}, 223 {"little", no_argument, NULL, OPTION_LITTLE}, 224 {"EB", no_argument, NULL, OPTION_BIG}, 225 {"EL", no_argument, NULL, OPTION_LITTLE}, 226 {"parallel", no_argument, NULL, OPTION_PARALLEL}, 227 {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL}, 228 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, 229 {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, 230 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, 231 {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, 232 {"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL}, 233 {"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL}, 234 {"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, 235 {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, 236 {"hidden", no_argument, NULL, OPTION_SPECIAL}, 237 {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R}, 238 {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R}, 239 {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT}, 240 /* Sigh. I guess all warnings must now have both variants. */ 241 {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, 242 {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, 243 {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, 244 {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, 245 {NULL, no_argument, NULL, 0} 246 }; 247 248 size_t md_longopts_size = sizeof (md_longopts); 249 250 static void 251 little (int on) 252 { 253 target_big_endian = ! on; 254 } 255 256 /* Use parallel execution. */ 257 258 static int 259 parallel (void) 260 { 261 if (! enable_m32rx) 262 return 0; 263 264 if (use_parallel == 1) 265 return 1; 266 267 return 0; 268 } 269 270 int 271 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) 272 { 273 switch (c) 274 { 275 case 'O': 276 optimize = 1; 277 use_parallel = 1; 278 break; 279 280 case OPTION_M32R: 281 allow_m32rx (0); 282 break; 283 284 case OPTION_M32RX: 285 allow_m32rx (1); 286 break; 287 288 case OPTION_M32R2: 289 allow_m32rx (2); 290 enable_special = 1; 291 enable_special_m32r = 1; 292 break; 293 294 case OPTION_BIG: 295 target_big_endian = 1; 296 break; 297 298 case OPTION_LITTLE: 299 target_big_endian = 0; 300 break; 301 302 case OPTION_PARALLEL: 303 use_parallel = 1; 304 break; 305 306 case OPTION_NO_PARALLEL: 307 use_parallel = 0; 308 break; 309 310 case OPTION_WARN_PARALLEL: 311 warn_explicit_parallel_conflicts = 1; 312 break; 313 314 case OPTION_NO_WARN_PARALLEL: 315 warn_explicit_parallel_conflicts = 0; 316 break; 317 318 case OPTION_IGNORE_PARALLEL: 319 ignore_parallel_conflicts = 1; 320 break; 321 322 case OPTION_NO_IGNORE_PARALLEL: 323 ignore_parallel_conflicts = 0; 324 break; 325 326 case OPTION_SPECIAL: 327 if (enable_m32rx) 328 enable_special = 1; 329 else 330 { 331 /* Pretend that we do not recognise this option. */ 332 as_bad (_("Unrecognised option: -hidden")); 333 return 0; 334 } 335 break; 336 337 case OPTION_SPECIAL_M32R: 338 enable_special_m32r = 1; 339 break; 340 341 case OPTION_NO_SPECIAL_M32R: 342 enable_special_m32r = 0; 343 break; 344 345 case OPTION_SPECIAL_FLOAT: 346 enable_special_float = 1; 347 break; 348 349 case OPTION_WARN_UNMATCHED: 350 warn_unmatched_high = 1; 351 break; 352 353 case OPTION_NO_WARN_UNMATCHED: 354 warn_unmatched_high = 0; 355 break; 356 357 case 'K': 358 if (strcmp (arg, "PIC") != 0) 359 as_warn (_("Unrecognized option following -K")); 360 else 361 pic_code = 1; 362 break; 363 364 default: 365 return 0; 366 } 367 368 return 1; 369 } 370 371 void 372 md_show_usage (FILE *stream) 373 { 374 fprintf (stream, _(" M32R specific command line options:\n")); 375 376 fprintf (stream, _("\ 377 -m32r disable support for the m32rx instruction set\n")); 378 fprintf (stream, _("\ 379 -m32rx support the extended m32rx instruction set\n")); 380 fprintf (stream, _("\ 381 -m32r2 support the extended m32r2 instruction set\n")); 382 fprintf (stream, _("\ 383 -EL,-little produce little endian code and data\n")); 384 fprintf (stream, _("\ 385 -EB,-big produce big endian code and data\n")); 386 fprintf (stream, _("\ 387 -parallel try to combine instructions in parallel\n")); 388 fprintf (stream, _("\ 389 -no-parallel disable -parallel\n")); 390 fprintf (stream, _("\ 391 -no-bitinst disallow the M32R2's extended bit-field instructions\n")); 392 fprintf (stream, _("\ 393 -O try to optimize code. Implies -parallel\n")); 394 395 fprintf (stream, _("\ 396 -warn-explicit-parallel-conflicts warn when parallel instructions\n")); 397 fprintf (stream, _("\ 398 might violate contraints\n")); 399 fprintf (stream, _("\ 400 -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); 401 fprintf (stream, _("\ 402 instructions might violate contraints\n")); 403 fprintf (stream, _("\ 404 -Wp synonym for -warn-explicit-parallel-conflicts\n")); 405 fprintf (stream, _("\ 406 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); 407 fprintf (stream, _("\ 408 -ignore-parallel-conflicts do not check parallel instructions\n")); 409 fprintf (stream, _("\ 410 for constraint violations\n")); 411 fprintf (stream, _("\ 412 -no-ignore-parallel-conflicts check parallel instructions for\n")); 413 fprintf (stream, _("\ 414 constraint violations\n")); 415 fprintf (stream, _("\ 416 -Ip synonym for -ignore-parallel-conflicts\n")); 417 fprintf (stream, _("\ 418 -nIp synonym for -no-ignore-parallel-conflicts\n")); 419 420 fprintf (stream, _("\ 421 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); 422 fprintf (stream, _("\ 423 -no-warn-unmatched-high do not warn about missing low relocs\n")); 424 fprintf (stream, _("\ 425 -Wuh synonym for -warn-unmatched-high\n")); 426 fprintf (stream, _("\ 427 -Wnuh synonym for -no-warn-unmatched-high\n")); 428 429 fprintf (stream, _("\ 430 -KPIC generate PIC\n")); 431 } 432 433 /* Set by md_assemble for use by m32r_fill_insn. */ 434 static subsegT prev_subseg; 435 static segT prev_seg; 436 437 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 438 symbolS * GOT_symbol; 439 440 static inline int 441 m32r_PIC_related_p (symbolS *sym) 442 { 443 expressionS *exp; 444 445 if (! sym) 446 return 0; 447 448 if (sym == GOT_symbol) 449 return 1; 450 451 exp = symbol_get_value_expression (sym); 452 453 return (exp->X_op == O_PIC_reloc 454 || exp->X_md == BFD_RELOC_M32R_26_PLTREL 455 || m32r_PIC_related_p (exp->X_add_symbol) 456 || m32r_PIC_related_p (exp->X_op_symbol)); 457 } 458 459 static inline int 460 m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p) 461 { 462 expressionS *exp = main_exp; 463 464 if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol)) 465 return 1; 466 467 if (exp->X_op == O_symbol && exp->X_add_symbol) 468 { 469 if (exp->X_add_symbol == GOT_symbol) 470 { 471 *r_type_p = BFD_RELOC_M32R_GOTPC24; 472 return 0; 473 } 474 } 475 else if (exp->X_op == O_add) 476 { 477 exp = symbol_get_value_expression (exp->X_add_symbol); 478 if (! exp) 479 return 0; 480 } 481 482 if (exp->X_op == O_PIC_reloc) 483 { 484 *r_type_p = exp->X_md; 485 if (exp == main_exp) 486 exp->X_op = O_symbol; 487 else 488 { 489 main_exp->X_add_symbol = exp->X_add_symbol; 490 main_exp->X_add_number += exp->X_add_number; 491 } 492 } 493 else 494 return (m32r_PIC_related_p (exp->X_add_symbol) 495 || m32r_PIC_related_p (exp->X_op_symbol)); 496 497 return 0; 498 } 499 500 /* FIXME: Should be machine generated. */ 501 #define NOP_INSN 0x7000 502 #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ 503 504 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents 505 of an rs_align_code fragment. */ 506 507 void 508 m32r_handle_align (fragS *fragp) 509 { 510 static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; 511 static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; 512 513 int bytes, fix; 514 char *p; 515 516 if (fragp->fr_type != rs_align_code) 517 return; 518 519 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 520 p = fragp->fr_literal + fragp->fr_fix; 521 fix = 0; 522 523 if (bytes & 1) 524 { 525 fix = 1; 526 *p++ = 0; 527 bytes--; 528 } 529 530 if (bytes & 2) 531 { 532 memcpy (p, nop_pattern, 2); 533 p += 2; 534 bytes -= 2; 535 fix += 2; 536 } 537 538 memcpy (p, multi_nop_pattern, 4); 539 540 fragp->fr_fix += fix; 541 fragp->fr_var = 4; 542 } 543 544 /* If the last instruction was the first of 2 16 bit insns, 545 output a nop to move the PC to a 32 bit boundary. 546 547 This is done via an alignment specification since branch relaxing 548 may make it unnecessary. 549 550 Internally, we need to output one of these each time a 32 bit insn is 551 seen after an insn that is relaxable. */ 552 553 static void 554 fill_insn (int ignore ATTRIBUTE_UNUSED) 555 { 556 frag_align_code (2, 0); 557 prev_insn.insn = NULL; 558 seen_relaxable_p = 0; 559 } 560 561 /* Record the symbol so that when we output the insn, we can create 562 a symbol that is at the start of the instruction. This is used 563 to emit the label for the start of a breakpoint without causing 564 the assembler to emit a NOP if the previous instruction was a 565 16 bit instruction. */ 566 567 static void 568 debug_sym (int ignore ATTRIBUTE_UNUSED) 569 { 570 char *name; 571 char delim; 572 char *end_name; 573 symbolS *symbolP; 574 sym_linkS *lnk; 575 576 name = input_line_pointer; 577 delim = get_symbol_end (); 578 end_name = input_line_pointer; 579 580 if ((symbolP = symbol_find (name)) == NULL 581 && (symbolP = md_undefined_symbol (name)) == NULL) 582 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); 583 584 symbol_table_insert (symbolP); 585 if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section 586 || S_IS_EXTERNAL (symbolP) 587 || S_IS_WEAK (symbolP))) 588 /* xgettext:c-format */ 589 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); 590 591 else 592 { 593 lnk = (sym_linkS *) xmalloc (sizeof (sym_linkS)); 594 lnk->symbol = symbolP; 595 lnk->next = debug_sym_link; 596 debug_sym_link = lnk; 597 symbol_get_obj (symbolP)->local = 1; 598 } 599 600 *end_name = delim; 601 demand_empty_rest_of_line (); 602 } 603 604 /* Second pass to expanding the debug symbols, go through linked 605 list of symbols and reassign the address. */ 606 607 static void 608 expand_debug_syms (sym_linkS *syms, int align) 609 { 610 char *save_input_line = input_line_pointer; 611 sym_linkS *next_syms; 612 613 if (!syms) 614 return; 615 616 (void) frag_align_code (align, 0); 617 for (; syms != (sym_linkS *) 0; syms = next_syms) 618 { 619 symbolS *symbolP = syms->symbol; 620 next_syms = syms->next; 621 input_line_pointer = ".\n"; 622 pseudo_set (symbolP); 623 free ((char *) syms); 624 } 625 626 input_line_pointer = save_input_line; 627 } 628 629 void 630 m32r_flush_pending_output (void) 631 { 632 if (debug_sym_link) 633 { 634 expand_debug_syms (debug_sym_link, 1); 635 debug_sym_link = (sym_linkS *) 0; 636 } 637 } 638 639 /* Cover function to fill_insn called after a label and at end of assembly. 640 The result is always 1: we're called in a conditional to see if the 641 current line is a label. */ 642 643 int 644 m32r_fill_insn (int done) 645 { 646 if (prev_seg != NULL) 647 { 648 segT seg = now_seg; 649 subsegT subseg = now_subseg; 650 651 subseg_set (prev_seg, prev_subseg); 652 653 fill_insn (0); 654 655 subseg_set (seg, subseg); 656 } 657 658 if (done && debug_sym_link) 659 { 660 expand_debug_syms (debug_sym_link, 1); 661 debug_sym_link = (sym_linkS *) 0; 662 } 663 664 return 1; 665 } 666 667 /* The default target format to use. */ 669 670 const char * 671 m32r_target_format (void) 672 { 673 #ifdef TE_LINUX 674 if (target_big_endian) 675 return "elf32-m32r-linux"; 676 else 677 return "elf32-m32rle-linux"; 678 #else 679 if (target_big_endian) 680 return "elf32-m32r"; 681 else 682 return "elf32-m32rle"; 683 #endif 684 } 685 686 void 687 md_begin (void) 688 { 689 flagword applicable; 690 segT seg; 691 subsegT subseg; 692 693 /* Initialize the `cgen' interface. */ 694 695 /* Set the machine number and endian. */ 696 gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, 697 CGEN_CPU_OPEN_ENDIAN, 698 (target_big_endian ? 699 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE), 700 CGEN_CPU_OPEN_END); 701 m32r_cgen_init_asm (gas_cgen_cpu_desc); 702 703 /* The operand instance table is used during optimization to determine 704 which insns can be executed in parallel. It is also used to give 705 warnings regarding operand interference in parallel insns. */ 706 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); 707 708 /* This is a callback from cgen to gas to parse operands. */ 709 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); 710 711 /* Save the current subseg so we can restore it [it's the default one and 712 we don't want the initial section to be .sbss]. */ 713 seg = now_seg; 714 subseg = now_subseg; 715 716 /* The sbss section is for local .scomm symbols. */ 717 sbss_section = subseg_new (".sbss", 0); 718 seg_info (sbss_section)->bss = 1; 719 720 /* This is copied from perform_an_assembly_pass. */ 721 applicable = bfd_applicable_section_flags (stdoutput); 722 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); 723 724 subseg_set (seg, subseg); 725 726 /* We must construct a fake section similar to bfd_com_section 727 but with the name .scommon. */ 728 scom_section = *bfd_com_section_ptr; 729 scom_section.name = ".scommon"; 730 scom_section.output_section = & scom_section; 731 scom_section.symbol = & scom_symbol; 732 scom_section.symbol_ptr_ptr = & scom_section.symbol; 733 scom_symbol = * bfd_com_section_ptr->symbol; 734 scom_symbol.name = ".scommon"; 735 scom_symbol.section = & scom_section; 736 737 allow_m32rx (enable_m32rx); 738 739 gas_cgen_initialize_saved_fixups_array (); 740 } 741 742 #define OPERAND_IS_COND_BIT(operand, indices, index) \ 743 ((operand)->hw_type == HW_H_COND \ 744 || ((operand)->hw_type == HW_H_PSW) \ 745 || ((operand)->hw_type == HW_H_CR \ 746 && (indices [index] == 0 || indices [index] == 1))) 747 748 /* Returns true if an output of instruction 'a' is referenced by an operand 749 of instruction 'b'. If 'check_outputs' is true then b's outputs are 750 checked, otherwise its inputs are examined. */ 751 752 static int 753 first_writes_to_seconds_operands (m32r_insn *a, 754 m32r_insn *b, 755 const int check_outputs) 756 { 757 const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); 758 const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); 759 int a_index; 760 761 if (ignore_parallel_conflicts) 762 return 0; 763 764 /* If at least one of the instructions takes no operands, then there is 765 nothing to check. There really are instructions without operands, 766 eg 'nop'. */ 767 if (a_operands == NULL || b_ops == NULL) 768 return 0; 769 770 /* Scan the operand list of 'a' looking for an output operand. */ 771 for (a_index = 0; 772 a_operands->type != CGEN_OPINST_END; 773 a_index ++, a_operands ++) 774 { 775 if (a_operands->type == CGEN_OPINST_OUTPUT) 776 { 777 int b_index; 778 const CGEN_OPINST *b_operands = b_ops; 779 780 /* Special Case: 781 The Condition bit 'C' is a shadow of the CBR register (control 782 register 1) and also a shadow of bit 31 of the program status 783 word (control register 0). For now this is handled here, rather 784 than by cgen.... */ 785 786 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) 787 { 788 /* Scan operand list of 'b' looking for another reference to the 789 condition bit, which goes in the right direction. */ 790 for (b_index = 0; 791 b_operands->type != CGEN_OPINST_END; 792 b_index++, b_operands++) 793 { 794 if ((b_operands->type 795 == (check_outputs 796 ? CGEN_OPINST_OUTPUT 797 : CGEN_OPINST_INPUT)) 798 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) 799 return 1; 800 } 801 } 802 else 803 { 804 /* Scan operand list of 'b' looking for an operand that 805 references the same hardware element, and which goes in the 806 right direction. */ 807 for (b_index = 0; 808 b_operands->type != CGEN_OPINST_END; 809 b_index++, b_operands++) 810 { 811 if ((b_operands->type 812 == (check_outputs 813 ? CGEN_OPINST_OUTPUT 814 : CGEN_OPINST_INPUT)) 815 && (b_operands->hw_type == a_operands->hw_type) 816 && (a->indices[a_index] == b->indices[b_index])) 817 return 1; 818 } 819 } 820 } 821 } 822 823 return 0; 824 } 825 826 /* Returns true if the insn can (potentially) alter the program counter. */ 827 828 static int 829 writes_to_pc (m32r_insn *a) 830 { 831 if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) 832 || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) 833 return 1; 834 return 0; 835 } 836 837 /* Return NULL if the two 16 bit insns can be executed in parallel. 838 Otherwise return a pointer to an error message explaining why not. */ 839 840 static const char * 841 can_make_parallel (m32r_insn *a, m32r_insn *b) 842 { 843 PIPE_ATTR a_pipe; 844 PIPE_ATTR b_pipe; 845 846 /* Make sure the instructions are the right length. */ 847 if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 848 || CGEN_FIELDS_BITSIZE (&b->fields) != 16) 849 abort (); 850 851 if (first_writes_to_seconds_operands (a, b, TRUE)) 852 return _("instructions write to the same destination register."); 853 854 a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); 855 b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); 856 857 /* Make sure that the instructions use the correct execution pipelines. */ 858 if (a_pipe == PIPE_NONE 859 || b_pipe == PIPE_NONE) 860 return _("Instructions do not use parallel execution pipelines."); 861 862 /* Leave this test for last, since it is the only test that can 863 go away if the instructions are swapped, and we want to make 864 sure that any other errors are detected before this happens. */ 865 if (a_pipe == PIPE_S 866 || b_pipe == PIPE_O 867 || (b_pipe == PIPE_O_OS && (enable_m32rx != 2))) 868 return _("Instructions share the same execution pipeline"); 869 870 return NULL; 871 } 872 873 /* Force the top bit of the second 16-bit insn to be set. */ 874 875 static void 876 make_parallel (CGEN_INSN_BYTES_PTR buffer) 877 { 878 #if CGEN_INT_INSN_P 879 *buffer |= 0x8000; 880 #else 881 buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] 882 |= 0x80; 883 #endif 884 } 885 886 /* Same as make_parallel except buffer contains the bytes in target order. */ 887 888 static void 889 target_make_parallel (char *buffer) 890 { 891 buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] 892 |= 0x80; 893 } 894 895 /* Assemble two instructions with an explicit parallel operation (||) or 896 sequential operation (->). */ 897 898 static void 899 assemble_two_insns (char *str1, char *str2, int parallel_p) 900 { 901 char *str3; 902 m32r_insn first; 903 m32r_insn second; 904 char *errmsg; 905 char save_str2 = *str2; 906 907 /* Separate the two instructions. */ 908 *str2 = 0; 909 910 /* Make sure the two insns begin on a 32 bit boundary. 911 This is also done for the serial case (foo -> bar), relaxing doesn't 912 affect insns written like this. 913 Note that we must always do this as we can't assume anything about 914 whether we're currently on a 32 bit boundary or not. Relaxing may 915 change this. */ 916 fill_insn (0); 917 918 first.debug_sym_link = debug_sym_link; 919 debug_sym_link = (sym_linkS *) 0; 920 921 /* Parse the first instruction. */ 922 if (! (first.insn = m32r_cgen_assemble_insn 923 (gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg))) 924 { 925 as_bad ("%s", errmsg); 926 return; 927 } 928 929 /* Check it. */ 930 if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) 931 { 932 /* xgettext:c-format */ 933 as_bad (_("not a 16 bit instruction '%s'"), str1); 934 return; 935 } 936 #ifdef E_M32R2_ARCH 937 else if ((enable_m32rx == 1) 938 /* FIXME: Need standard macro to perform this test. */ 939 && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) 940 & (1 << MACH_M32R2)) 941 && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) 942 & (1 << MACH_M32RX))))) 943 { 944 /* xgettext:c-format */ 945 as_bad (_("instruction '%s' is for the M32R2 only"), str1); 946 return; 947 } 948 else if ((! enable_special 949 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) 950 || (! enable_special_m32r 951 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R))) 952 #else 953 else if (! enable_special 954 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) 955 #endif 956 { 957 /* xgettext:c-format */ 958 as_bad (_("unknown instruction '%s'"), str1); 959 return; 960 } 961 else if (! enable_m32rx 962 /* FIXME: Need standard macro to perform this test. */ 963 && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) 964 == (1 << MACH_M32RX))) 965 { 966 /* xgettext:c-format */ 967 as_bad (_("instruction '%s' is for the M32RX only"), str1); 968 return; 969 } 970 971 /* Check to see if this is an allowable parallel insn. */ 972 if (parallel_p 973 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) 974 { 975 /* xgettext:c-format */ 976 as_bad (_("instruction '%s' cannot be executed in parallel."), str1); 977 return; 978 } 979 980 /* Restore the original assembly text, just in case it is needed. */ 981 *str2 = save_str2; 982 983 /* Save the original string pointer. */ 984 str3 = str1; 985 986 /* Advanced past the parsed string. */ 987 str1 = str2 + 2; 988 989 /* Remember the entire string in case it is needed for error 990 messages. */ 991 str2 = str3; 992 993 /* Convert the opcode to lower case. */ 994 { 995 char *s2 = str1; 996 997 while (ISSPACE (*s2++)) 998 continue; 999 1000 --s2; 1001 1002 while (ISALNUM (*s2)) 1003 { 1004 *s2 = TOLOWER (*s2); 1005 s2++; 1006 } 1007 } 1008 1009 /* Preserve any fixups that have been generated and reset the list 1010 to empty. */ 1011 gas_cgen_save_fixups (0); 1012 1013 /* Get the indices of the operands of the instruction. */ 1014 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact 1015 doesn't seem right. Perhaps allow passing fields like we do insn. */ 1016 /* FIXME: ALIAS insns do not have operands, so we use this function 1017 to find the equivalent insn and overwrite the value stored in our 1018 structure. We still need the original insn, however, since this 1019 may have certain attributes that are not present in the unaliased 1020 version (eg relaxability). When aliases behave differently this 1021 may have to change. */ 1022 first.orig_insn = first.insn; 1023 { 1024 CGEN_FIELDS tmp_fields; 1025 first.insn = cgen_lookup_get_insn_operands 1026 (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, 1027 first.indices, &tmp_fields); 1028 } 1029 1030 if (first.insn == NULL) 1031 as_fatal (_("internal error: lookup/get operands failed")); 1032 1033 second.debug_sym_link = NULL; 1034 1035 /* Parse the second instruction. */ 1036 if (! (second.insn = m32r_cgen_assemble_insn 1037 (gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg))) 1038 { 1039 as_bad ("%s", errmsg); 1040 return; 1041 } 1042 1043 /* Check it. */ 1044 if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) 1045 { 1046 /* xgettext:c-format */ 1047 as_bad (_("not a 16 bit instruction '%s'"), str1); 1048 return; 1049 } 1050 #ifdef E_M32R2_ARCH 1051 else if ((enable_m32rx == 1) 1052 /* FIXME: Need standard macro to perform this test. */ 1053 && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) 1054 & (1 << MACH_M32R2)) 1055 && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) 1056 & (1 << MACH_M32RX))))) 1057 { 1058 /* xgettext:c-format */ 1059 as_bad (_("instruction '%s' is for the M32R2 only"), str1); 1060 return; 1061 } 1062 else if ((! enable_special 1063 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) 1064 || (! enable_special_m32r 1065 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))) 1066 #else 1067 else if (! enable_special 1068 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) 1069 #endif 1070 { 1071 /* xgettext:c-format */ 1072 as_bad (_("unknown instruction '%s'"), str1); 1073 return; 1074 } 1075 else if (! enable_m32rx 1076 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) 1077 { 1078 /* xgettext:c-format */ 1079 as_bad (_("instruction '%s' is for the M32RX only"), str1); 1080 return; 1081 } 1082 1083 /* Check to see if this is an allowable parallel insn. */ 1084 if (parallel_p 1085 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) 1086 { 1087 /* xgettext:c-format */ 1088 as_bad (_("instruction '%s' cannot be executed in parallel."), str1); 1089 return; 1090 } 1091 1092 if (parallel_p && ! enable_m32rx) 1093 { 1094 if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP 1095 && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) 1096 { 1097 /* xgettext:c-format */ 1098 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); 1099 return; 1100 } 1101 } 1102 1103 /* Get the indices of the operands of the instruction. */ 1104 second.orig_insn = second.insn; 1105 { 1106 CGEN_FIELDS tmp_fields; 1107 second.insn = cgen_lookup_get_insn_operands 1108 (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, 1109 second.indices, &tmp_fields); 1110 } 1111 1112 if (second.insn == NULL) 1113 as_fatal (_("internal error: lookup/get operands failed")); 1114 1115 /* We assume that if the first instruction writes to a register that is 1116 read by the second instruction it is because the programmer intended 1117 this to happen, (after all they have explicitly requested that these 1118 two instructions be executed in parallel). Although if the global 1119 variable warn_explicit_parallel_conflicts is true then we do generate 1120 a warning message. Similarly we assume that parallel branch and jump 1121 instructions are deliberate and should not produce errors. */ 1122 1123 if (parallel_p && warn_explicit_parallel_conflicts) 1124 { 1125 if (first_writes_to_seconds_operands (&first, &second, FALSE)) 1126 /* xgettext:c-format */ 1127 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); 1128 1129 if (first_writes_to_seconds_operands (&second, &first, FALSE)) 1130 /* xgettext:c-format */ 1131 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); 1132 } 1133 1134 if (!parallel_p 1135 || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) 1136 { 1137 /* Get the fixups for the first instruction. */ 1138 gas_cgen_swap_fixups (0); 1139 1140 /* Write it out. */ 1141 expand_debug_syms (first.debug_sym_link, 1); 1142 gas_cgen_finish_insn (first.orig_insn, first.buffer, 1143 CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); 1144 1145 /* Force the top bit of the second insn to be set. */ 1146 if (parallel_p) 1147 make_parallel (second.buffer); 1148 1149 /* Get its fixups. */ 1150 gas_cgen_restore_fixups (0); 1151 1152 /* Write it out. */ 1153 expand_debug_syms (second.debug_sym_link, 1); 1154 gas_cgen_finish_insn (second.orig_insn, second.buffer, 1155 CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); 1156 } 1157 /* Try swapping the instructions to see if they work that way. */ 1158 else if (can_make_parallel (&second, &first) == NULL) 1159 { 1160 /* Write out the second instruction first. */ 1161 expand_debug_syms (second.debug_sym_link, 1); 1162 gas_cgen_finish_insn (second.orig_insn, second.buffer, 1163 CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); 1164 1165 /* Force the top bit of the first instruction to be set. */ 1166 make_parallel (first.buffer); 1167 1168 /* Get the fixups for the first instruction. */ 1169 gas_cgen_restore_fixups (0); 1170 1171 /* Write out the first instruction. */ 1172 expand_debug_syms (first.debug_sym_link, 1); 1173 gas_cgen_finish_insn (first.orig_insn, first.buffer, 1174 CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); 1175 } 1176 else 1177 { 1178 as_bad ("'%s': %s", str2, errmsg); 1179 return; 1180 } 1181 1182 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL) 1183 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) 1184 m32r_flags |= E_M32R_HAS_HIDDEN_INST; 1185 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R) 1186 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)) 1187 m32r_flags |= E_M32R_HAS_BIT_INST; 1188 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT) 1189 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT)) 1190 m32r_flags |= E_M32R_HAS_FLOAT_INST; 1191 1192 /* Set these so m32r_fill_insn can use them. */ 1193 prev_seg = now_seg; 1194 prev_subseg = now_subseg; 1195 } 1196 1197 void 1198 md_assemble (char *str) 1199 { 1200 m32r_insn insn; 1201 char *errmsg; 1202 char *str2 = NULL; 1203 1204 /* Initialize GAS's cgen interface for a new instruction. */ 1205 gas_cgen_init_parse (); 1206 1207 /* Look for a parallel instruction separator. */ 1208 if ((str2 = strstr (str, "||")) != NULL) 1209 { 1210 assemble_two_insns (str, str2, 1); 1211 m32r_flags |= E_M32R_HAS_PARALLEL; 1212 return; 1213 } 1214 1215 /* Also look for a sequential instruction separator. */ 1216 if ((str2 = strstr (str, "->")) != NULL) 1217 { 1218 assemble_two_insns (str, str2, 0); 1219 return; 1220 } 1221 1222 insn.debug_sym_link = debug_sym_link; 1223 debug_sym_link = (sym_linkS *) 0; 1224 1225 insn.insn = m32r_cgen_assemble_insn 1226 (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); 1227 1228 if (!insn.insn) 1229 { 1230 as_bad ("%s", errmsg); 1231 return; 1232 } 1233 1234 #ifdef E_M32R2_ARCH 1235 if ((enable_m32rx == 1) 1236 /* FIXME: Need standard macro to perform this test. */ 1237 && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) 1238 & (1 << MACH_M32R2)) 1239 && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) 1240 & (1 << MACH_M32RX))))) 1241 { 1242 /* xgettext:c-format */ 1243 as_bad (_("instruction '%s' is for the M32R2 only"), str); 1244 return; 1245 } 1246 else if ((! enable_special 1247 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) 1248 || (! enable_special_m32r 1249 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))) 1250 #else 1251 if (! enable_special 1252 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) 1253 #endif 1254 { 1255 /* xgettext:c-format */ 1256 as_bad (_("unknown instruction '%s'"), str); 1257 return; 1258 } 1259 else if (! enable_m32rx 1260 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) 1261 { 1262 /* xgettext:c-format */ 1263 as_bad (_("instruction '%s' is for the M32RX only"), str); 1264 return; 1265 } 1266 1267 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) 1268 m32r_flags |= E_M32R_HAS_HIDDEN_INST; 1269 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)) 1270 m32r_flags |= E_M32R_HAS_BIT_INST; 1271 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT)) 1272 m32r_flags |= E_M32R_HAS_FLOAT_INST; 1273 1274 if (CGEN_INSN_BITSIZE (insn.insn) == 32) 1275 { 1276 /* 32 bit insns must live on 32 bit boundaries. */ 1277 if (prev_insn.insn || seen_relaxable_p) 1278 { 1279 /* ??? If calling fill_insn too many times turns us into a memory 1280 pig, can we call a fn to assemble a nop instead of 1281 !seen_relaxable_p? */ 1282 fill_insn (0); 1283 } 1284 1285 expand_debug_syms (insn.debug_sym_link, 2); 1286 1287 /* Doesn't really matter what we pass for RELAX_P here. */ 1288 gas_cgen_finish_insn (insn.insn, insn.buffer, 1289 CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); 1290 } 1291 else 1292 { 1293 int on_32bit_boundary_p; 1294 int swap = FALSE; 1295 1296 if (CGEN_INSN_BITSIZE (insn.insn) != 16) 1297 abort (); 1298 1299 insn.orig_insn = insn.insn; 1300 1301 /* If the previous insn was relaxable, then it may be expanded 1302 to fill the current 16 bit slot. Emit a NOP here to occupy 1303 this slot, so that we can start at optimizing at a 32 bit 1304 boundary. */ 1305 if (prev_insn.insn && seen_relaxable_p && optimize) 1306 fill_insn (0); 1307 1308 if (enable_m32rx) 1309 { 1310 /* Get the indices of the operands of the instruction. 1311 FIXME: See assemble_parallel for notes on orig_insn. */ 1312 { 1313 CGEN_FIELDS tmp_fields; 1314 insn.insn = cgen_lookup_get_insn_operands 1315 (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, 1316 16, insn.indices, &tmp_fields); 1317 } 1318 1319 if (insn.insn == NULL) 1320 as_fatal (_("internal error: lookup/get operands failed")); 1321 } 1322 1323 /* Compute whether we're on a 32 bit boundary or not. 1324 prev_insn.insn is NULL when we're on a 32 bit boundary. */ 1325 on_32bit_boundary_p = prev_insn.insn == NULL; 1326 1327 /* Change a frag to, if each insn to swap is in a different frag. 1328 It must keep only one instruction in a frag. */ 1329 if (parallel() && on_32bit_boundary_p) 1330 { 1331 frag_wane (frag_now); 1332 frag_new (0); 1333 } 1334 1335 /* Look to see if this instruction can be combined with the 1336 previous instruction to make one, parallel, 32 bit instruction. 1337 If the previous instruction (potentially) changed the flow of 1338 program control, then it cannot be combined with the current 1339 instruction. If the current instruction is relaxable, then it 1340 might be replaced with a longer version, so we cannot combine it. 1341 Also if the output of the previous instruction is used as an 1342 input to the current instruction then it cannot be combined. 1343 Otherwise call can_make_parallel() with both orderings of the 1344 instructions to see if they can be combined. */ 1345 if (! on_32bit_boundary_p 1346 && parallel () 1347 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 1348 && ! writes_to_pc (&prev_insn) 1349 && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE)) 1350 { 1351 if (can_make_parallel (&prev_insn, &insn) == NULL) 1352 make_parallel (insn.buffer); 1353 else if (can_make_parallel (&insn, &prev_insn) == NULL) 1354 swap = TRUE; 1355 } 1356 1357 expand_debug_syms (insn.debug_sym_link, 1); 1358 1359 { 1360 int i; 1361 finished_insnS fi; 1362 1363 /* Ensure each pair of 16 bit insns is in the same frag. */ 1364 frag_grow (4); 1365 1366 gas_cgen_finish_insn (insn.orig_insn, insn.buffer, 1367 CGEN_FIELDS_BITSIZE (&insn.fields), 1368 1 /* relax_p */, &fi); 1369 insn.addr = fi.addr; 1370 insn.frag = fi.frag; 1371 insn.num_fixups = fi.num_fixups; 1372 for (i = 0; i < fi.num_fixups; ++i) 1373 insn.fixups[i] = fi.fixups[i]; 1374 } 1375 1376 if (swap) 1377 { 1378 int i, tmp; 1379 1380 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp 1381 1382 /* Swap the two insns */ 1383 SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); 1384 SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); 1385 1386 target_make_parallel (insn.addr); 1387 1388 /* Swap any relaxable frags recorded for the two insns. */ 1389 /* FIXME: Clarify. relaxation precludes parallel insns */ 1390 if (prev_insn.frag->fr_opcode == prev_insn.addr) 1391 prev_insn.frag->fr_opcode = insn.addr; 1392 else if (insn.frag->fr_opcode == insn.addr) 1393 insn.frag->fr_opcode = prev_insn.addr; 1394 1395 /* Change a frag to, if each insn is in a different frag. 1396 It must keep only one instruction in a frag. */ 1397 if (prev_insn.frag != insn.frag) 1398 { 1399 for (i = 0; i < prev_insn.num_fixups; ++i) 1400 prev_insn.fixups[i]->fx_frag = insn.frag; 1401 for (i = 0; i < insn.num_fixups; ++i) 1402 insn.fixups[i]->fx_frag = prev_insn.frag; 1403 } 1404 else 1405 { 1406 /* Update the addresses in any fixups. 1407 Note that we don't have to handle the case where each insn is in 1408 a different frag as we ensure they're in the same frag above. */ 1409 for (i = 0; i < prev_insn.num_fixups; ++i) 1410 prev_insn.fixups[i]->fx_where += 2; 1411 for (i = 0; i < insn.num_fixups; ++i) 1412 insn.fixups[i]->fx_where -= 2; 1413 } 1414 } 1415 1416 /* Keep track of whether we've seen a pair of 16 bit insns. 1417 prev_insn.insn is NULL when we're on a 32 bit boundary. */ 1418 if (on_32bit_boundary_p) 1419 prev_insn = insn; 1420 else 1421 prev_insn.insn = NULL; 1422 1423 /* If the insn needs the following one to be on a 32 bit boundary 1424 (e.g. subroutine calls), fill this insn's slot. */ 1425 if (on_32bit_boundary_p 1426 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) 1427 fill_insn (0); 1428 1429 /* If this is a relaxable insn (can be replaced with a larger version) 1430 mark the fact so that we can emit an alignment directive for a 1431 following 32 bit insn if we see one. */ 1432 if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) 1433 seen_relaxable_p = 1; 1434 } 1435 1436 /* Set these so m32r_fill_insn can use them. */ 1437 prev_seg = now_seg; 1438 prev_subseg = now_subseg; 1439 } 1440 1441 /* The syntax in the manual says constants begin with '#'. 1442 We just ignore it. */ 1443 1444 void 1445 md_operand (expressionS *expressionP) 1446 { 1447 if (*input_line_pointer == '#') 1448 { 1449 input_line_pointer++; 1450 expression (expressionP); 1451 } 1452 } 1453 1454 valueT 1455 md_section_align (segT segment, valueT size) 1456 { 1457 int align = bfd_get_section_alignment (stdoutput, segment); 1458 1459 return ((size + (1 << align) - 1) & (-1 << align)); 1460 } 1461 1462 symbolS * 1463 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 1464 { 1465 return 0; 1466 } 1467 1468 /* .scomm pseudo-op handler. 1470 1471 This is a new pseudo-op to handle putting objects in .scommon. 1472 By doing this the linker won't need to do any work, 1473 and more importantly it removes the implicit -G arg necessary to 1474 correctly link the object file. */ 1475 1476 static void 1477 m32r_scomm (int ignore ATTRIBUTE_UNUSED) 1478 { 1479 char *name; 1480 char c; 1481 char *p; 1482 offsetT size; 1483 symbolS *symbolP; 1484 offsetT align; 1485 int align2; 1486 1487 name = input_line_pointer; 1488 c = get_symbol_end (); 1489 1490 /* Just after name is now '\0'. */ 1491 p = input_line_pointer; 1492 *p = c; 1493 SKIP_WHITESPACE (); 1494 if (*input_line_pointer != ',') 1495 { 1496 as_bad (_("Expected comma after symbol-name: rest of line ignored.")); 1497 ignore_rest_of_line (); 1498 return; 1499 } 1500 1501 /* Skip ','. */ 1502 input_line_pointer++; 1503 if ((size = get_absolute_expression ()) < 0) 1504 { 1505 /* xgettext:c-format */ 1506 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); 1507 ignore_rest_of_line (); 1508 return; 1509 } 1510 1511 /* The third argument to .scomm is the alignment. */ 1512 if (*input_line_pointer != ',') 1513 align = 8; 1514 else 1515 { 1516 ++input_line_pointer; 1517 align = get_absolute_expression (); 1518 if (align <= 0) 1519 { 1520 as_warn (_("ignoring bad alignment")); 1521 align = 8; 1522 } 1523 } 1524 1525 /* Convert to a power of 2 alignment. */ 1526 if (align) 1527 { 1528 for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) 1529 continue; 1530 if (align != 1) 1531 { 1532 as_bad (_("Common alignment not a power of 2")); 1533 ignore_rest_of_line (); 1534 return; 1535 } 1536 } 1537 else 1538 align2 = 0; 1539 1540 *p = 0; 1541 symbolP = symbol_find_or_make (name); 1542 *p = c; 1543 1544 if (S_IS_DEFINED (symbolP)) 1545 { 1546 /* xgettext:c-format */ 1547 as_bad (_("Ignoring attempt to re-define symbol `%s'."), 1548 S_GET_NAME (symbolP)); 1549 ignore_rest_of_line (); 1550 return; 1551 } 1552 1553 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) 1554 { 1555 /* xgettext:c-format */ 1556 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), 1557 S_GET_NAME (symbolP), 1558 (long) S_GET_VALUE (symbolP), 1559 (long) size); 1560 1561 ignore_rest_of_line (); 1562 return; 1563 } 1564 1565 if (symbol_get_obj (symbolP)->local) 1566 { 1567 segT old_sec = now_seg; 1568 int old_subsec = now_subseg; 1569 char *pfrag; 1570 1571 record_alignment (sbss_section, align2); 1572 subseg_set (sbss_section, 0); 1573 1574 if (align2) 1575 frag_align (align2, 0, 0); 1576 1577 if (S_GET_SEGMENT (symbolP) == sbss_section) 1578 symbol_get_frag (symbolP)->fr_symbol = 0; 1579 1580 symbol_set_frag (symbolP, frag_now); 1581 1582 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, 1583 (char *) 0); 1584 *pfrag = 0; 1585 S_SET_SIZE (symbolP, size); 1586 S_SET_SEGMENT (symbolP, sbss_section); 1587 S_CLEAR_EXTERNAL (symbolP); 1588 subseg_set (old_sec, old_subsec); 1589 } 1590 else 1591 { 1592 S_SET_VALUE (symbolP, (valueT) size); 1593 S_SET_ALIGN (symbolP, align2); 1594 S_SET_EXTERNAL (symbolP); 1595 S_SET_SEGMENT (symbolP, &scom_section); 1596 } 1597 1598 demand_empty_rest_of_line (); 1599 } 1600 1601 /* The target specific pseudo-ops which we support. */ 1602 const pseudo_typeS md_pseudo_table[] = 1603 { 1604 { "word", cons, 4 }, 1605 { "fillinsn", fill_insn, 0 }, 1606 { "scomm", m32r_scomm, 0 }, 1607 { "debugsym", debug_sym, 0 }, 1608 { "m32r", allow_m32rx, 0 }, 1609 { "m32rx", allow_m32rx, 1 }, 1610 { "m32r2", allow_m32rx, 2 }, 1611 { "little", little, 1 }, 1612 { "big", little, 0 }, 1613 { NULL, NULL, 0 } 1614 }; 1615 1616 /* Interface to relax_segment. */ 1618 1619 /* FIXME: Build table by hand, get it working, then machine generate. */ 1620 1621 const relax_typeS md_relax_table[] = 1622 { 1623 /* The fields are: 1624 1) most positive reach of this state, 1625 2) most negative reach of this state, 1626 3) how many bytes this mode will add to the size of the current frag 1627 4) which index into the table to try if we can't fit into this one. */ 1628 1629 /* The first entry must be unused because an `rlx_more' value of zero ends 1630 each list. */ 1631 {1, 1, 0, 0}, 1632 1633 /* The displacement used by GAS is from the end of the 2 byte insn, 1634 so we subtract 2 from the following. */ 1635 /* 16 bit insn, 8 bit disp -> 10 bit range. 1636 This doesn't handle a branch in the right slot at the border: 1637 the "& -4" isn't taken into account. It's not important enough to 1638 complicate things over it, so we subtract an extra 2 (or + 2 in -ve 1639 case). */ 1640 {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, 1641 /* 32 bit insn, 24 bit disp -> 26 bit range. */ 1642 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, 1643 /* Same thing, but with leading nop for alignment. */ 1644 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } 1645 }; 1646 1647 long 1648 m32r_relax_frag (segT segment, fragS *fragP, long stretch) 1649 { 1650 /* Address of branch insn. */ 1651 long address = fragP->fr_address + fragP->fr_fix - 2; 1652 long growth = 0; 1653 1654 /* Keep 32 bit insns aligned on 32 bit boundaries. */ 1655 if (fragP->fr_subtype == 2) 1656 { 1657 if ((address & 3) != 0) 1658 { 1659 fragP->fr_subtype = 3; 1660 growth = 2; 1661 } 1662 } 1663 else if (fragP->fr_subtype == 3) 1664 { 1665 if ((address & 3) == 0) 1666 { 1667 fragP->fr_subtype = 2; 1668 growth = -2; 1669 } 1670 } 1671 else 1672 { 1673 growth = relax_frag (segment, fragP, stretch); 1674 1675 /* Long jump on odd halfword boundary? */ 1676 if (fragP->fr_subtype == 2 && (address & 3) != 0) 1677 { 1678 fragP->fr_subtype = 3; 1679 growth += 2; 1680 } 1681 } 1682 1683 return growth; 1684 } 1685 1686 /* Return an initial guess of the length by which a fragment must grow to 1687 hold a branch to reach its destination. 1688 Also updates fr_type/fr_subtype as necessary. 1689 1690 Called just before doing relaxation. 1691 Any symbol that is now undefined will not become defined. 1692 The guess for fr_var is ACTUALLY the growth beyond fr_fix. 1693 Whatever we do to grow fr_fix or fr_var contributes to our returned value. 1694 Although it may not be explicit in the frag, pretend fr_var starts 1695 with a 0 value. */ 1696 1697 int 1698 md_estimate_size_before_relax (fragS *fragP, segT segment) 1699 { 1700 /* The only thing we have to handle here are symbols outside of the 1701 current segment. They may be undefined or in a different segment in 1702 which case linker scripts may place them anywhere. 1703 However, we can't finish the fragment here and emit the reloc as insn 1704 alignment requirements may move the insn about. */ 1705 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 1706 || S_IS_EXTERNAL (fragP->fr_symbol) 1707 || S_IS_WEAK (fragP->fr_symbol)) 1708 { 1709 /* The symbol is undefined in this segment. 1710 Change the relaxation subtype to the max allowable and leave 1711 all further handling to md_convert_frag. */ 1712 fragP->fr_subtype = 2; 1713 1714 { 1715 const CGEN_INSN *insn; 1716 int i; 1717 1718 /* Update the recorded insn. 1719 Fortunately we don't have to look very far. 1720 FIXME: Change this to record in the instruction the next higher 1721 relaxable insn to use. */ 1722 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) 1723 { 1724 if ((strcmp (CGEN_INSN_MNEMONIC (insn), 1725 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) 1726 == 0) 1727 && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) 1728 break; 1729 } 1730 if (i == 4) 1731 abort (); 1732 1733 fragP->fr_cgen.insn = insn; 1734 return 2; 1735 } 1736 } 1737 1738 return md_relax_table[fragP->fr_subtype].rlx_length; 1739 } 1740 1741 /* *FRAGP has been relaxed to its final size, and now needs to have 1742 the bytes inside it modified to conform to the new size. 1743 1744 Called after relaxation is finished. 1745 fragP->fr_type == rs_machine_dependent. 1746 fragP->fr_subtype is the subtype of what the address relaxed to. */ 1747 1748 void 1749 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 1750 segT sec, 1751 fragS *fragP) 1752 { 1753 char *opcode; 1754 char *displacement; 1755 int target_address; 1756 int opcode_address; 1757 int extension; 1758 int addend; 1759 1760 opcode = fragP->fr_opcode; 1761 1762 /* Address opcode resides at in file space. */ 1763 opcode_address = fragP->fr_address + fragP->fr_fix - 2; 1764 1765 switch (fragP->fr_subtype) 1766 { 1767 case 1: 1768 extension = 0; 1769 displacement = &opcode[1]; 1770 break; 1771 case 2: 1772 opcode[0] |= 0x80; 1773 extension = 2; 1774 displacement = &opcode[1]; 1775 break; 1776 case 3: 1777 opcode[2] = opcode[0] | 0x80; 1778 md_number_to_chars (opcode, PAR_NOP_INSN, 2); 1779 opcode_address += 2; 1780 extension = 4; 1781 displacement = &opcode[3]; 1782 break; 1783 default: 1784 abort (); 1785 } 1786 1787 if (S_GET_SEGMENT (fragP->fr_symbol) != sec 1788 || S_IS_EXTERNAL (fragP->fr_symbol) 1789 || S_IS_WEAK (fragP->fr_symbol)) 1790 { 1791 /* Symbol must be resolved by linker. */ 1792 if (fragP->fr_offset & 3) 1793 as_warn (_("Addend to unresolved symbol not on word boundary.")); 1794 #ifdef USE_M32R_OLD_RELOC 1795 addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */ 1796 #else 1797 addend = 0; 1798 #endif 1799 } 1800 else 1801 { 1802 /* Address we want to reach in file space. */ 1803 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 1804 addend = (target_address - (opcode_address & -4)) >> 2; 1805 } 1806 1807 /* Create a relocation for symbols that must be resolved by the linker. 1808 Otherwise output the completed insn. */ 1809 1810 if (S_GET_SEGMENT (fragP->fr_symbol) != sec 1811 || S_IS_EXTERNAL (fragP->fr_symbol) 1812 || S_IS_WEAK (fragP->fr_symbol)) 1813 { 1814 fixS *fixP; 1815 1816 gas_assert (fragP->fr_subtype != 1); 1817 gas_assert (fragP->fr_cgen.insn != 0); 1818 1819 fixP = gas_cgen_record_fixup (fragP, 1820 /* Offset of branch insn in frag. */ 1821 fragP->fr_fix + extension - 4, 1822 fragP->fr_cgen.insn, 1823 4 /* Length. */, 1824 /* FIXME: quick hack. */ 1825 cgen_operand_lookup_by_num (gas_cgen_cpu_desc, 1826 M32R_OPERAND_DISP24), 1827 fragP->fr_cgen.opinfo, 1828 fragP->fr_symbol, fragP->fr_offset); 1829 if (fragP->fr_cgen.opinfo) 1830 fixP->fx_r_type = fragP->fr_cgen.opinfo; 1831 } 1832 1833 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) 1834 1835 md_number_to_chars (displacement, (valueT) addend, 1836 SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 1837 1838 fragP->fr_fix += extension; 1839 } 1840 1841 /* Functions concerning relocs. */ 1843 1844 /* The location from which a PC relative jump should be calculated, 1845 given a PC relative reloc. */ 1846 1847 long 1848 md_pcrel_from_section (fixS *fixP, segT sec) 1849 { 1850 if (fixP->fx_addsy != (symbolS *) NULL 1851 && (! S_IS_DEFINED (fixP->fx_addsy) 1852 || S_GET_SEGMENT (fixP->fx_addsy) != sec 1853 || S_IS_EXTERNAL (fixP->fx_addsy) 1854 || S_IS_WEAK (fixP->fx_addsy))) 1855 { 1856 if (S_GET_SEGMENT (fixP->fx_addsy) != sec 1857 && S_IS_DEFINED (fixP->fx_addsy) 1858 && ! S_IS_EXTERNAL (fixP->fx_addsy) 1859 && ! S_IS_WEAK (fixP->fx_addsy)) 1860 return fixP->fx_offset; 1861 1862 /* The symbol is undefined (or is defined but not in this section). 1863 Let the linker figure it out. */ 1864 return 0; 1865 } 1866 1867 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; 1868 } 1869 1870 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. 1871 Returns BFD_RELOC_NONE if no reloc type can be found. 1872 *FIXP may be modified if desired. */ 1873 1874 bfd_reloc_code_real_type 1875 md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, 1876 const CGEN_OPERAND *operand, 1877 fixS *fixP) 1878 { 1879 switch (operand->type) 1880 { 1881 case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; 1882 case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; 1883 case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; 1884 case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; 1885 case M32R_OPERAND_HI16: 1886 case M32R_OPERAND_SLO16: 1887 case M32R_OPERAND_ULO16: 1888 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ 1889 if (fixP->fx_cgen.opinfo != 0) 1890 return fixP->fx_cgen.opinfo; 1891 break; 1892 default: 1893 /* Avoid -Wall warning. */ 1894 break; 1895 } 1896 return BFD_RELOC_NONE; 1897 } 1898 1899 /* Record a HI16 reloc for later matching with its LO16 cousin. */ 1900 1901 static void 1902 m32r_record_hi16 (int reloc_type, 1903 fixS *fixP, 1904 segT seg ATTRIBUTE_UNUSED) 1905 { 1906 struct m32r_hi_fixup *hi_fixup; 1907 1908 gas_assert (reloc_type == BFD_RELOC_M32R_HI16_SLO 1909 || reloc_type == BFD_RELOC_M32R_HI16_ULO); 1910 1911 hi_fixup = xmalloc (sizeof (* hi_fixup)); 1912 hi_fixup->fixp = fixP; 1913 hi_fixup->seg = now_seg; 1914 hi_fixup->next = m32r_hi_fixup_list; 1915 1916 m32r_hi_fixup_list = hi_fixup; 1917 } 1918 1919 /* Called while parsing an instruction to create a fixup. 1920 We need to check for HI16 relocs and queue them up for later sorting. */ 1921 1922 fixS * 1923 m32r_cgen_record_fixup_exp (fragS *frag, 1924 int where, 1925 const CGEN_INSN *insn, 1926 int length, 1927 const CGEN_OPERAND *operand, 1928 int opinfo, 1929 expressionS *exp) 1930 { 1931 fixS *fixP; 1932 bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED; 1933 1934 if (m32r_check_fixup (exp, &r_type)) 1935 as_bad (_("Invalid PIC expression.")); 1936 1937 fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, 1938 operand, opinfo, exp); 1939 1940 switch (operand->type) 1941 { 1942 case M32R_OPERAND_HI16: 1943 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ 1944 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO 1945 || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) 1946 m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); 1947 break; 1948 1949 default: 1950 /* Avoid -Wall warning. */ 1951 break; 1952 } 1953 1954 switch (r_type) 1955 { 1956 case BFD_RELOC_UNUSED: 1957 default: 1958 return fixP; 1959 1960 case BFD_RELOC_M32R_GOTPC24: 1961 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) 1962 r_type = BFD_RELOC_M32R_GOTPC_HI_SLO; 1963 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) 1964 r_type = BFD_RELOC_M32R_GOTPC_HI_ULO; 1965 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) 1966 r_type = BFD_RELOC_M32R_GOTPC_LO; 1967 break; 1968 1969 case BFD_RELOC_M32R_GOT24: 1970 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) 1971 r_type = BFD_RELOC_M32R_GOT16_HI_SLO; 1972 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) 1973 r_type = BFD_RELOC_M32R_GOT16_HI_ULO; 1974 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) 1975 r_type = BFD_RELOC_M32R_GOT16_LO; 1976 break; 1977 1978 case BFD_RELOC_M32R_GOTOFF: 1979 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) 1980 r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO; 1981 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) 1982 r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO; 1983 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) 1984 r_type = BFD_RELOC_M32R_GOTOFF_LO; 1985 break; 1986 1987 case BFD_RELOC_M32R_26_PLTREL: 1988 as_bad (_("Invalid PIC expression.")); 1989 break; 1990 } 1991 1992 fixP->fx_r_type = r_type; 1993 1994 return fixP; 1995 } 1996 1997 /* Return BFD reloc type from opinfo field in a fixS. 1998 It's tricky using fx_r_type in m32r_frob_file because the values 1999 are BFD_RELOC_UNUSED + operand number. */ 2000 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) 2001 2002 /* Sort any unmatched HI16 relocs so that they immediately precede 2003 the corresponding LO16 reloc. This is called before md_apply_fix and 2004 tc_gen_reloc. */ 2005 2006 void 2007 m32r_frob_file (void) 2008 { 2009 struct m32r_hi_fixup *l; 2010 2011 for (l = m32r_hi_fixup_list; l != NULL; l = l->next) 2012 { 2013 segment_info_type *seginfo; 2014 int pass; 2015 2016 gas_assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO 2017 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); 2018 2019 /* Check quickly whether the next fixup happens to be a matching low. */ 2020 if (l->fixp->fx_next != NULL 2021 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 2022 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy 2023 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) 2024 continue; 2025 2026 /* Look through the fixups for this segment for a matching `low'. 2027 When we find one, move the high/shigh just in front of it. We do 2028 this in two passes. In the first pass, we try to find a 2029 unique `low'. In the second pass, we permit multiple high's 2030 relocs for a single `low'. */ 2031 seginfo = seg_info (l->seg); 2032 for (pass = 0; pass < 2; pass++) 2033 { 2034 fixS *f; 2035 fixS *prev; 2036 2037 prev = NULL; 2038 for (f = seginfo->fix_root; f != NULL; f = f->fx_next) 2039 { 2040 /* Check whether this is a `low' fixup which matches l->fixp. */ 2041 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 2042 && f->fx_addsy == l->fixp->fx_addsy 2043 && f->fx_offset == l->fixp->fx_offset 2044 && (pass == 1 2045 || prev == NULL 2046 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO 2047 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) 2048 || prev->fx_addsy != f->fx_addsy 2049 || prev->fx_offset != f->fx_offset)) 2050 { 2051 fixS **pf; 2052 2053 /* Move l->fixp before f. */ 2054 for (pf = &seginfo->fix_root; 2055 *pf != l->fixp; 2056 pf = & (*pf)->fx_next) 2057 gas_assert (*pf != NULL); 2058 2059 *pf = l->fixp->fx_next; 2060 2061 l->fixp->fx_next = f; 2062 if (prev == NULL) 2063 seginfo->fix_root = l->fixp; 2064 else 2065 prev->fx_next = l->fixp; 2066 2067 break; 2068 } 2069 2070 prev = f; 2071 } 2072 2073 if (f != NULL) 2074 break; 2075 2076 if (pass == 1 2077 && warn_unmatched_high) 2078 as_warn_where (l->fixp->fx_file, l->fixp->fx_line, 2079 _("Unmatched high/shigh reloc")); 2080 } 2081 } 2082 } 2083 2084 /* See whether we need to force a relocation into the output file. 2085 This is used to force out switch and PC relative relocations when 2086 relaxing. */ 2087 2088 int 2089 m32r_force_relocation (fixS *fix) 2090 { 2091 if (generic_force_reloc (fix)) 2092 return 1; 2093 2094 if (! m32r_relax) 2095 return 0; 2096 2097 return fix->fx_pcrel; 2098 } 2099 2100 /* Write a value out to the object file, using the appropriate endianness. */ 2102 2103 void 2104 md_number_to_chars (char *buf, valueT val, int n) 2105 { 2106 if (target_big_endian) 2107 number_to_chars_bigendian (buf, val, n); 2108 else 2109 number_to_chars_littleendian (buf, val, n); 2110 } 2111 2112 /* Turn a string in input_line_pointer into a floating point constant 2113 of type TYPE, and store the appropriate bytes in *LITP. The number 2114 of LITTLENUMS emitted is stored in *SIZEP. An error message is 2115 returned, or NULL on OK. */ 2116 2117 /* Equal to MAX_PRECISION in atof-ieee.c. */ 2118 #define MAX_LITTLENUMS 6 2119 2120 char * 2121 md_atof (int type, char *litP, int *sizeP) 2122 { 2123 return ieee_md_atof (type, litP, sizeP, target_big_endian); 2124 } 2125 2126 void 2127 m32r_elf_section_change_hook (void) 2128 { 2129 /* If we have reached the end of a section and we have just emitted a 2130 16 bit insn, then emit a nop to make sure that the section ends on 2131 a 32 bit boundary. */ 2132 2133 if (prev_insn.insn || seen_relaxable_p) 2134 (void) m32r_fill_insn (0); 2135 } 2136 2137 /* Return true if can adjust the reloc to be relative to its section 2138 (such as .data) instead of relative to some symbol. */ 2139 2140 bfd_boolean 2141 m32r_fix_adjustable (fixS *fixP) 2142 { 2143 bfd_reloc_code_real_type reloc_type; 2144 2145 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) 2146 { 2147 const CGEN_INSN *insn = NULL; 2148 int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; 2149 const CGEN_OPERAND *operand = 2150 cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); 2151 2152 reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); 2153 } 2154 else 2155 reloc_type = fixP->fx_r_type; 2156 2157 if (fixP->fx_addsy == NULL) 2158 return 1; 2159 2160 /* Prevent all adjustments to global symbols. */ 2161 if (S_IS_EXTERNAL (fixP->fx_addsy)) 2162 return 0; 2163 if (S_IS_WEAK (fixP->fx_addsy)) 2164 return 0; 2165 2166 if (pic_code 2167 && (reloc_type == BFD_RELOC_M32R_24 2168 || reloc_type == BFD_RELOC_M32R_26_PCREL 2169 || reloc_type == BFD_RELOC_M32R_HI16_SLO 2170 || reloc_type == BFD_RELOC_M32R_HI16_ULO 2171 || reloc_type == BFD_RELOC_M32R_LO16)) 2172 return 0; 2173 2174 if (reloc_type == BFD_RELOC_M32R_GOT24 2175 || reloc_type == BFD_RELOC_M32R_26_PLTREL 2176 || reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO 2177 || reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO 2178 || reloc_type == BFD_RELOC_M32R_GOTPC_LO 2179 || reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO 2180 || reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO 2181 || reloc_type == BFD_RELOC_M32R_GOT16_LO) 2182 return 0; 2183 2184 /* We need the symbol name for the VTABLE entries. */ 2185 if (reloc_type == BFD_RELOC_VTABLE_INHERIT 2186 || reloc_type == BFD_RELOC_VTABLE_ENTRY) 2187 return 0; 2188 2189 return 1; 2190 } 2191 2192 void 2193 m32r_elf_final_processing (void) 2194 { 2195 if (use_parallel) 2196 m32r_flags |= E_M32R_HAS_PARALLEL; 2197 elf_elfheader (stdoutput)->e_flags |= m32r_flags; 2198 } 2199 2200 /* Translate internal representation of relocation info to BFD target 2201 format. */ 2202 2203 arelent * 2204 tc_gen_reloc (asection * section, fixS * fixP) 2205 { 2206 arelent * reloc; 2207 bfd_reloc_code_real_type code; 2208 2209 reloc = xmalloc (sizeof (* reloc)); 2210 2211 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 2212 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); 2213 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; 2214 2215 if (fixP->fx_pcrel) 2216 { 2217 if (fixP->fx_r_type == BFD_RELOC_32) 2218 fixP->fx_r_type = BFD_RELOC_32_PCREL; 2219 else if (fixP->fx_r_type == BFD_RELOC_16) 2220 { 2221 fixP->fx_r_type = BFD_RELOC_16_PCREL; 2222 bfd_set_error (bfd_error_bad_value); 2223 } 2224 } 2225 2226 code = fixP->fx_r_type; 2227 if (pic_code) 2228 { 2229 #ifdef DEBUG_PIC 2230 printf("%s",bfd_get_reloc_code_name(code)); 2231 #endif 2232 switch (code) 2233 { 2234 case BFD_RELOC_M32R_26_PCREL: 2235 code = BFD_RELOC_M32R_26_PLTREL; 2236 break; 2237 2238 case BFD_RELOC_M32R_24: 2239 if (fixP->fx_addsy != NULL 2240 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) 2241 code = BFD_RELOC_M32R_GOTPC24; 2242 else 2243 code = BFD_RELOC_M32R_GOT24; 2244 break; 2245 2246 case BFD_RELOC_M32R_HI16_ULO: 2247 if (fixP->fx_addsy != NULL 2248 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) 2249 code = BFD_RELOC_M32R_GOTPC_HI_ULO; 2250 else 2251 code = BFD_RELOC_M32R_GOT16_HI_ULO; 2252 break; 2253 2254 case BFD_RELOC_M32R_HI16_SLO: 2255 if (fixP->fx_addsy != NULL 2256 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) 2257 code = BFD_RELOC_M32R_GOTPC_HI_SLO; 2258 else 2259 code = BFD_RELOC_M32R_GOT16_HI_SLO; 2260 break; 2261 2262 case BFD_RELOC_M32R_LO16: 2263 if (fixP->fx_addsy != NULL 2264 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) 2265 code = BFD_RELOC_M32R_GOTPC_LO; 2266 else 2267 code = BFD_RELOC_M32R_GOT16_LO; 2268 break; 2269 2270 default: 2271 break; 2272 } 2273 #ifdef DEBUG_PIC 2274 printf(" => %s",bfd_get_reloc_code_name(code)); 2275 #endif 2276 } 2277 2278 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 2279 2280 #ifdef DEBUG_PIC 2281 printf(" => %s\n",reloc->howto->name); 2282 #endif 2283 2284 if (reloc->howto == (reloc_howto_type *) NULL) 2285 { 2286 as_bad_where (fixP->fx_file, fixP->fx_line, 2287 _("internal error: can't export reloc type %d (`%s')"), 2288 fixP->fx_r_type, bfd_get_reloc_code_name (code)); 2289 return NULL; 2290 } 2291 2292 /* Use fx_offset for these cases. */ 2293 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY 2294 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 2295 || fixP->fx_r_type == BFD_RELOC_32_PCREL) 2296 reloc->addend = fixP->fx_offset; 2297 else if ((!pic_code 2298 && code != BFD_RELOC_M32R_26_PLTREL) 2299 && fixP->fx_pcrel 2300 && fixP->fx_addsy != NULL 2301 && (S_GET_SEGMENT(fixP->fx_addsy) != section) 2302 && S_IS_DEFINED (fixP->fx_addsy) 2303 && ! S_IS_EXTERNAL(fixP->fx_addsy) 2304 && ! S_IS_WEAK(fixP->fx_addsy)) 2305 /* Already used fx_offset in the opcode field itseld. */ 2306 reloc->addend = fixP->fx_offset; 2307 else 2308 reloc->addend = fixP->fx_addnumber; 2309 2310 return reloc; 2311 } 2312 2313 inline static char * 2314 m32r_end_of_match (char *cont, char *what) 2315 { 2316 int len = strlen (what); 2317 2318 if (strncasecmp (cont, what, strlen (what)) == 0 2319 && ! is_part_of_name (cont[len])) 2320 return cont + len; 2321 2322 return NULL; 2323 } 2324 2325 int 2326 m32r_parse_name (char const *name, 2327 expressionS *exprP, 2328 enum expr_mode mode, 2329 char *nextcharP) 2330 { 2331 char *next = input_line_pointer; 2332 char *next_end; 2333 int reloc_type; 2334 operatorT op_type; 2335 segT segment; 2336 2337 exprP->X_op_symbol = NULL; 2338 exprP->X_md = BFD_RELOC_UNUSED; 2339 2340 if (strcmp (name, GOT_NAME) == 0) 2341 { 2342 if (! GOT_symbol) 2343 GOT_symbol = symbol_find_or_make (name); 2344 2345 exprP->X_add_symbol = GOT_symbol; 2346 no_suffix: 2347 /* If we have an absolute symbol or a 2348 reg, then we know its value now. */ 2349 segment = S_GET_SEGMENT (exprP->X_add_symbol); 2350 if (mode != expr_defer && segment == absolute_section) 2351 { 2352 exprP->X_op = O_constant; 2353 exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol); 2354 exprP->X_add_symbol = NULL; 2355 } 2356 else if (mode != expr_defer && segment == reg_section) 2357 { 2358 exprP->X_op = O_register; 2359 exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol); 2360 exprP->X_add_symbol = NULL; 2361 } 2362 else 2363 { 2364 exprP->X_op = O_symbol; 2365 exprP->X_add_number = 0; 2366 } 2367 2368 return 1; 2369 } 2370 2371 exprP->X_add_symbol = symbol_find_or_make (name); 2372 2373 if (*nextcharP != '@') 2374 goto no_suffix; 2375 else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF"))) 2376 { 2377 reloc_type = BFD_RELOC_M32R_GOTOFF; 2378 op_type = O_PIC_reloc; 2379 } 2380 else if ((next_end = m32r_end_of_match (next + 1, "GOT"))) 2381 { 2382 reloc_type = BFD_RELOC_M32R_GOT24; 2383 op_type = O_PIC_reloc; 2384 } 2385 else if ((next_end = m32r_end_of_match (next + 1, "PLT"))) 2386 { 2387 reloc_type = BFD_RELOC_M32R_26_PLTREL; 2388 op_type = O_PIC_reloc; 2389 } 2390 else 2391 goto no_suffix; 2392 2393 *input_line_pointer = *nextcharP; 2394 input_line_pointer = next_end; 2395 *nextcharP = *input_line_pointer; 2396 *input_line_pointer = '\0'; 2397 2398 exprP->X_op = op_type; 2399 exprP->X_add_number = 0; 2400 exprP->X_md = reloc_type; 2401 2402 return 1; 2403 } 2404 2405 int 2406 m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp) 2407 { 2408 if (exp->X_op == O_PIC_reloc 2409 && exp->X_md == BFD_RELOC_M32R_26_PLTREL) 2410 { 2411 exp->X_op = O_symbol; 2412 opinfo = exp->X_md; 2413 } 2414 2415 return opinfo; 2416 } 2417
