1 /* tc-v850.c -- Assembler code for the NEC V850 2 Copyright (C) 1996-2014 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 19 Boston, MA 02110-1301, USA. */ 20 21 #include "as.h" 22 #include "safe-ctype.h" 23 #include "subsegs.h" 24 #include "opcode/v850.h" 25 #include "dwarf2dbg.h" 26 27 /* Sign-extend a 16-bit number. */ 28 #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000) 29 30 /* Set to TRUE if we want to be pedantic about signed overflows. */ 31 static bfd_boolean warn_signed_overflows = FALSE; 32 static bfd_boolean warn_unsigned_overflows = FALSE; 33 34 /* Indicates the target BFD machine number. */ 35 static int machine = -1; 36 37 38 /* Indiciates the target BFD architecture. */ 39 int v850_target_arch = bfd_arch_v850_rh850; 40 const char * v850_target_format = "elf32-v850-rh850"; 41 static flagword v850_e_flags = 0; 42 43 /* Indicates the target processor(s) for the assemble. */ 44 static int processor_mask = 0; 45 46 /* Structure to hold information about predefined registers. */ 48 struct reg_name 49 { 50 const char *name; 51 int value; 52 unsigned int processors; 53 }; 54 55 /* Generic assembler global variables which must be defined by all 56 targets. */ 57 58 /* Characters which always start a comment. */ 59 const char comment_chars[] = "#"; 60 61 /* Characters which start a comment at the beginning of a line. */ 62 const char line_comment_chars[] = ";#"; 63 64 /* Characters which may be used to separate multiple commands on a 65 single line. */ 66 const char line_separator_chars[] = ";"; 67 68 /* Characters which are used to indicate an exponent in a floating 69 point number. */ 70 const char EXP_CHARS[] = "eE"; 71 72 /* Characters which mean that a number is a floating point constant, 73 as in 0d1.0. */ 74 const char FLT_CHARS[] = "dD"; 75 76 const relax_typeS md_relax_table[] = 78 { 79 /* Conditional branches.(V850/V850E, max 22bit) */ 80 #define SUBYPTE_COND_9_22 0 81 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1}, 82 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 83 /* Conditional branches.(V850/V850E, max 22bit) */ 84 #define SUBYPTE_SA_9_22 2 85 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1}, 86 {0x1ffffe + 4, -0x200000 + 4, 8, 0}, 87 /* Unconditional branches.(V850/V850E, max 22bit) */ 88 #define SUBYPTE_UNCOND_9_22 4 89 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1}, 90 {0x1ffffe, -0x200000, 4, 0}, 91 /* Conditional branches.(V850E2, max 32bit) */ 92 #define SUBYPTE_COND_9_22_32 6 93 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1}, 94 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2}, 95 {0x7ffffffe, -0x80000000, 8, 0}, 96 /* Conditional branches.(V850E2, max 32bit) */ 97 #define SUBYPTE_SA_9_22_32 9 98 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1}, 99 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2}, 100 {0x7ffffffe, -0x80000000, 10, 0}, 101 /* Unconditional branches.(V850E2, max 32bit) */ 102 #define SUBYPTE_UNCOND_9_22_32 12 103 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1}, 104 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2}, 105 {0x7ffffffe, -0x80000000, 6, 0}, 106 /* Conditional branches.(V850E2R max 22bit) */ 107 #define SUBYPTE_COND_9_17_22 15 108 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1}, 109 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2}, 110 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 111 /* Conditional branches.(V850E2R max 22bit) */ 112 #define SUBYPTE_SA_9_17_22 18 113 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1}, 114 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2}, 115 {0x1ffffe + 4, -0x200000 + 4, 8, 0}, 116 /* Conditional branches.(V850E2R max 32bit) */ 117 #define SUBYPTE_COND_9_17_22_32 21 118 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1}, 119 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2}, 120 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3}, 121 {0x7ffffffe, -0x80000000, 8, 0}, 122 /* Conditional branches.(V850E2R max 32bit) */ 123 #define SUBYPTE_SA_9_17_22_32 25 124 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1}, 125 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2}, 126 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3}, 127 {0x7ffffffe, -0x80000000, 10, 0}, 128 /* Loop. (V850E2V4_UP, max 22-bit). */ 129 #define SUBYPTE_LOOP_16_22 29 130 {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22 + 1}, 131 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 132 }; 133 134 static int v850_relax = 0; 135 136 /* Default branch disp size 22 or 32. */ 137 static int default_disp_size = 22; 138 139 /* Default no using bcond17. */ 140 static int no_bcond17 = 0; 141 142 /* Default no using ld/st 23bit offset. */ 143 static int no_stld23 = 0; 144 145 /* Fixups. */ 146 #define MAX_INSN_FIXUPS 5 147 148 struct v850_fixup 149 { 150 expressionS exp; 151 int opindex; 152 bfd_reloc_code_real_type reloc; 153 }; 154 155 struct v850_fixup fixups[MAX_INSN_FIXUPS]; 156 static int fc; 157 158 struct v850_seg_entry 159 { 160 segT s; 161 const char *name; 162 flagword flags; 163 }; 164 165 struct v850_seg_entry v850_seg_table[] = 166 { 167 { NULL, ".sdata", 168 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 169 | SEC_SMALL_DATA }, 170 { NULL, ".tdata", 171 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 172 { NULL, ".zdata", 173 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 174 { NULL, ".sbss", 175 SEC_ALLOC | SEC_SMALL_DATA }, 176 { NULL, ".tbss", 177 SEC_ALLOC }, 178 { NULL, ".zbss", 179 SEC_ALLOC}, 180 { NULL, ".rosdata", 181 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA 182 | SEC_HAS_CONTENTS | SEC_SMALL_DATA }, 183 { NULL, ".rozdata", 184 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA 185 | SEC_HAS_CONTENTS }, 186 { NULL, ".scommon", 187 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 188 | SEC_SMALL_DATA | SEC_IS_COMMON }, 189 { NULL, ".tcommon", 190 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 191 | SEC_IS_COMMON }, 192 { NULL, ".zcommon", 193 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 194 | SEC_IS_COMMON }, 195 { NULL, ".call_table_data", 196 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 197 { NULL, ".call_table_text", 198 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE 199 | SEC_HAS_CONTENTS}, 200 { NULL, ".bss", 201 SEC_ALLOC } 202 }; 203 204 #define SDATA_SECTION 0 205 #define TDATA_SECTION 1 206 #define ZDATA_SECTION 2 207 #define SBSS_SECTION 3 208 #define TBSS_SECTION 4 209 #define ZBSS_SECTION 5 210 #define ROSDATA_SECTION 6 211 #define ROZDATA_SECTION 7 212 #define SCOMMON_SECTION 8 213 #define TCOMMON_SECTION 9 214 #define ZCOMMON_SECTION 10 215 #define CALL_TABLE_DATA_SECTION 11 216 #define CALL_TABLE_TEXT_SECTION 12 217 #define BSS_SECTION 13 218 219 static void 220 do_v850_seg (int i, subsegT sub) 221 { 222 struct v850_seg_entry *seg = v850_seg_table + i; 223 224 obj_elf_section_change_hook (); 225 226 if (seg->s != NULL) 227 subseg_set (seg->s, sub); 228 else 229 { 230 seg->s = subseg_new (seg->name, sub); 231 bfd_set_section_flags (stdoutput, seg->s, seg->flags); 232 if ((seg->flags & SEC_LOAD) == 0) 233 seg_info (seg->s)->bss = 1; 234 } 235 } 236 237 static void 238 v850_seg (int i) 239 { 240 subsegT sub = get_absolute_expression (); 241 242 do_v850_seg (i, sub); 243 demand_empty_rest_of_line (); 244 } 245 246 static void 247 v850_offset (int ignore ATTRIBUTE_UNUSED) 248 { 249 char *pfrag; 250 int temp = get_absolute_expression (); 251 252 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0, 253 (offsetT) temp, (char *) 0); 254 *pfrag = 0; 255 256 demand_empty_rest_of_line (); 257 } 258 259 /* Copied from obj_elf_common() in gas/config/obj-elf.c. */ 260 261 static void 262 v850_comm (int area) 263 { 264 char *name; 265 char c; 266 char *p; 267 int temp; 268 unsigned int size; 269 symbolS *symbolP; 270 int have_align; 271 272 name = input_line_pointer; 273 c = get_symbol_end (); 274 275 /* Just after name is now '\0'. */ 276 p = input_line_pointer; 277 *p = c; 278 279 SKIP_WHITESPACE (); 280 281 if (*input_line_pointer != ',') 282 { 283 as_bad (_("Expected comma after symbol-name")); 284 ignore_rest_of_line (); 285 return; 286 } 287 288 /* Skip ','. */ 289 input_line_pointer++; 290 291 if ((temp = get_absolute_expression ()) < 0) 292 { 293 /* xgettext:c-format */ 294 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp); 295 ignore_rest_of_line (); 296 return; 297 } 298 299 size = temp; 300 *p = 0; 301 symbolP = symbol_find_or_make (name); 302 *p = c; 303 304 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 305 { 306 as_bad (_("Ignoring attempt to re-define symbol")); 307 ignore_rest_of_line (); 308 return; 309 } 310 311 if (S_GET_VALUE (symbolP) != 0) 312 { 313 if (S_GET_VALUE (symbolP) != size) 314 /* xgettext:c-format */ 315 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), 316 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); 317 } 318 319 know (symbol_get_frag (symbolP) == &zero_address_frag); 320 321 if (*input_line_pointer != ',') 322 have_align = 0; 323 else 324 { 325 have_align = 1; 326 input_line_pointer++; 327 SKIP_WHITESPACE (); 328 } 329 330 if (! have_align || *input_line_pointer != '"') 331 { 332 if (! have_align) 333 temp = 0; 334 else 335 { 336 temp = get_absolute_expression (); 337 338 if (temp < 0) 339 { 340 temp = 0; 341 as_warn (_("Common alignment negative; 0 assumed")); 342 } 343 } 344 345 if (symbol_get_obj (symbolP)->local) 346 { 347 segT old_sec; 348 int old_subsec; 349 char *pfrag; 350 int align; 351 flagword applicable; 352 353 old_sec = now_seg; 354 old_subsec = now_subseg; 355 356 applicable = bfd_applicable_section_flags (stdoutput); 357 358 applicable &= SEC_ALLOC; 359 360 switch (area) 361 { 362 case SCOMMON_SECTION: 363 do_v850_seg (SBSS_SECTION, 0); 364 break; 365 366 case ZCOMMON_SECTION: 367 do_v850_seg (ZBSS_SECTION, 0); 368 break; 369 370 case TCOMMON_SECTION: 371 do_v850_seg (TBSS_SECTION, 0); 372 break; 373 } 374 375 if (temp) 376 { 377 /* Convert to a power of 2 alignment. */ 378 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align) 379 ; 380 381 if (temp != 1) 382 { 383 as_bad (_("Common alignment not a power of 2")); 384 ignore_rest_of_line (); 385 return; 386 } 387 } 388 else 389 align = 0; 390 391 record_alignment (now_seg, align); 392 393 if (align) 394 frag_align (align, 0, 0); 395 396 switch (area) 397 { 398 case SCOMMON_SECTION: 399 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s) 400 symbol_get_frag (symbolP)->fr_symbol = 0; 401 break; 402 403 case ZCOMMON_SECTION: 404 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s) 405 symbol_get_frag (symbolP)->fr_symbol = 0; 406 break; 407 408 case TCOMMON_SECTION: 409 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s) 410 symbol_get_frag (symbolP)->fr_symbol = 0; 411 break; 412 413 default: 414 abort (); 415 } 416 417 symbol_set_frag (symbolP, frag_now); 418 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 419 (offsetT) size, (char *) 0); 420 *pfrag = 0; 421 S_SET_SIZE (symbolP, size); 422 423 switch (area) 424 { 425 case SCOMMON_SECTION: 426 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s); 427 break; 428 429 case ZCOMMON_SECTION: 430 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s); 431 break; 432 433 case TCOMMON_SECTION: 434 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s); 435 break; 436 437 default: 438 abort (); 439 } 440 441 S_CLEAR_EXTERNAL (symbolP); 442 obj_elf_section_change_hook (); 443 subseg_set (old_sec, old_subsec); 444 } 445 else 446 { 447 segT old_sec; 448 int old_subsec; 449 450 allocate_common: 451 old_sec = now_seg; 452 old_subsec = now_subseg; 453 454 S_SET_VALUE (symbolP, (valueT) size); 455 S_SET_ALIGN (symbolP, temp); 456 S_SET_EXTERNAL (symbolP); 457 458 switch (area) 459 { 460 case SCOMMON_SECTION: 461 case ZCOMMON_SECTION: 462 case TCOMMON_SECTION: 463 do_v850_seg (area, 0); 464 S_SET_SEGMENT (symbolP, v850_seg_table[area].s); 465 break; 466 467 default: 468 abort (); 469 } 470 471 obj_elf_section_change_hook (); 472 subseg_set (old_sec, old_subsec); 473 } 474 } 475 else 476 { 477 input_line_pointer++; 478 479 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 480 if (*input_line_pointer == '.') 481 input_line_pointer++; 482 483 /* @@ Some say data, some say bss. */ 484 if (strncmp (input_line_pointer, "bss\"", 4) 485 && strncmp (input_line_pointer, "data\"", 5)) 486 { 487 while (*--input_line_pointer != '"') 488 ; 489 input_line_pointer--; 490 goto bad_common_segment; 491 } 492 493 while (*input_line_pointer++ != '"') 494 ; 495 496 goto allocate_common; 497 } 498 499 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 500 501 demand_empty_rest_of_line (); 502 return; 503 504 { 505 bad_common_segment: 506 p = input_line_pointer; 507 while (*p && *p != '\n') 508 p++; 509 c = *p; 510 *p = '\0'; 511 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 512 *p = c; 513 input_line_pointer = p; 514 ignore_rest_of_line (); 515 return; 516 } 517 } 518 519 static void 520 set_machine (int number) 521 { 522 machine = number; 523 bfd_set_arch_mach (stdoutput, v850_target_arch, machine); 524 525 switch (machine) 526 { 527 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; 528 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; 529 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; 530 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; 531 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break; 532 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break; 533 case bfd_mach_v850e3v5: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); break; 534 } 535 } 536 537 static void 538 v850_longcode (int type) 539 { 540 expressionS ex; 541 542 if (! v850_relax) 543 { 544 if (type == 1) 545 as_warn (_(".longcall pseudo-op seen when not relaxing")); 546 else 547 as_warn (_(".longjump pseudo-op seen when not relaxing")); 548 } 549 550 expression (&ex); 551 552 if (ex.X_op != O_symbol || ex.X_add_number != 0) 553 { 554 as_bad (_("bad .longcall format")); 555 ignore_rest_of_line (); 556 557 return; 558 } 559 560 if (type == 1) 561 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, 562 BFD_RELOC_V850_LONGCALL); 563 else 564 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, 565 BFD_RELOC_V850_LONGJUMP); 566 567 demand_empty_rest_of_line (); 568 } 569 570 /* The target specific pseudo-ops which we support. */ 571 const pseudo_typeS md_pseudo_table[] = 572 { 573 { "sdata", v850_seg, SDATA_SECTION }, 574 { "tdata", v850_seg, TDATA_SECTION }, 575 { "zdata", v850_seg, ZDATA_SECTION }, 576 { "sbss", v850_seg, SBSS_SECTION }, 577 { "tbss", v850_seg, TBSS_SECTION }, 578 { "zbss", v850_seg, ZBSS_SECTION }, 579 { "rosdata", v850_seg, ROSDATA_SECTION }, 580 { "rozdata", v850_seg, ROZDATA_SECTION }, 581 { "bss", v850_seg, BSS_SECTION }, 582 { "offset", v850_offset, 0 }, 583 { "word", cons, 4 }, 584 { "zcomm", v850_comm, ZCOMMON_SECTION }, 585 { "scomm", v850_comm, SCOMMON_SECTION }, 586 { "tcomm", v850_comm, TCOMMON_SECTION }, 587 { "v850", set_machine, 0 }, 588 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION }, 589 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION }, 590 { "v850e", set_machine, bfd_mach_v850e }, 591 { "v850e1", set_machine, bfd_mach_v850e1 }, 592 { "v850e2", set_machine, bfd_mach_v850e2 }, 593 { "v850e2v3", set_machine, bfd_mach_v850e2v3 }, 594 { "v850e2v4", set_machine, bfd_mach_v850e3v5 }, 595 { "v850e3v5", set_machine, bfd_mach_v850e3v5 }, 596 { "longcall", v850_longcode, 1 }, 597 { "longjump", v850_longcode, 2 }, 598 { NULL, NULL, 0 } 599 }; 600 601 /* Opcode hash table. */ 602 static struct hash_control *v850_hash; 603 604 /* This table is sorted. Suitable for searching by a binary search. */ 605 static const struct reg_name pre_defined_registers[] = 606 { 607 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */ 608 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */ 609 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */ 610 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */ 611 { "r0", 0, PROCESSOR_ALL }, 612 { "r1", 1, PROCESSOR_ALL }, 613 { "r10", 10, PROCESSOR_ALL }, 614 { "r11", 11, PROCESSOR_ALL }, 615 { "r12", 12, PROCESSOR_ALL }, 616 { "r13", 13, PROCESSOR_ALL }, 617 { "r14", 14, PROCESSOR_ALL }, 618 { "r15", 15, PROCESSOR_ALL }, 619 { "r16", 16, PROCESSOR_ALL }, 620 { "r17", 17, PROCESSOR_ALL }, 621 { "r18", 18, PROCESSOR_ALL }, 622 { "r19", 19, PROCESSOR_ALL }, 623 { "r2", 2, PROCESSOR_ALL }, 624 { "r20", 20, PROCESSOR_ALL }, 625 { "r21", 21, PROCESSOR_ALL }, 626 { "r22", 22, PROCESSOR_ALL }, 627 { "r23", 23, PROCESSOR_ALL }, 628 { "r24", 24, PROCESSOR_ALL }, 629 { "r25", 25, PROCESSOR_ALL }, 630 { "r26", 26, PROCESSOR_ALL }, 631 { "r27", 27, PROCESSOR_ALL }, 632 { "r28", 28, PROCESSOR_ALL }, 633 { "r29", 29, PROCESSOR_ALL }, 634 { "r3", 3, PROCESSOR_ALL }, 635 { "r30", 30, PROCESSOR_ALL }, 636 { "r31", 31, PROCESSOR_ALL }, 637 { "r4", 4, PROCESSOR_ALL }, 638 { "r5", 5, PROCESSOR_ALL }, 639 { "r6", 6, PROCESSOR_ALL }, 640 { "r7", 7, PROCESSOR_ALL }, 641 { "r8", 8, PROCESSOR_ALL }, 642 { "r9", 9, PROCESSOR_ALL }, 643 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */ 644 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */ 645 { "zero", 0, PROCESSOR_ALL }, 646 }; 647 648 #define REG_NAME_CNT \ 649 (sizeof (pre_defined_registers) / sizeof (struct reg_name)) 650 651 static const struct reg_name system_registers[] = 652 { 653 { "asid", 23, PROCESSOR_NOT_V850 }, 654 { "bpam", 25, PROCESSOR_NOT_V850 }, 655 { "bpav", 24, PROCESSOR_NOT_V850 }, 656 { "bpc", 22, PROCESSOR_NOT_V850 }, 657 { "bpdm", 27, PROCESSOR_NOT_V850 }, 658 { "bpdv", 26, PROCESSOR_NOT_V850 }, 659 { "bsel", 31, PROCESSOR_V850E2_UP }, 660 { "cfg", 7, PROCESSOR_V850E2V3_UP }, 661 { "ctbp", 20, PROCESSOR_NOT_V850 }, 662 { "ctpc", 16, PROCESSOR_NOT_V850 }, 663 { "ctpsw", 17, PROCESSOR_NOT_V850 }, 664 { "dbic", 15, PROCESSOR_V850E2_UP }, 665 { "dbpc", 18, PROCESSOR_NOT_V850 }, 666 { "dbpsw", 19, PROCESSOR_NOT_V850 }, 667 { "dbwr", 30, PROCESSOR_V850E2_UP }, 668 { "dir", 21, PROCESSOR_NOT_V850 }, 669 { "dpa0l", 16, PROCESSOR_V850E2V3_UP }, 670 { "dpa0u", 17, PROCESSOR_V850E2V3_UP }, 671 { "dpa1l", 18, PROCESSOR_V850E2V3_UP }, 672 { "dpa1u", 19, PROCESSOR_V850E2V3_UP }, 673 { "dpa2l", 20, PROCESSOR_V850E2V3_UP }, 674 { "dpa2u", 21, PROCESSOR_V850E2V3_UP }, 675 { "dpa3l", 22, PROCESSOR_V850E2V3_UP }, 676 { "dpa3u", 23, PROCESSOR_V850E2V3_UP }, 677 { "dpa4l", 24, PROCESSOR_V850E2V3_UP }, 678 { "dpa4u", 25, PROCESSOR_V850E2V3_UP }, 679 { "dpa5l", 26, PROCESSOR_V850E2V3_UP }, 680 { "dpa5u", 27, PROCESSOR_V850E2V3_UP }, 681 { "ecr", 4, PROCESSOR_ALL }, 682 { "eh_base", 3, PROCESSOR_V850E2V3_UP }, 683 { "eh_cfg", 1, PROCESSOR_V850E2V3_UP }, 684 { "eh_reset", 2, PROCESSOR_V850E2V3_UP }, 685 { "eiic", 13, PROCESSOR_V850E2_UP }, 686 { "eipc", 0, PROCESSOR_ALL }, 687 { "eipsw", 1, PROCESSOR_ALL }, 688 { "eiwr", 28, PROCESSOR_V850E2_UP }, 689 { "feic", 14, PROCESSOR_V850E2_UP }, 690 { "fepc", 2, PROCESSOR_ALL }, 691 { "fepsw", 3, PROCESSOR_ALL }, 692 { "fewr", 29, PROCESSOR_V850E2_UP }, 693 { "fpcc", 9, PROCESSOR_V850E2V3_UP }, 694 { "fpcfg", 10, PROCESSOR_V850E2V3_UP }, 695 { "fpec", 11, PROCESSOR_V850E2V3_UP }, 696 { "fpepc", 7, PROCESSOR_V850E2V3_UP }, 697 { "fpspc", 27, PROCESSOR_V850E2V3_UP }, 698 { "fpsr", 6, PROCESSOR_V850E2V3_UP }, 699 { "fpst", 8, PROCESSOR_V850E2V3_UP }, 700 { "ipa0l", 6, PROCESSOR_V850E2V3_UP }, 701 { "ipa0u", 7, PROCESSOR_V850E2V3_UP }, 702 { "ipa1l", 8, PROCESSOR_V850E2V3_UP }, 703 { "ipa1u", 9, PROCESSOR_V850E2V3_UP }, 704 { "ipa2l", 10, PROCESSOR_V850E2V3_UP }, 705 { "ipa2u", 11, PROCESSOR_V850E2V3_UP }, 706 { "ipa3l", 12, PROCESSOR_V850E2V3_UP }, 707 { "ipa3u", 13, PROCESSOR_V850E2V3_UP }, 708 { "ipa4l", 14, PROCESSOR_V850E2V3_UP }, 709 { "ipa4u", 15, PROCESSOR_V850E2V3_UP }, 710 { "mca", 24, PROCESSOR_V850E2V3_UP }, 711 { "mcc", 26, PROCESSOR_V850E2V3_UP }, 712 { "mcr", 27, PROCESSOR_V850E2V3_UP }, 713 { "mcs", 25, PROCESSOR_V850E2V3_UP }, 714 { "mpc", 1, PROCESSOR_V850E2V3_UP }, 715 { "mpm", 0, PROCESSOR_V850E2V3_UP }, 716 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP }, 717 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP }, 718 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP }, 719 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP }, 720 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP }, 721 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP }, 722 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP }, 723 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP }, 724 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP }, 725 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP }, 726 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP }, 727 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP }, 728 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP }, 729 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP }, 730 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP }, 731 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP }, 732 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP }, 733 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP }, 734 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP }, 735 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP }, 736 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP }, 737 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP }, 738 { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP }, 739 { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP }, 740 { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP }, 741 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP }, 742 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP }, 743 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP }, 744 { "pid", 6, PROCESSOR_V850E2V3_UP }, 745 { "pmcr0", 4, PROCESSOR_V850E2V3_UP }, 746 { "pmis2", 14, PROCESSOR_V850E2V3_UP }, 747 { "psw", 5, PROCESSOR_ALL }, 748 { "scbp", 12, PROCESSOR_V850E2V3_UP }, 749 { "sccfg", 11, PROCESSOR_V850E2V3_UP }, 750 { "sr0", 0, PROCESSOR_ALL }, 751 { "sr1", 1, PROCESSOR_ALL }, 752 { "sr10", 10, PROCESSOR_ALL }, 753 { "sr11", 11, PROCESSOR_ALL }, 754 { "sr12", 12, PROCESSOR_ALL }, 755 { "sr13", 13, PROCESSOR_ALL }, 756 { "sr14", 14, PROCESSOR_ALL }, 757 { "sr15", 15, PROCESSOR_ALL }, 758 { "sr16", 16, PROCESSOR_ALL }, 759 { "sr17", 17, PROCESSOR_ALL }, 760 { "sr18", 18, PROCESSOR_ALL }, 761 { "sr19", 19, PROCESSOR_ALL }, 762 { "sr2", 2, PROCESSOR_ALL }, 763 { "sr20", 20, PROCESSOR_ALL }, 764 { "sr21", 21, PROCESSOR_ALL }, 765 { "sr22", 22, PROCESSOR_ALL }, 766 { "sr23", 23, PROCESSOR_ALL }, 767 { "sr24", 24, PROCESSOR_ALL }, 768 { "sr25", 25, PROCESSOR_ALL }, 769 { "sr26", 26, PROCESSOR_ALL }, 770 { "sr27", 27, PROCESSOR_ALL }, 771 { "sr28", 28, PROCESSOR_ALL }, 772 { "sr29", 29, PROCESSOR_ALL }, 773 { "sr3", 3, PROCESSOR_ALL }, 774 { "sr30", 30, PROCESSOR_ALL }, 775 { "sr31", 31, PROCESSOR_ALL }, 776 { "sr4", 4, PROCESSOR_ALL }, 777 { "sr5", 5, PROCESSOR_ALL }, 778 { "sr6", 6, PROCESSOR_ALL }, 779 { "sr7", 7, PROCESSOR_ALL }, 780 { "sr8", 8, PROCESSOR_ALL }, 781 { "sr9", 9, PROCESSOR_ALL }, 782 { "sw_base", 3, PROCESSOR_V850E2V3_UP }, 783 { "sw_cfg", 1, PROCESSOR_V850E2V3_UP }, 784 { "sw_ctl", 0, PROCESSOR_V850E2V3_UP }, 785 { "tid", 2, PROCESSOR_V850E2V3_UP }, 786 { "vmadr", 6, PROCESSOR_V850E2V3_UP }, 787 { "vmecr", 4, PROCESSOR_V850E2V3_UP }, 788 { "vmtid", 5, PROCESSOR_V850E2V3_UP }, 789 { "vsadr", 2, PROCESSOR_V850E2V3_UP }, 790 { "vsecr", 0, PROCESSOR_V850E2V3_UP }, 791 { "vstid", 1, PROCESSOR_V850E2V3_UP }, 792 }; 793 794 #define SYSREG_NAME_CNT \ 795 (sizeof (system_registers) / sizeof (struct reg_name)) 796 797 798 static const struct reg_name cc_names[] = 799 { 800 { "c", 0x1, PROCESSOR_ALL }, 801 { "e", 0x2, PROCESSOR_ALL }, 802 { "ge", 0xe, PROCESSOR_ALL }, 803 { "gt", 0xf, PROCESSOR_ALL }, 804 { "h", 0xb, PROCESSOR_ALL }, 805 { "l", 0x1, PROCESSOR_ALL }, 806 { "le", 0x7, PROCESSOR_ALL }, 807 { "lt", 0x6, PROCESSOR_ALL }, 808 { "n", 0x4, PROCESSOR_ALL }, 809 { "nc", 0x9, PROCESSOR_ALL }, 810 { "ne", 0xa, PROCESSOR_ALL }, 811 { "nh", 0x3, PROCESSOR_ALL }, 812 { "nl", 0x9, PROCESSOR_ALL }, 813 { "ns", 0xc, PROCESSOR_ALL }, 814 { "nv", 0x8, PROCESSOR_ALL }, 815 { "nz", 0xa, PROCESSOR_ALL }, 816 { "p", 0xc, PROCESSOR_ALL }, 817 { "s", 0x4, PROCESSOR_ALL }, 818 #define COND_SA_NUM 0xd 819 { "sa", COND_SA_NUM, PROCESSOR_ALL }, 820 { "t", 0x5, PROCESSOR_ALL }, 821 { "v", 0x0, PROCESSOR_ALL }, 822 { "z", 0x2, PROCESSOR_ALL }, 823 }; 824 825 #define CC_NAME_CNT \ 826 (sizeof (cc_names) / sizeof (struct reg_name)) 827 828 static const struct reg_name float_cc_names[] = 829 { 830 { "eq", 0x2, PROCESSOR_V850E2V3_UP }, /* true. */ 831 { "f", 0x0, PROCESSOR_V850E2V3_UP }, /* true. */ 832 { "ge", 0xd, PROCESSOR_V850E2V3_UP }, /* false. */ 833 { "gl", 0xb, PROCESSOR_V850E2V3_UP }, /* false. */ 834 { "gle", 0x9, PROCESSOR_V850E2V3_UP }, /* false. */ 835 { "gt", 0xf, PROCESSOR_V850E2V3_UP }, /* false. */ 836 { "le", 0xe, PROCESSOR_V850E2V3_UP }, /* true. */ 837 { "lt", 0xc, PROCESSOR_V850E2V3_UP }, /* true. */ 838 { "neq", 0x2, PROCESSOR_V850E2V3_UP }, /* false. */ 839 { "nge", 0xd, PROCESSOR_V850E2V3_UP }, /* true. */ 840 { "ngl", 0xb, PROCESSOR_V850E2V3_UP }, /* true. */ 841 { "ngle",0x9, PROCESSOR_V850E2V3_UP }, /* true. */ 842 { "ngt", 0xf, PROCESSOR_V850E2V3_UP }, /* true. */ 843 { "nle", 0xe, PROCESSOR_V850E2V3_UP }, /* false. */ 844 { "nlt", 0xc, PROCESSOR_V850E2V3_UP }, /* false. */ 845 { "oge", 0x5, PROCESSOR_V850E2V3_UP }, /* false. */ 846 { "ogl", 0x3, PROCESSOR_V850E2V3_UP }, /* false. */ 847 { "ogt", 0x7, PROCESSOR_V850E2V3_UP }, /* false. */ 848 { "ole", 0x6, PROCESSOR_V850E2V3_UP }, /* true. */ 849 { "olt", 0x4, PROCESSOR_V850E2V3_UP }, /* true. */ 850 { "or", 0x1, PROCESSOR_V850E2V3_UP }, /* false. */ 851 { "seq", 0xa, PROCESSOR_V850E2V3_UP }, /* true. */ 852 { "sf", 0x8, PROCESSOR_V850E2V3_UP }, /* true. */ 853 { "sne", 0xa, PROCESSOR_V850E2V3_UP }, /* false. */ 854 { "st", 0x8, PROCESSOR_V850E2V3_UP }, /* false. */ 855 { "t", 0x0, PROCESSOR_V850E2V3_UP }, /* false. */ 856 { "ueq", 0x3, PROCESSOR_V850E2V3_UP }, /* true. */ 857 { "uge", 0x4, PROCESSOR_V850E2V3_UP }, /* false. */ 858 { "ugt", 0x6, PROCESSOR_V850E2V3_UP }, /* false. */ 859 { "ule", 0x7, PROCESSOR_V850E2V3_UP }, /* true. */ 860 { "ult", 0x5, PROCESSOR_V850E2V3_UP }, /* true. */ 861 { "un", 0x1, PROCESSOR_V850E2V3_UP }, /* true. */ 862 }; 863 864 #define FLOAT_CC_NAME_CNT \ 865 (sizeof (float_cc_names) / sizeof (struct reg_name)) 866 867 868 static const struct reg_name cacheop_names[] = 869 { 870 { "cfald", 0x44, PROCESSOR_V850E3V5_UP }, 871 { "cfali", 0x40, PROCESSOR_V850E3V5_UP }, 872 { "chbid", 0x04, PROCESSOR_V850E3V5_UP }, 873 { "chbii", 0x00, PROCESSOR_V850E3V5_UP }, 874 { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP }, 875 { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP }, 876 { "cibid", 0x24, PROCESSOR_V850E3V5_UP }, 877 { "cibii", 0x20, PROCESSOR_V850E3V5_UP }, 878 { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP }, 879 { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP }, 880 { "cildd", 0x65, PROCESSOR_V850E3V5_UP }, 881 { "cildi", 0x61, PROCESSOR_V850E3V5_UP }, 882 { "cistd", 0x64, PROCESSOR_V850E3V5_UP }, 883 { "cisti", 0x60, PROCESSOR_V850E3V5_UP }, 884 }; 885 886 #define CACHEOP_NAME_CNT \ 887 (sizeof (cacheop_names) / sizeof (struct reg_name)) 888 889 static const struct reg_name prefop_names[] = 890 { 891 { "prefd", 0x04, PROCESSOR_V850E3V5_UP }, 892 { "prefi", 0x00, PROCESSOR_V850E3V5_UP }, 893 }; 894 895 #define PREFOP_NAME_CNT \ 896 (sizeof (prefop_names) / sizeof (struct reg_name)) 897 898 static const struct reg_name vector_registers[] = 899 { 900 { "vr0", 0, PROCESSOR_V850E3V5_UP }, 901 { "vr1", 1, PROCESSOR_V850E3V5_UP }, 902 { "vr10", 10, PROCESSOR_V850E3V5_UP }, 903 { "vr11", 11, PROCESSOR_V850E3V5_UP }, 904 { "vr12", 12, PROCESSOR_V850E3V5_UP }, 905 { "vr13", 13, PROCESSOR_V850E3V5_UP }, 906 { "vr14", 14, PROCESSOR_V850E3V5_UP }, 907 { "vr15", 15, PROCESSOR_V850E3V5_UP }, 908 { "vr16", 16, PROCESSOR_V850E3V5_UP }, 909 { "vr17", 17, PROCESSOR_V850E3V5_UP }, 910 { "vr18", 18, PROCESSOR_V850E3V5_UP }, 911 { "vr19", 19, PROCESSOR_V850E3V5_UP }, 912 { "vr2", 2, PROCESSOR_V850E3V5_UP }, 913 { "vr20", 20, PROCESSOR_V850E3V5_UP }, 914 { "vr21", 21, PROCESSOR_V850E3V5_UP }, 915 { "vr22", 22, PROCESSOR_V850E3V5_UP }, 916 { "vr23", 23, PROCESSOR_V850E3V5_UP }, 917 { "vr24", 24, PROCESSOR_V850E3V5_UP }, 918 { "vr25", 25, PROCESSOR_V850E3V5_UP }, 919 { "vr26", 26, PROCESSOR_V850E3V5_UP }, 920 { "vr27", 27, PROCESSOR_V850E3V5_UP }, 921 { "vr28", 28, PROCESSOR_V850E3V5_UP }, 922 { "vr29", 29, PROCESSOR_V850E3V5_UP }, 923 { "vr3", 3, PROCESSOR_V850E3V5_UP }, 924 { "vr30", 30, PROCESSOR_V850E3V5_UP }, 925 { "vr31", 31, PROCESSOR_V850E3V5_UP }, 926 { "vr4", 4, PROCESSOR_V850E3V5_UP }, 927 { "vr5", 5, PROCESSOR_V850E3V5_UP }, 928 { "vr6", 6, PROCESSOR_V850E3V5_UP }, 929 { "vr7", 7, PROCESSOR_V850E3V5_UP }, 930 { "vr8", 8, PROCESSOR_V850E3V5_UP }, 931 { "vr9", 9, PROCESSOR_V850E3V5_UP }, 932 }; 933 934 #define VREG_NAME_CNT \ 935 (sizeof (vector_registers) / sizeof (struct reg_name)) 936 937 /* Do a binary search of the given register table to see if NAME is a 938 valid regiter name. Return the register number from the array on 939 success, or -1 on failure. */ 940 941 static int 942 reg_name_search (const struct reg_name *regs, 943 int regcount, 944 const char *name, 945 bfd_boolean accept_numbers) 946 { 947 int middle, low, high; 948 int cmp; 949 symbolS *symbolP; 950 951 /* If the register name is a symbol, then evaluate it. */ 952 if ((symbolP = symbol_find (name)) != NULL) 953 { 954 /* If the symbol is an alias for another name then use that. 955 If the symbol is an alias for a number, then return the number. */ 956 if (symbol_equated_p (symbolP)) 957 name 958 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol); 959 else if (accept_numbers) 960 { 961 int reg = S_GET_VALUE (symbolP); 962 return reg; 963 } 964 965 /* Otherwise drop through and try parsing name normally. */ 966 } 967 968 low = 0; 969 high = regcount - 1; 970 971 do 972 { 973 middle = (low + high) / 2; 974 cmp = strcasecmp (name, regs[middle].name); 975 if (cmp < 0) 976 high = middle - 1; 977 else if (cmp > 0) 978 low = middle + 1; 979 else 980 return ((regs[middle].processors & processor_mask) 981 ? regs[middle].value 982 : -1); 983 } 984 while (low <= high); 985 return -1; 986 } 987 988 /* Summary of register_name(). 989 990 in: Input_line_pointer points to 1st char of operand. 991 992 out: An expressionS. 993 The operand may have been a register: in this case, X_op == O_register, 994 X_add_number is set to the register number, and truth is returned. 995 Input_line_pointer->(next non-blank) char after operand, or is in 996 its original state. */ 997 998 static bfd_boolean 999 register_name (expressionS *expressionP) 1000 { 1001 int reg_number; 1002 char *name; 1003 char *start; 1004 char c; 1005 1006 /* Find the spelling of the operand. */ 1007 start = name = input_line_pointer; 1008 1009 c = get_symbol_end (); 1010 1011 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT, 1012 name, FALSE); 1013 1014 /* Put back the delimiting char. */ 1015 *input_line_pointer = c; 1016 1017 expressionP->X_add_symbol = NULL; 1018 expressionP->X_op_symbol = NULL; 1019 1020 /* Look to see if it's in the register table. */ 1021 if (reg_number >= 0) 1022 { 1023 expressionP->X_op = O_register; 1024 expressionP->X_add_number = reg_number; 1025 1026 return TRUE; 1027 } 1028 1029 /* Reset the line as if we had not done anything. */ 1030 input_line_pointer = start; 1031 1032 expressionP->X_op = O_illegal; 1033 1034 return FALSE; 1035 } 1036 1037 /* Summary of system_register_name(). 1038 1039 in: INPUT_LINE_POINTER points to 1st char of operand. 1040 EXPRESSIONP points to an expression structure to be filled in. 1041 ACCEPT_NUMBERS is true iff numerical register names may be used. 1042 1043 out: An expressionS structure in expressionP. 1044 The operand may have been a register: in this case, X_op == O_register, 1045 X_add_number is set to the register number, and truth is returned. 1046 Input_line_pointer->(next non-blank) char after operand, or is in 1047 its original state. */ 1048 1049 static bfd_boolean 1050 system_register_name (expressionS *expressionP, 1051 bfd_boolean accept_numbers) 1052 { 1053 int reg_number; 1054 char *name; 1055 char *start; 1056 char c; 1057 1058 /* Find the spelling of the operand. */ 1059 start = name = input_line_pointer; 1060 1061 c = get_symbol_end (); 1062 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name, 1063 accept_numbers); 1064 1065 /* Put back the delimiting char. */ 1066 *input_line_pointer = c; 1067 1068 if (reg_number < 0 1069 && accept_numbers) 1070 { 1071 /* Reset input_line pointer. */ 1072 input_line_pointer = start; 1073 1074 if (ISDIGIT (*input_line_pointer)) 1075 { 1076 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1077 } 1078 } 1079 1080 expressionP->X_add_symbol = NULL; 1081 expressionP->X_op_symbol = NULL; 1082 1083 /* Look to see if it's in the register table. */ 1084 if (reg_number >= 0) 1085 { 1086 expressionP->X_op = O_register; 1087 expressionP->X_add_number = reg_number; 1088 1089 return TRUE; 1090 } 1091 1092 /* Reset the line as if we had not done anything. */ 1093 input_line_pointer = start; 1094 1095 expressionP->X_op = O_illegal; 1096 1097 return FALSE; 1098 } 1099 1100 /* Summary of cc_name(). 1101 1102 in: INPUT_LINE_POINTER points to 1st char of operand. 1103 1104 out: An expressionS. 1105 The operand may have been a register: in this case, X_op == O_register, 1106 X_add_number is set to the register number, and truth is returned. 1107 Input_line_pointer->(next non-blank) char after operand, or is in 1108 its original state. */ 1109 1110 static bfd_boolean 1111 cc_name (expressionS *expressionP, 1112 bfd_boolean accept_numbers) 1113 { 1114 int reg_number; 1115 char *name; 1116 char *start; 1117 char c; 1118 1119 /* Find the spelling of the operand. */ 1120 start = name = input_line_pointer; 1121 1122 c = get_symbol_end (); 1123 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers); 1124 1125 /* Put back the delimiting char. */ 1126 *input_line_pointer = c; 1127 1128 if (reg_number < 0 1129 && accept_numbers) 1130 { 1131 /* Reset input_line pointer. */ 1132 input_line_pointer = start; 1133 1134 if (ISDIGIT (*input_line_pointer)) 1135 { 1136 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1137 } 1138 } 1139 1140 expressionP->X_add_symbol = NULL; 1141 expressionP->X_op_symbol = NULL; 1142 1143 /* Look to see if it's in the register table. */ 1144 if (reg_number >= 0) 1145 { 1146 expressionP->X_op = O_constant; 1147 expressionP->X_add_number = reg_number; 1148 1149 return TRUE; 1150 } 1151 1152 /* Reset the line as if we had not done anything. */ 1153 input_line_pointer = start; 1154 1155 expressionP->X_op = O_illegal; 1156 expressionP->X_add_number = 0; 1157 1158 return FALSE; 1159 } 1160 1161 static bfd_boolean 1162 float_cc_name (expressionS *expressionP, 1163 bfd_boolean accept_numbers) 1164 { 1165 int reg_number; 1166 char *name; 1167 char *start; 1168 char c; 1169 1170 /* Find the spelling of the operand. */ 1171 start = name = input_line_pointer; 1172 1173 c = get_symbol_end (); 1174 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers); 1175 1176 /* Put back the delimiting char. */ 1177 *input_line_pointer = c; 1178 1179 if (reg_number < 0 1180 && accept_numbers) 1181 { 1182 /* Reset input_line pointer. */ 1183 input_line_pointer = start; 1184 1185 if (ISDIGIT (*input_line_pointer)) 1186 { 1187 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1188 } 1189 } 1190 1191 expressionP->X_add_symbol = NULL; 1192 expressionP->X_op_symbol = NULL; 1193 1194 /* Look to see if it's in the register table. */ 1195 if (reg_number >= 0) 1196 { 1197 expressionP->X_op = O_constant; 1198 expressionP->X_add_number = reg_number; 1199 1200 return TRUE; 1201 } 1202 1203 /* Reset the line as if we had not done anything. */ 1204 input_line_pointer = start; 1205 1206 expressionP->X_op = O_illegal; 1207 expressionP->X_add_number = 0; 1208 1209 return FALSE; 1210 } 1211 1212 static bfd_boolean 1213 cacheop_name (expressionS * expressionP, 1214 bfd_boolean accept_numbers) 1215 { 1216 int reg_number; 1217 char *name; 1218 char *start; 1219 char c; 1220 1221 /* Find the spelling of the operand. */ 1222 start = name = input_line_pointer; 1223 1224 c = get_symbol_end (); 1225 reg_number = reg_name_search (cacheop_names, CACHEOP_NAME_CNT, name, accept_numbers); 1226 1227 /* Put back the delimiting char. */ 1228 *input_line_pointer = c; 1229 1230 if (reg_number < 0 1231 && accept_numbers) 1232 { 1233 /* Reset input_line pointer. */ 1234 input_line_pointer = start; 1235 1236 if (ISDIGIT (*input_line_pointer)) 1237 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1238 } 1239 1240 expressionP->X_add_symbol = NULL; 1241 expressionP->X_op_symbol = NULL; 1242 1243 /* Look to see if it's in the register table. */ 1244 if (reg_number >= 0) 1245 { 1246 expressionP->X_op = O_constant; 1247 expressionP->X_add_number = reg_number; 1248 1249 return TRUE; 1250 } 1251 1252 /* Reset the line as if we had not done anything. */ 1253 input_line_pointer = start; 1254 1255 expressionP->X_op = O_illegal; 1256 expressionP->X_add_number = 0; 1257 1258 return FALSE; 1259 } 1260 1261 static bfd_boolean 1262 prefop_name (expressionS * expressionP, 1263 bfd_boolean accept_numbers) 1264 { 1265 int reg_number; 1266 char *name; 1267 char *start; 1268 char c; 1269 1270 /* Find the spelling of the operand. */ 1271 start = name = input_line_pointer; 1272 1273 c = get_symbol_end (); 1274 reg_number = reg_name_search (prefop_names, PREFOP_NAME_CNT, name, accept_numbers); 1275 1276 /* Put back the delimiting char. */ 1277 *input_line_pointer = c; 1278 1279 if (reg_number < 0 1280 && accept_numbers) 1281 { 1282 /* Reset input_line pointer. */ 1283 input_line_pointer = start; 1284 1285 if (ISDIGIT (*input_line_pointer)) 1286 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1287 } 1288 1289 expressionP->X_add_symbol = NULL; 1290 expressionP->X_op_symbol = NULL; 1291 1292 /* Look to see if it's in the register table. */ 1293 if (reg_number >= 0) 1294 { 1295 expressionP->X_op = O_constant; 1296 expressionP->X_add_number = reg_number; 1297 1298 return TRUE; 1299 } 1300 1301 /* Reset the line as if we had not done anything. */ 1302 input_line_pointer = start; 1303 1304 expressionP->X_op = O_illegal; 1305 expressionP->X_add_number = 0; 1306 1307 return FALSE; 1308 } 1309 1310 static bfd_boolean 1311 vector_register_name (expressionS *expressionP) 1312 { 1313 int reg_number; 1314 char *name; 1315 char *start; 1316 char c; 1317 1318 /* Find the spelling of the operand. */ 1319 start = name = input_line_pointer; 1320 1321 c = get_symbol_end (); 1322 1323 reg_number = reg_name_search (vector_registers, VREG_NAME_CNT, 1324 name, FALSE); 1325 1326 /* Put back the delimiting char. */ 1327 *input_line_pointer = c; 1328 1329 expressionP->X_add_symbol = NULL; 1330 expressionP->X_op_symbol = NULL; 1331 1332 /* Look to see if it's in the register table. */ 1333 if (reg_number >= 0) 1334 { 1335 expressionP->X_op = O_register; 1336 expressionP->X_add_number = reg_number; 1337 1338 return TRUE; 1339 } 1340 1341 /* Reset the line as if we had not done anything. */ 1342 input_line_pointer = start; 1343 1344 expressionP->X_op = O_illegal; 1345 1346 return FALSE; 1347 } 1348 1349 static void 1350 skip_white_space (void) 1351 { 1352 while (*input_line_pointer == ' ' 1353 || *input_line_pointer == '\t') 1354 ++input_line_pointer; 1355 } 1356 1357 /* Summary of parse_register_list (). 1358 1359 in: INPUT_LINE_POINTER points to 1st char of a list of registers. 1360 INSN is the partially constructed instruction. 1361 OPERAND is the operand being inserted. 1362 1363 out: NULL if the parse completed successfully, otherwise a 1364 pointer to an error message is returned. If the parse 1365 completes the correct bit fields in the instruction 1366 will be filled in. 1367 1368 Parses register lists with the syntax: 1369 1370 { rX } 1371 { rX, rY } 1372 { rX - rY } 1373 { rX - rY, rZ } 1374 etc 1375 1376 and also parses constant expressions whoes bits indicate the 1377 registers in the lists. The LSB in the expression refers to 1378 the lowest numbered permissible register in the register list, 1379 and so on upwards. System registers are considered to be very 1380 high numbers. */ 1381 1382 static char * 1383 parse_register_list (unsigned long *insn, 1384 const struct v850_operand *operand) 1385 { 1386 static int type1_regs[32] = 1387 { 1388 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1389 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 1390 }; 1391 1392 int *regs; 1393 expressionS exp; 1394 1395 /* Select a register array to parse. */ 1396 switch (operand->shift) 1397 { 1398 case 0xffe00001: regs = type1_regs; break; 1399 default: 1400 as_bad (_("unknown operand shift: %x\n"), operand->shift); 1401 return _("internal failure in parse_register_list"); 1402 } 1403 1404 skip_white_space (); 1405 1406 /* If the expression starts with a curly brace it is a register list. 1407 Otherwise it is a constant expression, whoes bits indicate which 1408 registers are to be included in the list. */ 1409 if (*input_line_pointer != '{') 1410 { 1411 int reg; 1412 int i; 1413 1414 expression (&exp); 1415 1416 if (exp.X_op != O_constant) 1417 return _("constant expression or register list expected"); 1418 1419 if (regs == type1_regs) 1420 { 1421 if (exp.X_add_number & 0xFFFFF000) 1422 return _("high bits set in register list expression"); 1423 1424 for (reg = 20; reg < 32; reg++) 1425 if (exp.X_add_number & (1 << (reg - 20))) 1426 { 1427 for (i = 0; i < 32; i++) 1428 if (regs[i] == reg) 1429 *insn |= (1 << i); 1430 } 1431 } 1432 1433 return NULL; 1434 } 1435 1436 input_line_pointer++; 1437 1438 /* Parse the register list until a terminator (closing curly brace or 1439 new-line) is found. */ 1440 for (;;) 1441 { 1442 skip_white_space (); 1443 1444 if (register_name (&exp)) 1445 { 1446 int i; 1447 1448 /* Locate the given register in the list, and if it is there, 1449 insert the corresponding bit into the instruction. */ 1450 for (i = 0; i < 32; i++) 1451 { 1452 if (regs[i] == exp.X_add_number) 1453 { 1454 *insn |= (1 << i); 1455 break; 1456 } 1457 } 1458 1459 if (i == 32) 1460 return _("illegal register included in list"); 1461 } 1462 else if (system_register_name (&exp, TRUE)) 1463 { 1464 if (regs == type1_regs) 1465 { 1466 return _("system registers cannot be included in list"); 1467 } 1468 } 1469 1470 if (*input_line_pointer == '}') 1471 { 1472 input_line_pointer++; 1473 break; 1474 } 1475 else if (*input_line_pointer == ',') 1476 { 1477 input_line_pointer++; 1478 continue; 1479 } 1480 else if (*input_line_pointer == '-') 1481 { 1482 /* We have encountered a range of registers: rX - rY. */ 1483 int j; 1484 expressionS exp2; 1485 1486 /* Skip the dash. */ 1487 ++input_line_pointer; 1488 1489 /* Get the second register in the range. */ 1490 if (! register_name (&exp2)) 1491 { 1492 return _("second register should follow dash in register list"); 1493 } 1494 1495 if (exp.X_add_number > exp2.X_add_number) 1496 { 1497 return _("second register should be greater than first register"); 1498 } 1499 1500 /* Add the rest of the registers in the range. */ 1501 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++) 1502 { 1503 int i; 1504 1505 /* Locate the given register in the list, and if it is there, 1506 insert the corresponding bit into the instruction. */ 1507 for (i = 0; i < 32; i++) 1508 { 1509 if (regs[i] == j) 1510 { 1511 *insn |= (1 << i); 1512 break; 1513 } 1514 } 1515 1516 if (i == 32) 1517 return _("illegal register included in list"); 1518 } 1519 1520 exp = exp2; 1521 } 1522 else 1523 break; 1524 } 1525 1526 return NULL; 1527 } 1528 1529 const char *md_shortopts = "m:"; 1530 1531 struct option md_longopts[] = 1532 { 1533 #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE) 1534 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22}, 1535 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1) 1536 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, 1537 {NULL, no_argument, NULL, 0} 1538 }; 1539 1540 size_t md_longopts_size = sizeof (md_longopts); 1541 1542 void 1543 md_show_usage (FILE *stream) 1544 { 1545 fprintf (stream, _(" V850 options:\n")); 1546 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n")); 1547 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n")); 1548 fprintf (stream, _(" -mv850 The code is targeted at the v850\n")); 1549 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n")); 1550 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n")); 1551 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n")); 1552 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n")); 1553 fprintf (stream, _(" -mv850e2v4 Alias for -mv850e3v5\n")); 1554 fprintf (stream, _(" -mv850e3v5 The code is targeted at the v850e3v5\n")); 1555 fprintf (stream, _(" -mrelax Enable relaxation\n")); 1556 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n")); 1557 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n")); 1558 fprintf (stream, _(" -mextension enable extension opcode support\n")); 1559 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n")); 1560 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n")); 1561 fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n")); 1562 fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n")); 1563 fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n")); 1564 fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n")); 1565 } 1566 1567 int 1568 md_parse_option (int c, char *arg) 1569 { 1570 if (c != 'm') 1571 { 1572 switch (c) 1573 { 1574 case OPTION_DISP_SIZE_DEFAULT_22: 1575 default_disp_size = 22; 1576 return 1; 1577 1578 case OPTION_DISP_SIZE_DEFAULT_32: 1579 default_disp_size = 32; 1580 return 1; 1581 } 1582 return 0; 1583 } 1584 1585 if (strcmp (arg, "warn-signed-overflow") == 0) 1586 warn_signed_overflows = TRUE; 1587 1588 else if (strcmp (arg, "warn-unsigned-overflow") == 0) 1589 warn_unsigned_overflows = TRUE; 1590 1591 else if (strcmp (arg, "v850") == 0) 1592 { 1593 machine = 0; 1594 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); 1595 } 1596 else if (strcmp (arg, "v850e") == 0) 1597 { 1598 machine = bfd_mach_v850e; 1599 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); 1600 } 1601 else if (strcmp (arg, "v850e1") == 0) 1602 { 1603 machine = bfd_mach_v850e1; 1604 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); 1605 } 1606 else if (strcmp (arg, "v850e2") == 0) 1607 { 1608 machine = bfd_mach_v850e2; 1609 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); 1610 } 1611 else if (strcmp (arg, "v850e2v3") == 0) 1612 { 1613 machine = bfd_mach_v850e2v3; 1614 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); 1615 } 1616 else if (strcmp (arg, "v850e2v4") == 0) 1617 { 1618 machine = bfd_mach_v850e3v5; 1619 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1620 } 1621 else if (strcmp (arg, "v850e3v5") == 0) 1622 { 1623 machine = bfd_mach_v850e3v5; 1624 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1625 } 1626 else if (strcmp (arg, "extension") == 0) 1627 { 1628 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS; 1629 } 1630 else if (strcmp (arg, "no-bcond17") == 0) 1631 { 1632 no_bcond17 = 1; 1633 } 1634 else if (strcmp (arg, "no-stld23") == 0) 1635 { 1636 no_stld23 = 1; 1637 } 1638 else if (strcmp (arg, "relax") == 0) 1639 v850_relax = 1; 1640 else if (strcmp (arg, "gcc-abi") == 0) 1641 { 1642 v850_target_arch = bfd_arch_v850; 1643 v850_target_format = "elf32-v850"; 1644 } 1645 else if (strcmp (arg, "rh850-abi") == 0) 1646 { 1647 v850_target_arch = bfd_arch_v850_rh850; 1648 v850_target_format = "elf32-v850-rh850"; 1649 } 1650 else if (strcmp (arg, "8byte-align") == 0) 1651 v850_e_flags |= EF_RH850_DATA_ALIGN8; 1652 else if (strcmp (arg, "4byte-align") == 0) 1653 v850_e_flags &= ~ EF_RH850_DATA_ALIGN8; 1654 else 1655 return 0; 1656 1657 return 1; 1658 } 1659 1660 symbolS * 1661 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 1662 { 1663 return 0; 1664 } 1665 1666 char * 1667 md_atof (int type, char *litp, int *sizep) 1668 { 1669 return ieee_md_atof (type, litp, sizep, FALSE); 1670 } 1671 1672 /* Very gross. */ 1673 1674 void 1675 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 1676 asection *sec, 1677 fragS *fragP) 1678 { 1679 union u 1680 { 1681 bfd_reloc_code_real_type fx_r_type; 1682 char * fr_opcode; 1683 } 1684 opcode_converter; 1685 subseg_change (sec, 0); 1686 1687 opcode_converter.fr_opcode = fragP->fr_opcode; 1688 1689 subseg_change (sec, 0); 1690 1691 if (fragP->fr_subtype == SUBYPTE_LOOP_16_22) 1692 { 1693 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1694 fragP->fr_offset, 1, 1695 BFD_RELOC_UNUSED + opcode_converter.fx_r_type); 1696 fragP->fr_fix += 4; 1697 } 1698 else if (fragP->fr_subtype == SUBYPTE_LOOP_16_22 + 1) 1699 { 1700 unsigned char * buffer = 1701 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1702 int loop_reg = (buffer[0] & 0x1f); 1703 1704 /* Add -1.reg. */ 1705 md_number_to_chars ((char *) buffer, 0x025f | (loop_reg << 11), 2); 1706 /* Now create the conditional branch + fixup to the final target. */ 1707 /* 0x000107ea = bne LBL(disp17). */ 1708 md_number_to_chars ((char *) buffer + 2, 0x000107ea, 4); 1709 fix_new (fragP, fragP->fr_fix+2, 4, fragP->fr_symbol, 1710 fragP->fr_offset, 1, 1711 BFD_RELOC_V850_17_PCREL); 1712 fragP->fr_fix += 6; 1713 } 1714 /* In range conditional or unconditional branch. */ 1715 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 1716 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22 1717 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 1718 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 1719 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 1720 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 1721 || fragP->fr_subtype == SUBYPTE_SA_9_22 1722 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 1723 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 1724 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32) 1725 1726 { 1727 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 1728 fragP->fr_offset, 1, 1729 BFD_RELOC_UNUSED + opcode_converter.fx_r_type); 1730 fragP->fr_fix += 2; 1731 } 1732 /* V850e2r-v3 17bit conditional branch. */ 1733 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1 1734 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1 1735 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1 1736 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1) 1737 { 1738 unsigned char *buffer = 1739 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1740 1741 buffer[0] &= 0x0f; /* Use condition. */ 1742 buffer[0] |= 0xe0; 1743 buffer[1] = 0x07; 1744 1745 /* Now create the unconditional branch + fixup to the final 1746 target. */ 1747 md_number_to_chars ((char *) buffer + 2, 0x0001, 2); 1748 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1749 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL); 1750 fragP->fr_fix += 4; 1751 } 1752 /* Out of range conditional branch. Emit a branch around a 22bit jump. */ 1753 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1 1754 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1 1755 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2 1756 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2) 1757 { 1758 unsigned char *buffer = 1759 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1760 1761 /* Reverse the condition of the first branch. */ 1762 buffer[0] ^= 0x08; 1763 /* Mask off all the displacement bits. */ 1764 buffer[0] &= 0x8f; 1765 buffer[1] &= 0x07; 1766 /* Now set the displacement bits so that we branch 1767 around the unconditional branch. */ 1768 buffer[0] |= 0x30; 1769 1770 /* Now create the unconditional branch + fixup to the final 1771 target. */ 1772 md_number_to_chars ((char *) buffer + 2, 0x00000780, 4); 1773 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol, 1774 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1775 fragP->fr_fix += 6; 1776 } 1777 /* Out of range conditional branch. Emit a branch around a 32bit jump. */ 1778 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2 1779 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3) 1780 { 1781 unsigned char *buffer = 1782 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1783 1784 /* Reverse the condition of the first branch. */ 1785 buffer[0] ^= 0x08; 1786 /* Mask off all the displacement bits. */ 1787 buffer[0] &= 0x8f; 1788 buffer[1] &= 0x07; 1789 /* Now set the displacement bits so that we branch 1790 around the unconditional branch. */ 1791 buffer[0] |= 0x40; 1792 1793 /* Now create the unconditional branch + fixup to the final 1794 target. */ 1795 md_number_to_chars ((char *) buffer + 2, 0x02e0, 2); 1796 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1797 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1798 fragP->fr_fix += 8; 1799 } 1800 /* Out of range unconditional branch. Emit a 22bit jump. */ 1801 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1 1802 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1) 1803 { 1804 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4); 1805 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1806 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1807 fragP->fr_fix += 4; 1808 } 1809 /* Out of range unconditional branch. Emit a 32bit jump. */ 1810 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2) 1811 { 1812 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2); 1813 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1814 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1815 fragP->fr_fix += 6; 1816 } 1817 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */ 1818 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1 1819 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1 1820 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2 1821 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2) 1822 { 1823 unsigned char *buffer = 1824 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1825 1826 /* bsa .+4 */ 1827 buffer[0] &= 0x8f; 1828 buffer[0] |= 0x20; 1829 buffer[1] &= 0x07; 1830 1831 /* br .+6 */ 1832 md_number_to_chars ((char *) buffer + 2, 0x05b5, 2); 1833 1834 /* Now create the unconditional branch + fixup to the final 1835 target. */ 1836 /* jr SYM */ 1837 md_number_to_chars ((char *) buffer + 4, 0x00000780, 4); 1838 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1839 fragP->fr_offset, 1, 1840 BFD_RELOC_V850_22_PCREL); 1841 fragP->fr_fix += 8; 1842 } 1843 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */ 1844 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2 1845 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3) 1846 { 1847 unsigned char *buffer = 1848 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1849 1850 /* bsa .+2 */ 1851 buffer[0] &= 0x8f; 1852 buffer[0] |= 0x20; 1853 buffer[1] &= 0x07; 1854 1855 /* br .+8 */ 1856 md_number_to_chars ((char *) buffer + 2, 0x05c5, 2); 1857 1858 /* Now create the unconditional branch + fixup to the final 1859 target. */ 1860 /* jr SYM */ 1861 md_number_to_chars ((char *) buffer + 4, 0x02e0, 2); 1862 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol, 1863 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1864 1865 fragP->fr_fix += 10; 1866 } 1867 else 1868 abort (); 1869 } 1870 1871 valueT 1872 md_section_align (asection *seg, valueT addr) 1873 { 1874 int align = bfd_get_section_alignment (stdoutput, seg); 1875 return ((addr + (1 << align) - 1) & (-1 << align)); 1876 } 1877 1878 void 1879 md_begin (void) 1880 { 1881 char *prev_name = ""; 1882 const struct v850_opcode *op; 1883 1884 if (strncmp (TARGET_CPU, "v850e3v5", 8) == 0) 1885 { 1886 if (machine == -1) 1887 machine = bfd_mach_v850e3v5; 1888 1889 if (!processor_mask) 1890 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1891 } 1892 else if (strncmp (TARGET_CPU, "v850e2v4", 8) == 0) 1893 { 1894 if (machine == -1) 1895 machine = bfd_mach_v850e3v5; 1896 1897 if (!processor_mask) 1898 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1899 } 1900 else if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0) 1901 { 1902 if (machine == -1) 1903 machine = bfd_mach_v850e2v3; 1904 1905 if (!processor_mask) 1906 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); 1907 } 1908 else if (strncmp (TARGET_CPU, "v850e2", 6) == 0) 1909 { 1910 if (machine == -1) 1911 machine = bfd_mach_v850e2; 1912 1913 if (!processor_mask) 1914 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); 1915 } 1916 else if (strncmp (TARGET_CPU, "v850e1", 6) == 0) 1917 { 1918 if (machine == -1) 1919 machine = bfd_mach_v850e1; 1920 1921 if (!processor_mask) 1922 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); 1923 } 1924 else if (strncmp (TARGET_CPU, "v850e", 5) == 0) 1925 { 1926 if (machine == -1) 1927 machine = bfd_mach_v850e; 1928 1929 if (!processor_mask) 1930 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); 1931 } 1932 else if (strncmp (TARGET_CPU, "v850", 4) == 0) 1933 { 1934 if (machine == -1) 1935 machine = 0; 1936 1937 if (!processor_mask) 1938 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); 1939 } 1940 else 1941 /* xgettext:c-format */ 1942 as_bad (_("Unable to determine default target processor from string: %s"), 1943 TARGET_CPU); 1944 1945 v850_hash = hash_new (); 1946 1947 /* Insert unique names into hash table. The V850 instruction set 1948 has many identical opcode names that have different opcodes based 1949 on the operands. This hash table then provides a quick index to 1950 the first opcode with a particular name in the opcode table. */ 1951 op = v850_opcodes; 1952 while (op->name) 1953 { 1954 if (strcmp (prev_name, op->name)) 1955 { 1956 prev_name = (char *) op->name; 1957 hash_insert (v850_hash, op->name, (char *) op); 1958 } 1959 op++; 1960 } 1961 1962 v850_seg_table[BSS_SECTION].s = bss_section; 1963 bfd_set_arch_mach (stdoutput, v850_target_arch, machine); 1964 bfd_set_private_flags (stdoutput, v850_e_flags); 1965 } 1966 1967 1968 static bfd_reloc_code_real_type 1969 handle_hi016 (const struct v850_operand *operand, const char **errmsg) 1970 { 1971 if (operand == NULL) 1972 return BFD_RELOC_HI16; 1973 1974 if (operand->default_reloc == BFD_RELOC_HI16) 1975 return BFD_RELOC_HI16; 1976 1977 if (operand->default_reloc == BFD_RELOC_HI16_S) 1978 return BFD_RELOC_HI16; 1979 1980 if (operand->default_reloc == BFD_RELOC_16) 1981 return BFD_RELOC_HI16; 1982 1983 *errmsg = _("hi0() relocation used on an instruction which does " 1984 "not support it"); 1985 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1986 } 1987 1988 static bfd_reloc_code_real_type 1989 handle_hi16 (const struct v850_operand *operand, const char **errmsg) 1990 { 1991 if (operand == NULL) 1992 return BFD_RELOC_HI16_S; 1993 1994 if (operand->default_reloc == BFD_RELOC_HI16_S) 1995 return BFD_RELOC_HI16_S; 1996 1997 if (operand->default_reloc == BFD_RELOC_HI16) 1998 return BFD_RELOC_HI16_S; 1999 2000 if (operand->default_reloc == BFD_RELOC_16) 2001 return BFD_RELOC_HI16_S; 2002 2003 *errmsg = _("hi() relocation used on an instruction which does " 2004 "not support it"); 2005 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2006 } 2007 2008 static bfd_reloc_code_real_type 2009 handle_lo16 (const struct v850_operand *operand, const char **errmsg) 2010 { 2011 if (operand == NULL) 2012 return BFD_RELOC_LO16; 2013 2014 if (operand->default_reloc == BFD_RELOC_LO16) 2015 return BFD_RELOC_LO16; 2016 2017 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 2018 return BFD_RELOC_V850_LO16_SPLIT_OFFSET; 2019 2020 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2021 return BFD_RELOC_V850_LO16_S1; 2022 2023 if (operand->default_reloc == BFD_RELOC_16) 2024 return BFD_RELOC_LO16; 2025 2026 *errmsg = _("lo() relocation used on an instruction which does " 2027 "not support it"); 2028 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2029 } 2030 2031 static bfd_reloc_code_real_type 2032 handle_ctoff (const struct v850_operand *operand, const char **errmsg) 2033 { 2034 if (v850_target_arch == bfd_arch_v850_rh850) 2035 { 2036 *errmsg = _("ctoff() is not supported by the rh850 ABI. Use -mgcc-abi instead"); 2037 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2038 } 2039 2040 if (operand == NULL) 2041 return BFD_RELOC_V850_CALLT_16_16_OFFSET; 2042 2043 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET) 2044 return operand->default_reloc; 2045 2046 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2047 return BFD_RELOC_V850_CALLT_15_16_OFFSET; 2048 2049 if (operand->default_reloc == BFD_RELOC_16) 2050 return BFD_RELOC_V850_CALLT_16_16_OFFSET; 2051 2052 *errmsg = _("ctoff() relocation used on an instruction which does not support it"); 2053 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2054 } 2055 2056 static bfd_reloc_code_real_type 2057 handle_sdaoff (const struct v850_operand *operand, const char **errmsg) 2058 { 2059 if (operand == NULL) 2060 return BFD_RELOC_V850_SDA_16_16_OFFSET; 2061 2062 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 2063 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET; 2064 2065 if (operand->default_reloc == BFD_RELOC_16) 2066 return BFD_RELOC_V850_SDA_16_16_OFFSET; 2067 2068 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2069 return BFD_RELOC_V850_SDA_15_16_OFFSET; 2070 2071 *errmsg = _("sdaoff() relocation used on an instruction which does not support it"); 2072 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2073 } 2074 2075 static bfd_reloc_code_real_type 2076 handle_zdaoff (const struct v850_operand *operand, const char **errmsg) 2077 { 2078 if (operand == NULL) 2079 return BFD_RELOC_V850_ZDA_16_16_OFFSET; 2080 2081 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 2082 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET; 2083 2084 if (operand->default_reloc == BFD_RELOC_16) 2085 return BFD_RELOC_V850_ZDA_16_16_OFFSET; 2086 2087 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2088 return BFD_RELOC_V850_ZDA_15_16_OFFSET; 2089 2090 *errmsg = _("zdaoff() relocation used on an instruction which does not support it"); 2091 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2092 } 2093 2094 static bfd_reloc_code_real_type 2095 handle_tdaoff (const struct v850_operand *operand, const char **errmsg) 2096 { 2097 if (operand == NULL) 2098 /* Data item, not an instruction. */ 2099 return BFD_RELOC_V850_TDA_16_16_OFFSET; 2100 2101 switch (operand->default_reloc) 2102 { 2103 /* sld.hu, operand: D5-4. */ 2104 case BFD_RELOC_V850_TDA_4_5_OFFSET: 2105 /* sld.bu, operand: D4. */ 2106 case BFD_RELOC_V850_TDA_4_4_OFFSET: 2107 /* sld.w/sst.w, operand: D8_6. */ 2108 case BFD_RELOC_V850_TDA_6_8_OFFSET: 2109 /* sld.h/sst.h, operand: D8_7. */ 2110 case BFD_RELOC_V850_TDA_7_8_OFFSET: 2111 /* sld.b/sst.b, operand: D7. */ 2112 case BFD_RELOC_V850_TDA_7_7_OFFSET: 2113 return operand->default_reloc; 2114 default: 2115 break; 2116 } 2117 2118 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16) 2119 /* set1 & chums, operands: D16. */ 2120 return BFD_RELOC_V850_TDA_16_16_OFFSET; 2121 2122 *errmsg = _("tdaoff() relocation used on an instruction which does not support it"); 2123 /* Used to indicate an error condition. */ 2124 return BFD_RELOC_64; 2125 } 2126 2127 /* Warning: The code in this function relies upon the definitions 2128 in the v850_operands[] array (defined in opcodes/v850-opc.c) 2129 matching the hard coded values contained herein. */ 2130 2131 static bfd_reloc_code_real_type 2132 v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg) 2133 { 2134 bfd_boolean paren_skipped = FALSE; 2135 2136 /* Skip leading opening parenthesis. */ 2137 if (*input_line_pointer == '(') 2138 { 2139 ++input_line_pointer; 2140 paren_skipped = TRUE; 2141 } 2142 2143 #define CHECK_(name, reloc) \ 2144 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \ 2145 { \ 2146 input_line_pointer += strlen (name); \ 2147 return reloc; \ 2148 } 2149 2150 CHECK_ ("hi0", handle_hi016(operand, errmsg) ); 2151 CHECK_ ("hi", handle_hi16(operand, errmsg) ); 2152 CHECK_ ("lo", handle_lo16 (operand, errmsg) ); 2153 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg)); 2154 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg)); 2155 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg)); 2156 CHECK_ ("hilo", BFD_RELOC_32); 2157 CHECK_ ("lo23", BFD_RELOC_V850_23); 2158 CHECK_ ("ctoff", handle_ctoff (operand, errmsg) ); 2159 2160 /* Restore skipped parenthesis. */ 2161 if (paren_skipped) 2162 --input_line_pointer; 2163 2164 return BFD_RELOC_NONE; 2165 } 2166 2167 /* Insert an operand value into an instruction. */ 2168 2169 static unsigned long 2170 v850_insert_operand (unsigned long insn, 2171 const struct v850_operand *operand, 2172 offsetT val, 2173 const char **errmsg) 2174 { 2175 if (operand->insert) 2176 { 2177 const char *message = NULL; 2178 2179 insn = operand->insert (insn, val, &message); 2180 if (message != NULL) 2181 { 2182 if ((operand->flags & V850_OPERAND_SIGNED) 2183 && ! warn_signed_overflows 2184 && v850_msg_is_out_of_range (message)) 2185 { 2186 /* Skip warning... */ 2187 } 2188 else if ((operand->flags & V850_OPERAND_SIGNED) == 0 2189 && ! warn_unsigned_overflows 2190 && v850_msg_is_out_of_range (message)) 2191 { 2192 /* Skip warning... */ 2193 } 2194 else 2195 { 2196 if (errmsg != NULL) 2197 *errmsg = message; 2198 } 2199 } 2200 } 2201 else if (operand->bits == -1 2202 || operand->flags & V850E_IMMEDIATE16 2203 || operand->flags & V850E_IMMEDIATE23 2204 || operand->flags & V850E_IMMEDIATE32) 2205 { 2206 abort (); 2207 } 2208 else 2209 { 2210 if (operand->bits < 32) 2211 { 2212 long min, max; 2213 2214 if ((operand->flags & V850_OPERAND_SIGNED) != 0) 2215 { 2216 if (! warn_signed_overflows) 2217 max = (1 << operand->bits) - 1; 2218 else 2219 max = (1 << (operand->bits - 1)) - 1; 2220 2221 min = -(1 << (operand->bits - 1)); 2222 } 2223 else 2224 { 2225 max = (1 << operand->bits) - 1; 2226 2227 if (! warn_unsigned_overflows) 2228 min = -(1 << (operand->bits - 1)); 2229 else 2230 min = 0; 2231 } 2232 2233 /* Some people write constants with the sign extension done by 2234 hand but only up to 32 bits. This shouldn't really be valid, 2235 but, to permit this code to assemble on a 64-bit host, we 2236 sign extend the 32-bit value to 64 bits if so doing makes the 2237 value valid. */ 2238 if (val > max 2239 && (offsetT) (val - 0x80000000 - 0x80000000) >= min 2240 && (offsetT) (val - 0x80000000 - 0x80000000) <= max) 2241 val = val - 0x80000000 - 0x80000000; 2242 2243 /* Similarly, people write expressions like ~(1<<15), and expect 2244 this to be OK for a 32-bit unsigned value. */ 2245 else if (val < min 2246 && (offsetT) (val + 0x80000000 + 0x80000000) >= min 2247 && (offsetT) (val + 0x80000000 + 0x80000000) <= max) 2248 val = val + 0x80000000 + 0x80000000; 2249 2250 else if (val < (offsetT) min || val > (offsetT) max) 2251 { 2252 static char buf [128]; 2253 2254 /* Restore min and mix to expected values for decimal ranges. */ 2255 if ((operand->flags & V850_OPERAND_SIGNED) 2256 && ! warn_signed_overflows) 2257 max = (1 << (operand->bits - 1)) - 1; 2258 2259 if (! (operand->flags & V850_OPERAND_SIGNED) 2260 && ! warn_unsigned_overflows) 2261 min = 0; 2262 2263 sprintf (buf, _("operand out of range (%d is not between %d and %d)"), 2264 (int) val, (int) min, (int) max); 2265 *errmsg = buf; 2266 } 2267 2268 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift); 2269 } 2270 else 2271 { 2272 insn |= (((long) val) << operand->shift); 2273 } 2274 } 2275 2276 return insn; 2277 } 2278 2279 static char copy_of_instruction[128]; 2281 2282 void 2283 md_assemble (char *str) 2284 { 2285 char *s; 2286 char *start_of_operands; 2287 struct v850_opcode *opcode; 2288 struct v850_opcode *next_opcode; 2289 const unsigned char *opindex_ptr; 2290 int next_opindex; 2291 int relaxable = 0; 2292 unsigned long insn; 2293 unsigned long insn_size; 2294 char *f = NULL; 2295 int i; 2296 int match; 2297 bfd_boolean extra_data_after_insn = FALSE; 2298 unsigned extra_data_len = 0; 2299 unsigned long extra_data = 0; 2300 char *saved_input_line_pointer; 2301 char most_match_errmsg[1024]; 2302 int most_match_count = -1; 2303 2304 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1); 2305 most_match_errmsg[0] = 0; 2306 2307 /* Get the opcode. */ 2308 for (s = str; *s != '\0' && ! ISSPACE (*s); s++) 2309 continue; 2310 2311 if (*s != '\0') 2312 *s++ = '\0'; 2313 2314 /* Find the first opcode with the proper name. */ 2315 opcode = (struct v850_opcode *) hash_find (v850_hash, str); 2316 if (opcode == NULL) 2317 { 2318 /* xgettext:c-format */ 2319 as_bad (_("Unrecognized opcode: `%s'"), str); 2320 ignore_rest_of_line (); 2321 return; 2322 } 2323 2324 str = s; 2325 while (ISSPACE (*str)) 2326 ++str; 2327 2328 start_of_operands = str; 2329 2330 saved_input_line_pointer = input_line_pointer; 2331 2332 for (;;) 2333 { 2334 const char *errmsg = NULL; 2335 const char *warningmsg = NULL; 2336 2337 match = 0; 2338 opindex_ptr = opcode->operands; 2339 2340 if (no_stld23) 2341 { 2342 if ((strncmp (opcode->name, "st.", 3) == 0 2343 && v850_operands[opcode->operands[1]].bits == 23) 2344 || (strncmp (opcode->name, "ld.", 3) == 0 2345 && v850_operands[opcode->operands[0]].bits == 23)) 2346 { 2347 errmsg = _("st/ld offset 23 instruction was disabled ."); 2348 goto error; 2349 } 2350 } 2351 2352 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0 2353 || (((opcode->processors & ~PROCESSOR_MASK) != 0) 2354 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0))) 2355 { 2356 errmsg = _("Target processor does not support this instruction."); 2357 goto error; 2358 } 2359 2360 relaxable = 0; 2361 fc = 0; 2362 next_opindex = 0; 2363 insn = opcode->opcode; 2364 extra_data_len = 0; 2365 extra_data_after_insn = FALSE; 2366 2367 input_line_pointer = str = start_of_operands; 2368 2369 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) 2370 { 2371 const struct v850_operand *operand; 2372 char *hold; 2373 expressionS ex; 2374 bfd_reloc_code_real_type reloc; 2375 2376 if (next_opindex == 0) 2377 operand = &v850_operands[*opindex_ptr]; 2378 else 2379 { 2380 operand = &v850_operands[next_opindex]; 2381 next_opindex = 0; 2382 } 2383 2384 errmsg = NULL; 2385 2386 while (*str == ' ') 2387 ++str; 2388 2389 if (operand->flags & V850_OPERAND_BANG 2390 && *str == '!') 2391 ++str; 2392 else if (operand->flags & V850_OPERAND_PERCENT 2393 && *str == '%') 2394 ++str; 2395 2396 if (*str == ',' || *str == '[' || *str == ']') 2397 ++str; 2398 2399 while (*str == ' ') 2400 ++str; 2401 2402 if ( (strcmp (opcode->name, "pushsp") == 0 2403 || strcmp (opcode->name, "popsp") == 0 2404 || strcmp (opcode->name, "dbpush") == 0) 2405 && (*str == '-')) 2406 ++str; 2407 2408 if (operand->flags & V850_OPERAND_RELAX) 2409 relaxable = 1; 2410 2411 /* Gather the operand. */ 2412 hold = input_line_pointer; 2413 input_line_pointer = str; 2414 2415 /* lo(), hi(), hi0(), etc... */ 2416 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_NONE) 2417 { 2418 /* This is a fake reloc, used to indicate an error condition. */ 2419 if (reloc == BFD_RELOC_64) 2420 { 2421 /* match = 1; */ 2422 goto error; 2423 } 2424 2425 expression (&ex); 2426 2427 if (ex.X_op == O_constant) 2428 { 2429 switch (reloc) 2430 { 2431 case BFD_RELOC_V850_ZDA_16_16_OFFSET: 2432 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: 2433 case BFD_RELOC_V850_ZDA_15_16_OFFSET: 2434 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]" 2435 and the like. */ 2436 /* Fall through. */ 2437 2438 case BFD_RELOC_LO16: 2439 case BFD_RELOC_V850_LO16_S1: 2440 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 2441 { 2442 /* Truncate, then sign extend the value. */ 2443 ex.X_add_number = SEXT16 (ex.X_add_number); 2444 break; 2445 } 2446 2447 case BFD_RELOC_HI16: 2448 { 2449 /* Truncate, then sign extend the value. */ 2450 ex.X_add_number = SEXT16 (ex.X_add_number >> 16); 2451 break; 2452 } 2453 2454 case BFD_RELOC_HI16_S: 2455 { 2456 /* Truncate, then sign extend the value. */ 2457 int temp = (ex.X_add_number >> 16) & 0xffff; 2458 2459 temp += (ex.X_add_number >> 15) & 1; 2460 2461 ex.X_add_number = SEXT16 (temp); 2462 break; 2463 } 2464 2465 case BFD_RELOC_V850_23: 2466 if ((operand->flags & V850E_IMMEDIATE23) == 0) 2467 { 2468 errmsg = _("immediate operand is too large"); 2469 goto error; 2470 } 2471 break; 2472 2473 case BFD_RELOC_32: 2474 case BFD_RELOC_V850_32_ABS: 2475 case BFD_RELOC_V850_32_PCREL: 2476 if ((operand->flags & V850E_IMMEDIATE32) == 0) 2477 { 2478 errmsg = _("immediate operand is too large"); 2479 goto error; 2480 } 2481 2482 break; 2483 2484 default: 2485 as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc); 2486 break; 2487 } 2488 2489 if (operand->flags & V850E_IMMEDIATE32) 2490 { 2491 extra_data_after_insn = TRUE; 2492 extra_data_len = 4; 2493 extra_data = 0; 2494 } 2495 else if (operand->flags & V850E_IMMEDIATE23) 2496 { 2497 if (reloc != BFD_RELOC_V850_23) 2498 { 2499 errmsg = _("immediate operand is too large"); 2500 goto error; 2501 } 2502 extra_data_after_insn = TRUE; 2503 extra_data_len = 2; 2504 extra_data = 0; 2505 } 2506 else if ((operand->flags & V850E_IMMEDIATE16) 2507 || (operand->flags & V850E_IMMEDIATE16HI)) 2508 { 2509 if (operand->flags & V850E_IMMEDIATE16HI 2510 && reloc != BFD_RELOC_HI16 2511 && reloc != BFD_RELOC_HI16_S) 2512 { 2513 errmsg = _("immediate operand is too large"); 2514 goto error; 2515 } 2516 else if (operand->flags & V850E_IMMEDIATE16 2517 && reloc != BFD_RELOC_LO16) 2518 { 2519 errmsg = _("immediate operand is too large"); 2520 goto error; 2521 } 2522 2523 extra_data_after_insn = TRUE; 2524 extra_data_len = 2; 2525 extra_data = 0; 2526 } 2527 2528 if (fc > MAX_INSN_FIXUPS) 2529 as_fatal (_("too many fixups")); 2530 2531 fixups[fc].exp = ex; 2532 fixups[fc].opindex = *opindex_ptr; 2533 fixups[fc].reloc = reloc; 2534 fc++; 2535 } 2536 else /* ex.X_op != O_constant. */ 2537 { 2538 if ((reloc == BFD_RELOC_32 2539 || reloc == BFD_RELOC_V850_32_ABS 2540 || reloc == BFD_RELOC_V850_32_PCREL) 2541 && operand->bits < 32) 2542 { 2543 errmsg = _("immediate operand is too large"); 2544 goto error; 2545 } 2546 else if (reloc == BFD_RELOC_V850_23 2547 && (operand->flags & V850E_IMMEDIATE23) == 0) 2548 { 2549 errmsg = _("immediate operand is too large"); 2550 goto error; 2551 } 2552 else if ((reloc == BFD_RELOC_HI16 2553 || reloc == BFD_RELOC_HI16_S) 2554 && operand->bits < 16) 2555 { 2556 errmsg = _("immediate operand is too large"); 2557 goto error; 2558 } 2559 2560 if (operand->flags & V850E_IMMEDIATE32) 2561 { 2562 extra_data_after_insn = TRUE; 2563 extra_data_len = 4; 2564 extra_data = 0; 2565 } 2566 else if (operand->flags & V850E_IMMEDIATE23) 2567 { 2568 if (reloc != BFD_RELOC_V850_23) 2569 { 2570 errmsg = _("immediate operand is too large"); 2571 goto error; 2572 } 2573 extra_data_after_insn = TRUE; 2574 extra_data_len = 2; 2575 extra_data = 0; 2576 } 2577 else if ((operand->flags & V850E_IMMEDIATE16) 2578 || (operand->flags & V850E_IMMEDIATE16HI)) 2579 { 2580 if (operand->flags & V850E_IMMEDIATE16HI 2581 && reloc != BFD_RELOC_HI16 2582 && reloc != BFD_RELOC_HI16_S) 2583 { 2584 errmsg = _("immediate operand is too large"); 2585 goto error; 2586 } 2587 else if (operand->flags & V850E_IMMEDIATE16 2588 && reloc != BFD_RELOC_LO16) 2589 { 2590 errmsg = _("immediate operand is too large"); 2591 goto error; 2592 } 2593 2594 extra_data_after_insn = TRUE; 2595 extra_data_len = 2; 2596 extra_data = 0; 2597 } 2598 2599 if (fc > MAX_INSN_FIXUPS) 2600 as_fatal (_("too many fixups")); 2601 2602 fixups[fc].exp = ex; 2603 fixups[fc].opindex = *opindex_ptr; 2604 fixups[fc].reloc = reloc; 2605 fc++; 2606 } 2607 } 2608 else if (operand->flags & V850E_IMMEDIATE16 2609 || operand->flags & V850E_IMMEDIATE16HI) 2610 { 2611 expression (&ex); 2612 2613 switch (ex.X_op) 2614 { 2615 case O_constant: 2616 if (operand->flags & V850E_IMMEDIATE16HI) 2617 { 2618 if (ex.X_add_number & 0xffff) 2619 { 2620 errmsg = _("constant too big to fit into instruction"); 2621 goto error; 2622 } 2623 2624 ex.X_add_number >>= 16; 2625 } 2626 if (operand->flags & V850E_IMMEDIATE16) 2627 { 2628 if ((ex.X_add_number & 0xffff8000) 2629 && ((ex.X_add_number & 0xffff8000) != 0xffff8000)) 2630 { 2631 errmsg = _("constant too big to fit into instruction"); 2632 goto error; 2633 } 2634 } 2635 break; 2636 2637 case O_illegal: 2638 errmsg = _("illegal operand"); 2639 goto error; 2640 2641 case O_absent: 2642 errmsg = _("missing operand"); 2643 goto error; 2644 2645 default: 2646 if (fc >= MAX_INSN_FIXUPS) 2647 as_fatal (_("too many fixups")); 2648 2649 fixups[fc].exp = ex; 2650 fixups[fc].opindex = *opindex_ptr; 2651 fixups[fc].reloc = operand->default_reloc; 2652 ++fc; 2653 2654 ex.X_add_number = 0; 2655 break; 2656 } 2657 2658 extra_data_after_insn = TRUE; 2659 extra_data_len = 2; 2660 extra_data = ex.X_add_number; 2661 } 2662 else if (operand->flags & V850E_IMMEDIATE23) 2663 { 2664 expression (&ex); 2665 2666 switch (ex.X_op) 2667 { 2668 case O_constant: 2669 break; 2670 2671 case O_illegal: 2672 errmsg = _("illegal operand"); 2673 goto error; 2674 2675 case O_absent: 2676 errmsg = _("missing operand"); 2677 goto error; 2678 2679 default: 2680 break; 2681 } 2682 2683 if (fc >= MAX_INSN_FIXUPS) 2684 as_fatal (_("too many fixups")); 2685 2686 fixups[fc].exp = ex; 2687 fixups[fc].opindex = *opindex_ptr; 2688 fixups[fc].reloc = operand->default_reloc; 2689 ++fc; 2690 2691 extra_data_after_insn = TRUE; 2692 extra_data_len = 2; 2693 extra_data = 0; 2694 } 2695 else if (operand->flags & V850E_IMMEDIATE32) 2696 { 2697 expression (&ex); 2698 2699 switch (ex.X_op) 2700 { 2701 case O_constant: 2702 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS 2703 || operand->default_reloc == BFD_RELOC_V850_32_PCREL) 2704 && (ex.X_add_number & 1)) 2705 { 2706 errmsg = _("odd number cannot be used here"); 2707 goto error; 2708 } 2709 break; 2710 2711 case O_illegal: 2712 errmsg = _("illegal operand"); 2713 goto error; 2714 2715 case O_absent: 2716 errmsg = _("missing operand"); 2717 goto error; 2718 2719 default: 2720 if (fc >= MAX_INSN_FIXUPS) 2721 as_fatal (_("too many fixups")); 2722 2723 fixups[fc].exp = ex; 2724 fixups[fc].opindex = *opindex_ptr; 2725 fixups[fc].reloc = operand->default_reloc; 2726 ++fc; 2727 2728 ex.X_add_number = 0; 2729 break; 2730 } 2731 2732 extra_data_after_insn = TRUE; 2733 extra_data_len = 4; 2734 extra_data = ex.X_add_number; 2735 } 2736 else if (operand->flags & V850E_OPERAND_REG_LIST) 2737 { 2738 errmsg = parse_register_list (&insn, operand); 2739 2740 if (errmsg) 2741 goto error; 2742 } 2743 else 2744 { 2745 errmsg = NULL; 2746 2747 if ((operand->flags & V850_OPERAND_REG) != 0) 2748 { 2749 if (!register_name (&ex)) 2750 { 2751 errmsg = _("invalid register name"); 2752 } 2753 2754 if ((operand->flags & V850_NOT_R0) 2755 && ex.X_add_number == 0) 2756 { 2757 errmsg = _("register r0 cannot be used here"); 2758 } 2759 2760 if (operand->flags & V850_REG_EVEN) 2761 { 2762 if (ex.X_add_number % 2) 2763 errmsg = _("odd register cannot be used here"); 2764 ex.X_add_number = ex.X_add_number / 2; 2765 } 2766 2767 } 2768 else if ((operand->flags & V850_OPERAND_SRG) != 0) 2769 { 2770 if (!system_register_name (&ex, TRUE)) 2771 { 2772 errmsg = _("invalid system register name"); 2773 } 2774 } 2775 else if ((operand->flags & V850_OPERAND_EP) != 0) 2776 { 2777 char *start = input_line_pointer; 2778 char c = get_symbol_end (); 2779 2780 if (strcmp (start, "ep") != 0 && strcmp (start, "r30") != 0) 2781 { 2782 /* Put things back the way we found them. */ 2783 *input_line_pointer = c; 2784 input_line_pointer = start; 2785 errmsg = _("expected EP register"); 2786 goto error; 2787 } 2788 2789 *input_line_pointer = c; 2790 str = input_line_pointer; 2791 input_line_pointer = hold; 2792 2793 while (*str == ' ' || *str == ',' 2794 || *str == '[' || *str == ']') 2795 ++str; 2796 continue; 2797 } 2798 else if ((operand->flags & V850_OPERAND_CC) != 0) 2799 { 2800 if (!cc_name (&ex, TRUE)) 2801 { 2802 errmsg = _("invalid condition code name"); 2803 } 2804 2805 if ((operand->flags & V850_NOT_SA) 2806 && ex.X_add_number == COND_SA_NUM) 2807 { 2808 errmsg = _("condition sa cannot be used here"); 2809 } 2810 } 2811 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0) 2812 { 2813 if (!float_cc_name (&ex, TRUE)) 2814 { 2815 errmsg = _("invalid condition code name"); 2816 } 2817 } 2818 else if ((operand->flags & V850_OPERAND_CACHEOP) != 0) 2819 { 2820 if (!cacheop_name (&ex, TRUE)) 2821 errmsg = _("invalid cache oparation name"); 2822 } 2823 else if ((operand->flags & V850_OPERAND_PREFOP) != 0) 2824 { 2825 if (!prefop_name (&ex, TRUE)) 2826 errmsg = _("invalid pref oparation name"); 2827 } 2828 else if ((operand->flags & V850_OPERAND_VREG) != 0) 2829 { 2830 if (!vector_register_name (&ex)) 2831 errmsg = _("invalid vector register name"); 2832 } 2833 else if ((register_name (&ex) 2834 && (operand->flags & V850_OPERAND_REG) == 0)) 2835 { 2836 char c; 2837 int exists = 0; 2838 2839 /* It is possible that an alias has been defined that 2840 matches a register name. For example the code may 2841 include a ".set ZERO, 0" directive, which matches 2842 the register name "zero". Attempt to reparse the 2843 field as an expression, and only complain if we 2844 cannot generate a constant. */ 2845 2846 input_line_pointer = str; 2847 2848 c = get_symbol_end (); 2849 2850 if (symbol_find (str) != NULL) 2851 exists = 1; 2852 2853 *input_line_pointer = c; 2854 input_line_pointer = str; 2855 2856 expression (&ex); 2857 2858 if (ex.X_op != O_constant) 2859 { 2860 /* If this register is actually occurring too early on 2861 the parsing of the instruction, (because another 2862 field is missing) then report this. */ 2863 if (opindex_ptr[1] != 0 2864 && ((v850_operands[opindex_ptr[1]].flags 2865 & V850_OPERAND_REG) 2866 ||(v850_operands[opindex_ptr[1]].flags 2867 & V850_OPERAND_VREG))) 2868 errmsg = _("syntax error: value is missing before the register name"); 2869 else 2870 errmsg = _("syntax error: register not expected"); 2871 2872 /* If we created a symbol in the process of this 2873 test then delete it now, so that it will not 2874 be output with the real symbols... */ 2875 if (exists == 0 2876 && ex.X_op == O_symbol) 2877 symbol_remove (ex.X_add_symbol, 2878 &symbol_rootP, &symbol_lastP); 2879 } 2880 } 2881 else if (system_register_name (&ex, FALSE) 2882 && (operand->flags & V850_OPERAND_SRG) == 0) 2883 { 2884 errmsg = _("syntax error: system register not expected"); 2885 } 2886 else if (cc_name (&ex, FALSE) 2887 && (operand->flags & V850_OPERAND_CC) == 0) 2888 { 2889 errmsg = _("syntax error: condition code not expected"); 2890 } 2891 else if (float_cc_name (&ex, FALSE) 2892 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0) 2893 { 2894 errmsg = _("syntax error: condition code not expected"); 2895 } 2896 else if (vector_register_name (&ex) 2897 && (operand->flags & V850_OPERAND_VREG) == 0) 2898 { 2899 errmsg = _("syntax error: vector register not expected"); 2900 } 2901 else 2902 { 2903 expression (&ex); 2904 2905 if ((operand->flags & V850_NOT_IMM0) 2906 && ex.X_op == O_constant 2907 && ex.X_add_number == 0) 2908 { 2909 errmsg = _("immediate 0 cannot be used here"); 2910 } 2911 2912 /* Special case: 2913 If we are assembling a MOV/JARL/JR instruction and the immediate 2914 value does not fit into the bits available then create a 2915 fake error so that the next MOV/JARL/JR instruction will be 2916 selected. This one has a 32 bit immediate field. */ 2917 2918 if ((strcmp (opcode->name, "mov") == 0 2919 || strcmp (opcode->name, "jarl") == 0 2920 || strcmp (opcode->name, "jr") == 0) 2921 && ex.X_op == O_constant 2922 && (ex.X_add_number < (-(1 << (operand->bits - 1))) 2923 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) 2924 { 2925 errmsg = _("immediate operand is too large"); 2926 } 2927 2928 if ((strcmp (opcode->name, "jarl") == 0 2929 || strcmp (opcode->name, "jr") == 0) 2930 && ex.X_op != O_constant 2931 && operand->bits != default_disp_size) 2932 { 2933 errmsg = _("immediate operand is not match"); 2934 } 2935 2936 /* Special case2 : 2937 If we are assembling a ld/st instruction and the immediate 2938 value does not fit into the bits available then create a 2939 fake error so that the next ld/st instruction will be 2940 selected. */ 2941 if ( ( (strncmp (opcode->name, "st.", 3) == 0) 2942 || (strncmp (opcode->name, "ld.", 3) == 0)) 2943 && ex.X_op == O_constant 2944 && (ex.X_add_number < (-(1 << (operand->bits - 1))) 2945 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) 2946 errmsg = _("displacement is too large"); 2947 } 2948 2949 if (errmsg) 2950 goto error; 2951 2952 switch (ex.X_op) 2953 { 2954 case O_illegal: 2955 errmsg = _("illegal operand"); 2956 goto error; 2957 case O_absent: 2958 errmsg = _("missing operand"); 2959 goto error; 2960 case O_register: 2961 if ((operand->flags 2962 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0) 2963 { 2964 errmsg = _("invalid operand"); 2965 goto error; 2966 } 2967 2968 insn = v850_insert_operand (insn, operand, 2969 ex.X_add_number, 2970 &warningmsg); 2971 2972 break; 2973 2974 case O_constant: 2975 insn = v850_insert_operand (insn, operand, ex.X_add_number, 2976 &warningmsg); 2977 break; 2978 2979 default: 2980 /* We need to generate a fixup for this expression. */ 2981 if (fc >= MAX_INSN_FIXUPS) 2982 as_fatal (_("too many fixups")); 2983 2984 fixups[fc].exp = ex; 2985 fixups[fc].opindex = *opindex_ptr; 2986 fixups[fc].reloc = BFD_RELOC_NONE; 2987 ++fc; 2988 break; 2989 } 2990 } 2991 2992 str = input_line_pointer; 2993 input_line_pointer = hold; 2994 2995 while (*str == ' ' || *str == ',' || *str == '[' || *str == ']' 2996 || *str == ')') 2997 ++str; 2998 } 2999 3000 while (ISSPACE (*str)) 3001 ++str; 3002 3003 if (*str == '\0') 3004 match = 1; 3005 3006 error: 3007 if (match == 0) 3008 { 3009 if ((opindex_ptr - opcode->operands) >= most_match_count) 3010 { 3011 most_match_count = opindex_ptr - opcode->operands; 3012 if (errmsg != NULL) 3013 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1); 3014 } 3015 3016 next_opcode = opcode + 1; 3017 if (next_opcode->name != NULL 3018 && strcmp (next_opcode->name, opcode->name) == 0) 3019 { 3020 opcode = next_opcode; 3021 3022 /* Skip versions that are not supported by the target 3023 processor. */ 3024 if ((opcode->processors & processor_mask) == 0) 3025 goto error; 3026 3027 continue; 3028 } 3029 3030 if (most_match_errmsg[0] == 0) 3031 /* xgettext:c-format. */ 3032 as_bad (_("junk at end of line: `%s'"), str); 3033 else 3034 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg); 3035 3036 if (*input_line_pointer == ']') 3037 ++input_line_pointer; 3038 3039 ignore_rest_of_line (); 3040 input_line_pointer = saved_input_line_pointer; 3041 return; 3042 } 3043 3044 if (warningmsg != NULL) 3045 as_warn ("%s", warningmsg); 3046 break; 3047 } 3048 3049 input_line_pointer = str; 3050 3051 /* Tie dwarf2 debug info to the address at the start of the insn. 3052 We can't do this after the insn has been output as the current 3053 frag may have been closed off. eg. by frag_var. */ 3054 dwarf2_emit_insn (0); 3055 3056 /* Write out the instruction. */ 3057 3058 if (relaxable && fc > 0) 3059 { 3060 insn_size = 2; 3061 fc = 0; 3062 3063 if (strcmp (opcode->name, "loop") == 0) 3064 { 3065 if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22) 3066 { 3067 insn_size = 4; 3068 f = frag_var (rs_machine_dependent, 6, 2, SUBYPTE_LOOP_16_22, 3069 fixups[0].exp.X_add_symbol, 3070 fixups[0].exp.X_add_number, 3071 (char *)(size_t) fixups[0].opindex); 3072 md_number_to_chars (f, insn, insn_size); 3073 md_number_to_chars (f+4, 0, 4); 3074 } 3075 else 3076 { 3077 as_bad (_("loop: 32-bit displacement not supported")); 3078 } 3079 } 3080 else if (strcmp (opcode->name, "br") == 0 3081 || strcmp (opcode->name, "jbr") == 0) 3082 { 3083 if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22) 3084 { 3085 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22, 3086 fixups[0].exp.X_add_symbol, 3087 fixups[0].exp.X_add_number, 3088 (char *)(size_t) fixups[0].opindex); 3089 md_number_to_chars (f, insn, insn_size); 3090 md_number_to_chars (f + 2, 0, 2); 3091 } 3092 else 3093 { 3094 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32, 3095 fixups[0].exp.X_add_symbol, 3096 fixups[0].exp.X_add_number, 3097 (char *)(size_t) fixups[0].opindex); 3098 md_number_to_chars (f, insn, insn_size); 3099 md_number_to_chars (f + 2, 0, 4); 3100 } 3101 } 3102 else /* b<cond>, j<cond>. */ 3103 { 3104 if (default_disp_size == 22 3105 || (processor_mask & PROCESSOR_V850E2_UP) == 0) 3106 { 3107 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17) 3108 { 3109 if (strcmp (opcode->name, "bsa") == 0) 3110 { 3111 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22, 3112 fixups[0].exp.X_add_symbol, 3113 fixups[0].exp.X_add_number, 3114 (char *)(size_t) fixups[0].opindex); 3115 md_number_to_chars (f, insn, insn_size); 3116 md_number_to_chars (f + 2, 0, 6); 3117 } 3118 else 3119 { 3120 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22, 3121 fixups[0].exp.X_add_symbol, 3122 fixups[0].exp.X_add_number, 3123 (char *)(size_t) fixups[0].opindex); 3124 md_number_to_chars (f, insn, insn_size); 3125 md_number_to_chars (f + 2, 0, 4); 3126 } 3127 } 3128 else 3129 { 3130 if (strcmp (opcode->name, "bsa") == 0) 3131 { 3132 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22, 3133 fixups[0].exp.X_add_symbol, 3134 fixups[0].exp.X_add_number, 3135 (char *)(size_t) fixups[0].opindex); 3136 md_number_to_chars (f, insn, insn_size); 3137 md_number_to_chars (f + 2, 0, 6); 3138 } 3139 else 3140 { 3141 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22, 3142 fixups[0].exp.X_add_symbol, 3143 fixups[0].exp.X_add_number, 3144 (char *)(size_t) fixups[0].opindex); 3145 md_number_to_chars (f, insn, insn_size); 3146 md_number_to_chars (f + 2, 0, 4); 3147 } 3148 } 3149 } 3150 else 3151 { 3152 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17) 3153 { 3154 if (strcmp (opcode->name, "bsa") == 0) 3155 { 3156 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32, 3157 fixups[0].exp.X_add_symbol, 3158 fixups[0].exp.X_add_number, 3159 (char *)(size_t) fixups[0].opindex); 3160 md_number_to_chars (f, insn, insn_size); 3161 md_number_to_chars (f + 2, 0, 8); 3162 } 3163 else 3164 { 3165 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32, 3166 fixups[0].exp.X_add_symbol, 3167 fixups[0].exp.X_add_number, 3168 (char *)(size_t) fixups[0].opindex); 3169 md_number_to_chars (f, insn, insn_size); 3170 md_number_to_chars (f + 2, 0, 6); 3171 } 3172 } 3173 else 3174 { 3175 if (strcmp (opcode->name, "bsa") == 0) 3176 { 3177 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32, 3178 fixups[0].exp.X_add_symbol, 3179 fixups[0].exp.X_add_number, 3180 (char *)(size_t) fixups[0].opindex); 3181 md_number_to_chars (f, insn, insn_size); 3182 md_number_to_chars (f + 2, 0, 8); 3183 } 3184 else 3185 { 3186 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32, 3187 fixups[0].exp.X_add_symbol, 3188 fixups[0].exp.X_add_number, 3189 (char *)(size_t) fixups[0].opindex); 3190 md_number_to_chars (f, insn, insn_size); 3191 md_number_to_chars (f + 2, 0, 6); 3192 } 3193 } 3194 } 3195 } 3196 } 3197 else 3198 { 3199 /* Four byte insns have an opcode with the two high bits on. */ 3200 if ((insn & 0x0600) == 0x0600) 3201 insn_size = 4; 3202 else 3203 insn_size = 2; 3204 3205 /* Special case: 32 bit MOV. */ 3206 if ((insn & 0xffe0) == 0x0620) 3207 insn_size = 2; 3208 3209 /* Special case: 32 bit JARL,JMP,JR. */ 3210 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */ 3211 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */ 3212 || (insn & 0x1ffff) == 0x2e0) /* JR. */ 3213 insn_size = 2; 3214 3215 if (obstack_room (& frchain_now->frch_obstack) < (insn_size + extra_data_len)) 3216 { 3217 frag_wane (frag_now); 3218 frag_new (0); 3219 } 3220 3221 f = frag_more (insn_size); 3222 md_number_to_chars (f, insn, insn_size); 3223 3224 if (extra_data_after_insn) 3225 { 3226 f = frag_more (extra_data_len); 3227 md_number_to_chars (f, extra_data, extra_data_len); 3228 3229 extra_data_after_insn = FALSE; 3230 } 3231 } 3232 3233 /* Create any fixups. At this point we do not use a 3234 bfd_reloc_code_real_type, but instead just use the 3235 BFD_RELOC_UNUSED plus the operand index. This lets us easily 3236 handle fixups for any operand type, although that is admittedly 3237 not a very exciting feature. We pick a BFD reloc type in 3238 md_apply_fix. */ 3239 for (i = 0; i < fc; i++) 3240 { 3241 const struct v850_operand *operand; 3242 bfd_reloc_code_real_type reloc; 3243 3244 operand = &v850_operands[fixups[i].opindex]; 3245 3246 reloc = fixups[i].reloc; 3247 3248 if (reloc != BFD_RELOC_NONE) 3249 { 3250 reloc_howto_type *reloc_howto = 3251 bfd_reloc_type_lookup (stdoutput, reloc); 3252 int size; 3253 int address; 3254 fixS *fixP; 3255 3256 if (!reloc_howto) 3257 abort (); 3258 3259 size = bfd_get_reloc_size (reloc_howto); 3260 3261 /* XXX This will abort on an R_V850_8 reloc - 3262 is this reloc actually used? */ 3263 if (size != 2 && size != 4) 3264 abort (); 3265 3266 if (extra_data_len == 0) 3267 { 3268 address = (f - frag_now->fr_literal) + insn_size - size; 3269 } 3270 else 3271 { 3272 address = (f - frag_now->fr_literal) + extra_data_len - size; 3273 } 3274 3275 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL)) 3276 { 3277 fixups[i].exp.X_add_number += 2; 3278 } 3279 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) 3280 { 3281 fixups[i].exp.X_add_number += 2; 3282 address += 2; 3283 } 3284 3285 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */ 3286 fixP = fix_new_exp (frag_now, address, size, 3287 &fixups[i].exp, 3288 reloc_howto->pc_relative, 3289 reloc); 3290 3291 fixP->tc_fix_data = (void *) operand; 3292 3293 switch (reloc) 3294 { 3295 case BFD_RELOC_LO16: 3296 case BFD_RELOC_V850_LO16_S1: 3297 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 3298 case BFD_RELOC_HI16: 3299 case BFD_RELOC_HI16_S: 3300 fixP->fx_no_overflow = 1; 3301 break; 3302 default: 3303 break; 3304 } 3305 } 3306 else 3307 { 3308 gas_assert (f != NULL); 3309 fix_new_exp (frag_now, 3310 f - frag_now->fr_literal, 4, 3311 & fixups[i].exp, 3312 (operand->flags & V850_PCREL) != 0, 3313 (bfd_reloc_code_real_type) (fixups[i].opindex 3314 + (int) BFD_RELOC_UNUSED)); 3315 } 3316 } 3317 3318 input_line_pointer = saved_input_line_pointer; 3319 } 3320 3321 /* If while processing a fixup, a reloc really needs to be created 3322 then it is done here. */ 3323 3324 arelent * 3325 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) 3326 { 3327 arelent *reloc; 3328 3329 reloc = xmalloc (sizeof (arelent)); 3330 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 3331 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3332 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3333 3334 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY 3335 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3336 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL 3337 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP 3338 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN) 3339 reloc->addend = fixp->fx_offset; 3340 else 3341 { 3342 #if 0 3343 if (fixp->fx_r_type == BFD_RELOC_32 3344 && fixp->fx_pcrel) 3345 fixp->fx_r_type = BFD_RELOC_32_PCREL; 3346 #endif 3347 3348 reloc->addend = fixp->fx_addnumber; 3349 } 3350 3351 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 3352 3353 if (reloc->howto == NULL) 3354 { 3355 as_bad_where (fixp->fx_file, fixp->fx_line, 3356 /* xgettext:c-format */ 3357 _("reloc %d not supported by object file format"), 3358 (int) fixp->fx_r_type); 3359 3360 xfree (reloc); 3361 3362 return NULL; 3363 } 3364 3365 return reloc; 3366 } 3367 3368 void 3369 v850_handle_align (fragS * frag) 3370 { 3371 if (v850_relax 3372 && frag->fr_type == rs_align 3373 && frag->fr_address + frag->fr_fix > 0 3374 && frag->fr_offset > 1 3375 && now_seg != bss_section 3376 && now_seg != v850_seg_table[SBSS_SECTION].s 3377 && now_seg != v850_seg_table[TBSS_SECTION].s 3378 && now_seg != v850_seg_table[ZBSS_SECTION].s) 3379 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0, 3380 BFD_RELOC_V850_ALIGN); 3381 } 3382 3383 /* Return current size of variable part of frag. */ 3384 3385 int 3386 md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED) 3387 { 3388 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) 3389 abort (); 3390 3391 return md_relax_table[fragp->fr_subtype].rlx_length; 3392 } 3393 3394 long 3395 v850_pcrel_from_section (fixS *fixp, segT section) 3396 { 3397 /* If the symbol is undefined, or in a section other than our own, 3398 or it is weak (in which case it may well be in another section, 3399 then let the linker figure it out. */ 3400 if (fixp->fx_addsy != (symbolS *) NULL 3401 && (! S_IS_DEFINED (fixp->fx_addsy) 3402 || S_IS_WEAK (fixp->fx_addsy) 3403 || (S_GET_SEGMENT (fixp->fx_addsy) != section))) 3404 return 0; 3405 3406 return fixp->fx_frag->fr_address + fixp->fx_where; 3407 } 3408 3409 void 3410 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED) 3411 { 3412 valueT value = * valueP; 3413 char *where; 3414 3415 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3416 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL 3417 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP 3418 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3419 { 3420 fixP->fx_done = 0; 3421 return; 3422 } 3423 3424 if (fixP->fx_addsy == (symbolS *) NULL) 3425 fixP->fx_addnumber = value, 3426 fixP->fx_done = 1; 3427 3428 else if (fixP->fx_pcrel) 3429 fixP->fx_addnumber = fixP->fx_offset; 3430 3431 else 3432 { 3433 value = fixP->fx_offset; 3434 if (fixP->fx_subsy != (symbolS *) NULL) 3435 { 3436 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) 3437 value -= S_GET_VALUE (fixP->fx_subsy); 3438 else 3439 /* We don't actually support subtracting a symbol. */ 3440 as_bad_where (fixP->fx_file, fixP->fx_line, 3441 _("expression too complex")); 3442 } 3443 fixP->fx_addnumber = value; 3444 } 3445 3446 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) 3447 { 3448 int opindex; 3449 const struct v850_operand *operand; 3450 unsigned long insn; 3451 const char *errmsg = NULL; 3452 3453 opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; 3454 operand = &v850_operands[opindex]; 3455 3456 /* Fetch the instruction, insert the fully resolved operand 3457 value, and stuff the instruction back again. 3458 3459 Note the instruction has been stored in little endian 3460 format! */ 3461 where = fixP->fx_frag->fr_literal + fixP->fx_where; 3462 3463 if (fixP->fx_size > 2) 3464 insn = bfd_getl32 ((unsigned char *) where); 3465 else 3466 insn = bfd_getl16 ((unsigned char *) where); 3467 3468 /* When inserting loop offets a backwards displacement 3469 is encoded as a positive value. */ 3470 if (operand->flags & V850_INVERSE_PCREL) 3471 value = - value; 3472 3473 insn = v850_insert_operand (insn, operand, (offsetT) value, 3474 &errmsg); 3475 if (errmsg) 3476 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg); 3477 3478 if (fixP->fx_size > 2) 3479 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); 3480 else 3481 bfd_putl16 ((bfd_vma) insn, (unsigned char *) where); 3482 3483 if (fixP->fx_done) 3484 /* Nothing else to do here. */ 3485 return; 3486 3487 /* Determine a BFD reloc value based on the operand information. 3488 We are only prepared to turn a few of the operands into relocs. */ 3489 3490 if (operand->default_reloc == BFD_RELOC_NONE) 3491 { 3492 as_bad_where (fixP->fx_file, fixP->fx_line, 3493 _("unresolved expression that must be resolved")); 3494 fixP->fx_done = 1; 3495 return; 3496 } 3497 3498 { 3499 fixP->fx_r_type = operand->default_reloc; 3500 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) 3501 { 3502 fixP->fx_where += 2; 3503 fixP->fx_size = 2; 3504 fixP->fx_addnumber += 2; 3505 } 3506 } 3507 } 3508 else if (fixP->fx_done) 3509 { 3510 /* We still have to insert the value into memory! */ 3511 where = fixP->fx_frag->fr_literal + fixP->fx_where; 3512 3513 if (fixP->tc_fix_data != NULL 3514 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL) 3515 { 3516 const char * message = NULL; 3517 struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data; 3518 unsigned long insn; 3519 3520 /* The variable "where" currently points at the exact point inside 3521 the insn where we need to insert the value. But we need to 3522 extract the entire insn so we probably need to move "where" 3523 back a few bytes. */ 3524 3525 if (fixP->fx_size == 2) 3526 where -= 2; 3527 else if (fixP->fx_size == 1) 3528 where -= 3; 3529 3530 insn = bfd_getl32 ((unsigned char *) where); 3531 3532 /* Use the operand's insertion procedure, if present, in order to 3533 make sure that the value is correctly stored in the insn. */ 3534 insn = operand->insert (insn, (offsetT) value, & message); 3535 /* Ignore message even if it is set. */ 3536 3537 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); 3538 } 3539 else 3540 { 3541 switch (fixP->fx_r_type) 3542 { 3543 case BFD_RELOC_V850_32_ABS: 3544 case BFD_RELOC_V850_32_PCREL: 3545 bfd_putl32 (value & 0xfffffffe, (unsigned char *) where); 3546 break; 3547 3548 case BFD_RELOC_32: 3549 bfd_putl32 (value, (unsigned char *) where); 3550 break; 3551 3552 case BFD_RELOC_V850_23: 3553 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)) 3554 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))), 3555 (unsigned char *) where); 3556 break; 3557 3558 case BFD_RELOC_16: 3559 case BFD_RELOC_HI16: 3560 case BFD_RELOC_HI16_S: 3561 case BFD_RELOC_LO16: 3562 case BFD_RELOC_V850_ZDA_16_16_OFFSET: 3563 case BFD_RELOC_V850_SDA_16_16_OFFSET: 3564 case BFD_RELOC_V850_TDA_16_16_OFFSET: 3565 case BFD_RELOC_V850_CALLT_16_16_OFFSET: 3566 bfd_putl16 (value & 0xffff, (unsigned char *) where); 3567 break; 3568 3569 case BFD_RELOC_8: 3570 *where = value & 0xff; 3571 break; 3572 3573 case BFD_RELOC_V850_9_PCREL: 3574 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3) 3575 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where); 3576 break; 3577 3578 case BFD_RELOC_V850_17_PCREL: 3579 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16) 3580 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where); 3581 break; 3582 3583 case BFD_RELOC_V850_16_PCREL: 3584 bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001), 3585 (unsigned char *) (where + 2)); 3586 break; 3587 3588 case BFD_RELOC_V850_22_PCREL: 3589 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16) 3590 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where); 3591 break; 3592 3593 case BFD_RELOC_V850_16_S1: 3594 case BFD_RELOC_V850_LO16_S1: 3595 case BFD_RELOC_V850_ZDA_15_16_OFFSET: 3596 case BFD_RELOC_V850_SDA_15_16_OFFSET: 3597 bfd_putl16 (value & 0xfffe, (unsigned char *) where); 3598 break; 3599 3600 case BFD_RELOC_V850_16_SPLIT_OFFSET: 3601 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 3602 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: 3603 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET: 3604 bfd_putl32 (((value << 16) & 0xfffe0000) 3605 | ((value << 5) & 0x20) 3606 | (bfd_getl32 (where) & ~0xfffe0020), where); 3607 break; 3608 3609 case BFD_RELOC_V850_TDA_6_8_OFFSET: 3610 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e); 3611 break; 3612 3613 case BFD_RELOC_V850_TDA_7_8_OFFSET: 3614 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f); 3615 break; 3616 3617 case BFD_RELOC_V850_TDA_7_7_OFFSET: 3618 *where = (*where & ~0x7f) | (value & 0x7f); 3619 break; 3620 3621 case BFD_RELOC_V850_TDA_4_5_OFFSET: 3622 *where = (*where & ~0xf) | ((value >> 1) & 0xf); 3623 break; 3624 3625 case BFD_RELOC_V850_TDA_4_4_OFFSET: 3626 *where = (*where & ~0xf) | (value & 0xf); 3627 break; 3628 3629 case BFD_RELOC_V850_CALLT_6_7_OFFSET: 3630 *where = (*where & ~0x3f) | (value & 0x3f); 3631 break; 3632 3633 default: 3634 abort (); 3635 } 3636 } 3637 } 3638 } 3639 3640 /* Parse a cons expression. We have to handle hi(), lo(), etc 3641 on the v850. */ 3642 3643 bfd_reloc_code_real_type 3644 parse_cons_expression_v850 (expressionS *exp) 3645 { 3646 const char *errmsg; 3647 bfd_reloc_code_real_type r; 3648 3649 /* See if there's a reloc prefix like hi() we have to handle. */ 3650 r = v850_reloc_prefix (NULL, &errmsg); 3651 3652 /* Do normal expression parsing. */ 3653 expression (exp); 3654 return r; 3655 } 3656 3657 /* Create a fixup for a cons expression. If parse_cons_expression_v850 3658 found a reloc prefix, then we use that reloc, else we choose an 3659 appropriate one based on the size of the expression. */ 3660 3661 void 3662 cons_fix_new_v850 (fragS *frag, 3663 int where, 3664 int size, 3665 expressionS *exp, 3666 bfd_reloc_code_real_type r) 3667 { 3668 if (r == BFD_RELOC_NONE) 3669 { 3670 if (size == 4) 3671 r = BFD_RELOC_32; 3672 if (size == 2) 3673 r = BFD_RELOC_16; 3674 if (size == 1) 3675 r = BFD_RELOC_8; 3676 } 3677 3678 if (exp != NULL) 3679 fix_new_exp (frag, where, size, exp, 0, r); 3680 else 3681 fix_new (frag, where, size, NULL, 0, 0, r); 3682 } 3683 3684 bfd_boolean 3685 v850_fix_adjustable (fixS *fixP) 3686 { 3687 if (fixP->fx_addsy == NULL) 3688 return 1; 3689 3690 /* Don't adjust function names. */ 3691 if (S_IS_FUNCTION (fixP->fx_addsy)) 3692 return 0; 3693 3694 /* We need the symbol name for the VTABLE entries. */ 3695 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3696 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3697 return 0; 3698 3699 return 1; 3700 } 3701 3702 int 3703 v850_force_relocation (struct fix *fixP) 3704 { 3705 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL 3706 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP) 3707 return 1; 3708 3709 if (v850_relax 3710 && (fixP->fx_pcrel 3711 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN 3712 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL 3713 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL 3714 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL 3715 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL 3716 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL 3717 || fixP->fx_r_type >= BFD_RELOC_UNUSED)) 3718 return 1; 3719 3720 return generic_force_reloc (fixP); 3721 } 3722
