Lines Matching full:sregs
1245 BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1247 // Generate a set of unique, callee-saved registers (SRegs), where each
1249 // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1252 // sub-registers to SRegs.
1258 SRegs[*SR] = true;
1261 DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1264 // sub- and super-registers from SRegs.
1269 SRegs[*SR] = false;
1272 DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1274 // (3) Collect all registers that have at least one sub-register in SRegs,
1279 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1295 // (4) Include all super-registers found in (3) into SRegs.
1296 SRegs |= TmpSup;
1297 DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1299 // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1300 // remove R from SRegs.
1301 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1304 if (!SRegs[*SR])
1306 SRegs[R] = false;
1310 DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1321 if (!SRegs[S->Reg])
1327 SRegs[S->Reg] = false;
1333 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1343 SRegs[R] = false;
1362 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
