1 /* Opcode table for the ARC. 2 Copyright (C) 1994-2016 Free Software Foundation, Inc. 3 4 Contributed by Claudiu Zissulescu (claziss (at) synopsys.com) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software Foundation, 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include <stdio.h> 24 #include "bfd.h" 25 #include "opcode/arc.h" 26 #include "opintl.h" 27 #include "libiberty.h" 28 29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom 30 instructions. All NPS400 features are built into all ARC target builds as 31 this reduces the chances that regressions might creep in. */ 32 33 /* Insert RB register into a 32-bit opcode. */ 34 static unsigned 35 insert_rb (unsigned insn, 36 int value, 37 const char **errmsg ATTRIBUTE_UNUSED) 38 { 39 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); 40 } 41 42 static int 43 extract_rb (unsigned insn ATTRIBUTE_UNUSED, 44 bfd_boolean * invalid ATTRIBUTE_UNUSED) 45 { 46 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); 47 48 if (value == 0x3e && invalid) 49 *invalid = TRUE; /* A limm operand, it should be extracted in a 50 different way. */ 51 52 return value; 53 } 54 55 static unsigned 56 insert_rad (unsigned insn, 57 int value, 58 const char **errmsg ATTRIBUTE_UNUSED) 59 { 60 if (value & 0x01) 61 *errmsg = _("Improper register value."); 62 63 return insn | (value & 0x3F); 64 } 65 66 static unsigned 67 insert_rcd (unsigned insn, 68 int value, 69 const char **errmsg ATTRIBUTE_UNUSED) 70 { 71 if (value & 0x01) 72 *errmsg = _("Improper register value."); 73 74 return insn | ((value & 0x3F) << 6); 75 } 76 77 /* Dummy insert ZERO operand function. */ 78 79 static unsigned 80 insert_za (unsigned insn, 81 int value, 82 const char **errmsg) 83 { 84 if (value) 85 *errmsg = _("operand is not zero"); 86 return insn; 87 } 88 89 /* Insert Y-bit in bbit/br instructions. This function is called only 90 when solving fixups. */ 91 92 static unsigned 93 insert_Ybit (unsigned insn, 94 int value, 95 const char **errmsg ATTRIBUTE_UNUSED) 96 { 97 if (value > 0) 98 insn |= 0x08; 99 100 return insn; 101 } 102 103 /* Insert Y-bit in bbit/br instructions. This function is called only 104 when solving fixups. */ 105 106 static unsigned 107 insert_NYbit (unsigned insn, 108 int value, 109 const char **errmsg ATTRIBUTE_UNUSED) 110 { 111 if (value < 0) 112 insn |= 0x08; 113 114 return insn; 115 } 116 117 /* Insert H register into a 16-bit opcode. */ 118 119 static unsigned 120 insert_rhv1 (unsigned insn, 121 int value, 122 const char **errmsg ATTRIBUTE_UNUSED) 123 { 124 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07); 125 } 126 127 static int 128 extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED, 129 bfd_boolean * invalid ATTRIBUTE_UNUSED) 130 { 131 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7); 132 133 return value; 134 } 135 136 /* Insert H register into a 16-bit opcode. */ 137 138 static unsigned 139 insert_rhv2 (unsigned insn, 140 int value, 141 const char **errmsg) 142 { 143 if (value == 0x1E) 144 *errmsg = 145 _("Register R30 is a limm indicator for this type of instruction."); 146 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); 147 } 148 149 static int 150 extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED, 151 bfd_boolean * invalid ATTRIBUTE_UNUSED) 152 { 153 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); 154 155 return value; 156 } 157 158 static unsigned 159 insert_r0 (unsigned insn, 160 int value, 161 const char **errmsg ATTRIBUTE_UNUSED) 162 { 163 if (value != 0) 164 *errmsg = _("Register must be R0."); 165 return insn; 166 } 167 168 static int 169 extract_r0 (unsigned insn ATTRIBUTE_UNUSED, 170 bfd_boolean * invalid ATTRIBUTE_UNUSED) 171 { 172 return 0; 173 } 174 175 176 static unsigned 177 insert_r1 (unsigned insn, 178 int value, 179 const char **errmsg ATTRIBUTE_UNUSED) 180 { 181 if (value != 1) 182 *errmsg = _("Register must be R1."); 183 return insn; 184 } 185 186 static int 187 extract_r1 (unsigned insn ATTRIBUTE_UNUSED, 188 bfd_boolean * invalid ATTRIBUTE_UNUSED) 189 { 190 return 1; 191 } 192 193 static unsigned 194 insert_r2 (unsigned insn, 195 int value, 196 const char **errmsg ATTRIBUTE_UNUSED) 197 { 198 if (value != 2) 199 *errmsg = _("Register must be R2."); 200 return insn; 201 } 202 203 static int 204 extract_r2 (unsigned insn ATTRIBUTE_UNUSED, 205 bfd_boolean * invalid ATTRIBUTE_UNUSED) 206 { 207 return 2; 208 } 209 210 static unsigned 211 insert_r3 (unsigned insn, 212 int value, 213 const char **errmsg ATTRIBUTE_UNUSED) 214 { 215 if (value != 3) 216 *errmsg = _("Register must be R3."); 217 return insn; 218 } 219 220 static int 221 extract_r3 (unsigned insn ATTRIBUTE_UNUSED, 222 bfd_boolean * invalid ATTRIBUTE_UNUSED) 223 { 224 return 3; 225 } 226 227 static unsigned 228 insert_sp (unsigned insn, 229 int value, 230 const char **errmsg ATTRIBUTE_UNUSED) 231 { 232 if (value != 28) 233 *errmsg = _("Register must be SP."); 234 return insn; 235 } 236 237 static int 238 extract_sp (unsigned insn ATTRIBUTE_UNUSED, 239 bfd_boolean * invalid ATTRIBUTE_UNUSED) 240 { 241 return 28; 242 } 243 244 static unsigned 245 insert_gp (unsigned insn, 246 int value, 247 const char **errmsg ATTRIBUTE_UNUSED) 248 { 249 if (value != 26) 250 *errmsg = _("Register must be GP."); 251 return insn; 252 } 253 254 static int 255 extract_gp (unsigned insn ATTRIBUTE_UNUSED, 256 bfd_boolean * invalid ATTRIBUTE_UNUSED) 257 { 258 return 26; 259 } 260 261 static unsigned 262 insert_pcl (unsigned insn, 263 int value, 264 const char **errmsg ATTRIBUTE_UNUSED) 265 { 266 if (value != 63) 267 *errmsg = _("Register must be PCL."); 268 return insn; 269 } 270 271 static int 272 extract_pcl (unsigned insn ATTRIBUTE_UNUSED, 273 bfd_boolean * invalid ATTRIBUTE_UNUSED) 274 { 275 return 63; 276 } 277 278 static unsigned 279 insert_blink (unsigned insn, 280 int value, 281 const char **errmsg ATTRIBUTE_UNUSED) 282 { 283 if (value != 31) 284 *errmsg = _("Register must be BLINK."); 285 return insn; 286 } 287 288 static int 289 extract_blink (unsigned insn ATTRIBUTE_UNUSED, 290 bfd_boolean * invalid ATTRIBUTE_UNUSED) 291 { 292 return 31; 293 } 294 295 static unsigned 296 insert_ilink1 (unsigned insn, 297 int value, 298 const char **errmsg ATTRIBUTE_UNUSED) 299 { 300 if (value != 29) 301 *errmsg = _("Register must be ILINK1."); 302 return insn; 303 } 304 305 static int 306 extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED, 307 bfd_boolean * invalid ATTRIBUTE_UNUSED) 308 { 309 return 29; 310 } 311 312 static unsigned 313 insert_ilink2 (unsigned insn, 314 int value, 315 const char **errmsg ATTRIBUTE_UNUSED) 316 { 317 if (value != 30) 318 *errmsg = _("Register must be ILINK2."); 319 return insn; 320 } 321 322 static int 323 extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED, 324 bfd_boolean * invalid ATTRIBUTE_UNUSED) 325 { 326 return 30; 327 } 328 329 static unsigned 330 insert_ras (unsigned insn, 331 int value, 332 const char **errmsg ATTRIBUTE_UNUSED) 333 { 334 switch (value) 335 { 336 case 0: 337 case 1: 338 case 2: 339 case 3: 340 insn |= value; 341 break; 342 case 12: 343 case 13: 344 case 14: 345 case 15: 346 insn |= (value - 8); 347 break; 348 default: 349 *errmsg = _("Register must be either r0-r3 or r12-r15."); 350 break; 351 } 352 return insn; 353 } 354 355 static int 356 extract_ras (unsigned insn ATTRIBUTE_UNUSED, 357 bfd_boolean * invalid ATTRIBUTE_UNUSED) 358 { 359 int value = insn & 0x07; 360 if (value > 3) 361 return (value + 8); 362 else 363 return value; 364 } 365 366 static unsigned 367 insert_rbs (unsigned insn, 368 int value, 369 const char **errmsg ATTRIBUTE_UNUSED) 370 { 371 switch (value) 372 { 373 case 0: 374 case 1: 375 case 2: 376 case 3: 377 insn |= value << 8; 378 break; 379 case 12: 380 case 13: 381 case 14: 382 case 15: 383 insn |= ((value - 8)) << 8; 384 break; 385 default: 386 *errmsg = _("Register must be either r0-r3 or r12-r15."); 387 break; 388 } 389 return insn; 390 } 391 392 static int 393 extract_rbs (unsigned insn ATTRIBUTE_UNUSED, 394 bfd_boolean * invalid ATTRIBUTE_UNUSED) 395 { 396 int value = (insn >> 8) & 0x07; 397 if (value > 3) 398 return (value + 8); 399 else 400 return value; 401 } 402 403 static unsigned 404 insert_rcs (unsigned insn, 405 int value, 406 const char **errmsg ATTRIBUTE_UNUSED) 407 { 408 switch (value) 409 { 410 case 0: 411 case 1: 412 case 2: 413 case 3: 414 insn |= value << 5; 415 break; 416 case 12: 417 case 13: 418 case 14: 419 case 15: 420 insn |= ((value - 8)) << 5; 421 break; 422 default: 423 *errmsg = _("Register must be either r0-r3 or r12-r15."); 424 break; 425 } 426 return insn; 427 } 428 429 static int 430 extract_rcs (unsigned insn ATTRIBUTE_UNUSED, 431 bfd_boolean * invalid ATTRIBUTE_UNUSED) 432 { 433 int value = (insn >> 5) & 0x07; 434 if (value > 3) 435 return (value + 8); 436 else 437 return value; 438 } 439 440 static unsigned 441 insert_simm3s (unsigned insn, 442 int value, 443 const char **errmsg ATTRIBUTE_UNUSED) 444 { 445 int tmp = 0; 446 switch (value) 447 { 448 case -1: 449 tmp = 0x07; 450 break; 451 case 0: 452 tmp = 0x00; 453 break; 454 case 1: 455 tmp = 0x01; 456 break; 457 case 2: 458 tmp = 0x02; 459 break; 460 case 3: 461 tmp = 0x03; 462 break; 463 case 4: 464 tmp = 0x04; 465 break; 466 case 5: 467 tmp = 0x05; 468 break; 469 case 6: 470 tmp = 0x06; 471 break; 472 default: 473 *errmsg = _("Accepted values are from -1 to 6."); 474 break; 475 } 476 477 insn |= tmp << 8; 478 return insn; 479 } 480 481 static int 482 extract_simm3s (unsigned insn ATTRIBUTE_UNUSED, 483 bfd_boolean * invalid ATTRIBUTE_UNUSED) 484 { 485 int value = (insn >> 8) & 0x07; 486 if (value == 7) 487 return -1; 488 else 489 return value; 490 } 491 492 static unsigned 493 insert_rrange (unsigned insn, 494 int value, 495 const char **errmsg ATTRIBUTE_UNUSED) 496 { 497 int reg1 = (value >> 16) & 0xFFFF; 498 int reg2 = value & 0xFFFF; 499 if (reg1 != 13) 500 { 501 *errmsg = _("First register of the range should be r13."); 502 return insn; 503 } 504 if (reg2 < 13 || reg2 > 26) 505 { 506 *errmsg = _("Last register of the range doesn't fit."); 507 return insn; 508 } 509 insn |= ((reg2 - 12) & 0x0F) << 1; 510 return insn; 511 } 512 513 static int 514 extract_rrange (unsigned insn ATTRIBUTE_UNUSED, 515 bfd_boolean * invalid ATTRIBUTE_UNUSED) 516 { 517 return (insn >> 1) & 0x0F; 518 } 519 520 static unsigned 521 insert_fpel (unsigned insn, 522 int value, 523 const char **errmsg ATTRIBUTE_UNUSED) 524 { 525 if (value != 27) 526 { 527 *errmsg = _("Invalid register number, should be fp."); 528 return insn; 529 } 530 531 insn |= 0x0100; 532 return insn; 533 } 534 535 static int 536 extract_fpel (unsigned insn ATTRIBUTE_UNUSED, 537 bfd_boolean * invalid ATTRIBUTE_UNUSED) 538 { 539 return (insn & 0x0100) ? 27 : -1; 540 } 541 542 static unsigned 543 insert_blinkel (unsigned insn, 544 int value, 545 const char **errmsg ATTRIBUTE_UNUSED) 546 { 547 if (value != 31) 548 { 549 *errmsg = _("Invalid register number, should be blink."); 550 return insn; 551 } 552 553 insn |= 0x0200; 554 return insn; 555 } 556 557 static int 558 extract_blinkel (unsigned insn ATTRIBUTE_UNUSED, 559 bfd_boolean * invalid ATTRIBUTE_UNUSED) 560 { 561 return (insn & 0x0200) ? 31 : -1; 562 } 563 564 static unsigned 565 insert_pclel (unsigned insn, 566 int value, 567 const char **errmsg ATTRIBUTE_UNUSED) 568 { 569 if (value != 63) 570 { 571 *errmsg = _("Invalid register number, should be pcl."); 572 return insn; 573 } 574 575 insn |= 0x0400; 576 return insn; 577 } 578 579 static int 580 extract_pclel (unsigned insn ATTRIBUTE_UNUSED, 581 bfd_boolean * invalid ATTRIBUTE_UNUSED) 582 { 583 return (insn & 0x0400) ? 63 : -1; 584 } 585 586 #define INSERT_W6 587 /* mask = 00000000000000000000111111000000 588 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */ 589 static unsigned 590 insert_w6 (unsigned insn ATTRIBUTE_UNUSED, 591 int value ATTRIBUTE_UNUSED, 592 const char **errmsg ATTRIBUTE_UNUSED) 593 { 594 insn |= ((value >> 0) & 0x003f) << 6; 595 596 return insn; 597 } 598 599 #define EXTRACT_W6 600 /* mask = 00000000000000000000111111000000. */ 601 static int 602 extract_w6 (unsigned insn ATTRIBUTE_UNUSED, 603 bfd_boolean * invalid ATTRIBUTE_UNUSED) 604 { 605 unsigned value = 0; 606 607 value |= ((insn >> 6) & 0x003f) << 0; 608 609 return value; 610 } 611 612 #define INSERT_G_S 613 /* mask = 0000011100022000 614 insn = 01000ggghhhGG0HH. */ 615 static unsigned 616 insert_g_s (unsigned insn ATTRIBUTE_UNUSED, 617 int value ATTRIBUTE_UNUSED, 618 const char **errmsg ATTRIBUTE_UNUSED) 619 { 620 insn |= ((value >> 0) & 0x0007) << 8; 621 insn |= ((value >> 3) & 0x0003) << 3; 622 623 return insn; 624 } 625 626 #define EXTRACT_G_S 627 /* mask = 0000011100022000. */ 628 static int 629 extract_g_s (unsigned insn ATTRIBUTE_UNUSED, 630 bfd_boolean * invalid ATTRIBUTE_UNUSED) 631 { 632 int value = 0; 633 634 value |= ((insn >> 8) & 0x0007) << 0; 635 value |= ((insn >> 3) & 0x0003) << 3; 636 637 /* Extend the sign. */ 638 int signbit = 1 << (6 - 1); 639 value = (value ^ signbit) - signbit; 640 641 return value; 642 } 643 644 /* ARC NPS400 Support: See comment near head of file. */ 645 static unsigned 646 insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED, 647 int value ATTRIBUTE_UNUSED, 648 const char **errmsg ATTRIBUTE_UNUSED) 649 { 650 switch (value) 651 { 652 case 0: 653 case 1: 654 case 2: 655 case 3: 656 insn |= value << 24; 657 break; 658 case 12: 659 case 13: 660 case 14: 661 case 15: 662 insn |= (value - 8) << 24; 663 break; 664 default: 665 *errmsg = _("Register must be either r0-r3 or r12-r15."); 666 break; 667 } 668 return insn; 669 } 670 671 static int 672 extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED, 673 bfd_boolean * invalid ATTRIBUTE_UNUSED) 674 { 675 int value = (insn >> 24) & 0x07; 676 if (value > 3) 677 return (value + 8); 678 else 679 return value; 680 } 681 682 static unsigned 683 insert_nps_3bit_dst_short (unsigned insn ATTRIBUTE_UNUSED, 684 int value ATTRIBUTE_UNUSED, 685 const char **errmsg ATTRIBUTE_UNUSED) 686 { 687 switch (value) 688 { 689 case 0: 690 case 1: 691 case 2: 692 case 3: 693 insn |= value << 8; 694 break; 695 case 12: 696 case 13: 697 case 14: 698 case 15: 699 insn |= (value - 8) << 8; 700 break; 701 default: 702 *errmsg = _("Register must be either r0-r3 or r12-r15."); 703 break; 704 } 705 return insn; 706 } 707 708 static int 709 extract_nps_3bit_dst_short (unsigned insn ATTRIBUTE_UNUSED, 710 bfd_boolean * invalid ATTRIBUTE_UNUSED) 711 { 712 int value = (insn >> 8) & 0x07; 713 if (value > 3) 714 return (value + 8); 715 else 716 return value; 717 } 718 719 static unsigned 720 insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED, 721 int value ATTRIBUTE_UNUSED, 722 const char **errmsg ATTRIBUTE_UNUSED) 723 { 724 switch (value) 725 { 726 case 0: 727 case 1: 728 case 2: 729 case 3: 730 insn |= value << 21; 731 break; 732 case 12: 733 case 13: 734 case 14: 735 case 15: 736 insn |= (value - 8) << 21; 737 break; 738 default: 739 *errmsg = _("Register must be either r0-r3 or r12-r15."); 740 break; 741 } 742 return insn; 743 } 744 745 static int 746 extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED, 747 bfd_boolean * invalid ATTRIBUTE_UNUSED) 748 { 749 int value = (insn >> 21) & 0x07; 750 if (value > 3) 751 return (value + 8); 752 else 753 return value; 754 } 755 756 static unsigned 757 insert_nps_3bit_src2_short (unsigned insn ATTRIBUTE_UNUSED, 758 int value ATTRIBUTE_UNUSED, 759 const char **errmsg ATTRIBUTE_UNUSED) 760 { 761 switch (value) 762 { 763 case 0: 764 case 1: 765 case 2: 766 case 3: 767 insn |= value << 5; 768 break; 769 case 12: 770 case 13: 771 case 14: 772 case 15: 773 insn |= (value - 8) << 5; 774 break; 775 default: 776 *errmsg = _("Register must be either r0-r3 or r12-r15."); 777 break; 778 } 779 return insn; 780 } 781 782 static int 783 extract_nps_3bit_src2_short (unsigned insn ATTRIBUTE_UNUSED, 784 bfd_boolean * invalid ATTRIBUTE_UNUSED) 785 { 786 int value = (insn >> 5) & 0x07; 787 if (value > 3) 788 return (value + 8); 789 else 790 return value; 791 } 792 793 static unsigned 794 insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED, 795 int value ATTRIBUTE_UNUSED, 796 const char **errmsg ATTRIBUTE_UNUSED) 797 { 798 switch (value) 799 { 800 case 1: 801 value = 0; 802 break; 803 case 2: 804 value = 1; 805 break; 806 case 4: 807 value = 2; 808 break; 809 case 8: 810 value = 3; 811 break; 812 default: 813 value = 0; 814 *errmsg = _("Invalid size, should be 1, 2, 4, or 8."); 815 break; 816 } 817 818 insn |= value << 10; 819 return insn; 820 } 821 822 static int 823 extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED, 824 bfd_boolean * invalid ATTRIBUTE_UNUSED) 825 { 826 return 1 << ((insn >> 10) & 0x3); 827 } 828 829 static unsigned 830 insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED, 831 int value ATTRIBUTE_UNUSED, 832 const char **errmsg ATTRIBUTE_UNUSED) 833 { 834 insn |= ((value >> 5) & 7) << 12; 835 insn |= (value & 0x1f); 836 return insn; 837 } 838 839 static int 840 extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED, 841 bfd_boolean * invalid ATTRIBUTE_UNUSED) 842 { 843 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f); 844 } 845 846 static unsigned 847 insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED, 848 int value ATTRIBUTE_UNUSED, 849 const char **errmsg ATTRIBUTE_UNUSED) 850 { 851 switch (value) 852 { 853 case 1: 854 case 2: 855 case 4: 856 break; 857 858 default: 859 *errmsg = _("invalid immediate, must be 1, 2, or 4"); 860 value = 0; 861 } 862 863 insn |= (value << 6); 864 return insn; 865 } 866 867 static int 868 extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED, 869 bfd_boolean * invalid ATTRIBUTE_UNUSED) 870 { 871 return (insn >> 6) & 0x3f; 872 } 873 874 static unsigned 875 insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED, 876 int value ATTRIBUTE_UNUSED, 877 const char **errmsg ATTRIBUTE_UNUSED) 878 { 879 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10)); 880 return insn; 881 } 882 883 static int 884 extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED, 885 bfd_boolean * invalid ATTRIBUTE_UNUSED) 886 { 887 return (insn & 0x1f); 888 } 889 890 static unsigned 891 insert_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED, 892 int value ATTRIBUTE_UNUSED, 893 const char **errmsg ATTRIBUTE_UNUSED) 894 { 895 int top = (value >> 16) & 0xffff; 896 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE) 897 *errmsg = _("invalid value for CMEM ld/st immediate"); 898 insn |= (value & 0xffff); 899 return insn; 900 } 901 902 static int 903 extract_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED, 904 bfd_boolean * invalid ATTRIBUTE_UNUSED) 905 { 906 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff); 907 } 908 909 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \ 910 static unsigned \ 911 insert_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \ 912 int value ATTRIBUTE_UNUSED, \ 913 const char **errmsg ATTRIBUTE_UNUSED) \ 914 { \ 915 switch (value) \ 916 { \ 917 case 0: \ 918 case 8: \ 919 case 16: \ 920 case 24: \ 921 value = value / 8; \ 922 break; \ 923 default: \ 924 *errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \ 925 value = 0; \ 926 } \ 927 insn |= (value << SHIFT); \ 928 return insn; \ 929 } \ 930 \ 931 static int \ 932 extract_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \ 933 bfd_boolean * invalid ATTRIBUTE_UNUSED) \ 934 { \ 935 return ((insn >> SHIFT) & 0x3) * 8; \ 936 } 937 938 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12) 939 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10) 940 941 #define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\ 942 static unsigned \ 943 insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \ 944 int value ATTRIBUTE_UNUSED, \ 945 const char **errmsg ATTRIBUTE_UNUSED) \ 946 { \ 947 if (value < LOWER || value > UPPER) \ 948 { \ 949 *errmsg = _("Invalid size, value must be " \ 950 #LOWER " to " #UPPER "."); \ 951 return insn; \ 952 } \ 953 value -= BIAS; \ 954 insn |= (value << SHIFT); \ 955 return insn; \ 956 } \ 957 \ 958 static int \ 959 extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \ 960 bfd_boolean * invalid ATTRIBUTE_UNUSED) \ 961 { \ 962 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \ 963 } 964 965 MAKE_BIAS_INSERT_EXTRACT_FUNCS(addb_size,2,32,5,1,5) 966 MAKE_BIAS_INSERT_EXTRACT_FUNCS(andb_size,1,32,5,1,5) 967 MAKE_BIAS_INSERT_EXTRACT_FUNCS(fxorb_size,8,32,5,8,5) 968 MAKE_BIAS_INSERT_EXTRACT_FUNCS(wxorb_size,16,32,5,16,5) 969 MAKE_BIAS_INSERT_EXTRACT_FUNCS(bitop_size,1,32,5,1,10) 970 MAKE_BIAS_INSERT_EXTRACT_FUNCS(qcmp_size,1,8,3,1,9) 971 MAKE_BIAS_INSERT_EXTRACT_FUNCS(bitop1_size,1,32,5,1,20) 972 MAKE_BIAS_INSERT_EXTRACT_FUNCS(bitop2_size,1,32,5,1,25) 973 MAKE_BIAS_INSERT_EXTRACT_FUNCS(hash_width,1,32,5,1,6) 974 MAKE_BIAS_INSERT_EXTRACT_FUNCS(hash_len,1,8,3,1,2) 975 MAKE_BIAS_INSERT_EXTRACT_FUNCS(index3,4,7,2,4,0) 976 977 static int 978 extract_nps_qcmp_m3 (unsigned insn ATTRIBUTE_UNUSED, 979 bfd_boolean * invalid ATTRIBUTE_UNUSED) 980 { 981 int m3 = (insn >> 5) & 0xf; 982 if (m3 == 0xf) 983 *invalid = TRUE; 984 return m3; 985 } 986 987 static int 988 extract_nps_qcmp_m2 (unsigned insn ATTRIBUTE_UNUSED, 989 bfd_boolean * invalid ATTRIBUTE_UNUSED) 990 { 991 bfd_boolean tmp_invalid = FALSE; 992 int m2 = (insn >> 15) & 0x1; 993 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); 994 995 if (m2 == 0 && m3 == 0xf) 996 *invalid = TRUE; 997 return m2; 998 } 999 1000 static int 1001 extract_nps_qcmp_m1 (unsigned insn ATTRIBUTE_UNUSED, 1002 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1003 { 1004 bfd_boolean tmp_invalid = FALSE; 1005 int m1 = (insn >> 14) & 0x1; 1006 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid); 1007 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); 1008 1009 if (m1 == 0 && m2 == 0 && m3 == 0xf) 1010 *invalid = TRUE; 1011 return m1; 1012 } 1013 1014 static unsigned 1015 insert_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED, 1016 int value ATTRIBUTE_UNUSED, 1017 const char **errmsg ATTRIBUTE_UNUSED) 1018 { 1019 unsigned pwr; 1020 1021 if (value < 1 || value > 256) 1022 { 1023 *errmsg = _("value out of range 1 - 256"); 1024 return 0; 1025 } 1026 1027 for (pwr = 0; (value & 1) == 0; value >>= 1) 1028 ++pwr; 1029 1030 if (value != 1) 1031 { 1032 *errmsg = _("value must be power of 2"); 1033 return 0; 1034 } 1035 1036 return insn | (pwr << 8); 1037 } 1038 1039 static int 1040 extract_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED, 1041 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1042 { 1043 unsigned entry_size = (insn >> 8) & 0xf; 1044 return 1 << entry_size; 1045 } 1046 1047 static unsigned 1048 insert_nps_bitop_mod4_msb (unsigned insn ATTRIBUTE_UNUSED, 1049 int value ATTRIBUTE_UNUSED, 1050 const char **errmsg ATTRIBUTE_UNUSED) 1051 { 1052 return insn | ((value & 0x2) << 30); 1053 } 1054 1055 static int 1056 extract_nps_bitop_mod4_msb (unsigned insn ATTRIBUTE_UNUSED, 1057 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1058 { 1059 return (insn >> 30) & 0x2; 1060 } 1061 1062 static unsigned 1063 insert_nps_bitop_mod4_lsb (unsigned insn ATTRIBUTE_UNUSED, 1064 int value ATTRIBUTE_UNUSED, 1065 const char **errmsg ATTRIBUTE_UNUSED) 1066 { 1067 return insn | ((value & 0x1) << 15); 1068 } 1069 1070 static int 1071 extract_nps_bitop_mod4_lsb (unsigned insn ATTRIBUTE_UNUSED, 1072 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1073 { 1074 return (insn >> 15) & 0x1; 1075 } 1076 1077 static unsigned 1078 insert_nps_bitop_dst_pos3_pos4 (unsigned insn ATTRIBUTE_UNUSED, 1079 int value ATTRIBUTE_UNUSED, 1080 const char **errmsg ATTRIBUTE_UNUSED) 1081 { 1082 return insn | (value << 10) | (value << 5); 1083 } 1084 1085 static int 1086 extract_nps_bitop_dst_pos3_pos4 (unsigned insn ATTRIBUTE_UNUSED, 1087 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1088 { 1089 if (((insn >> 10) & 0x1f) != ((insn >> 5) & 0x1f)) 1090 *invalid = TRUE; 1091 return ((insn >> 5) & 0x1f); 1092 } 1093 1094 static unsigned 1095 insert_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED, 1096 int value ATTRIBUTE_UNUSED, 1097 const char **errmsg ATTRIBUTE_UNUSED) 1098 { 1099 if (value < 0 || value > 28) 1100 *errmsg = _("Value must be in the range 0 to 28"); 1101 return insn | (value << 20); 1102 } 1103 1104 static int 1105 extract_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED, 1106 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1107 { 1108 int value = (insn >> 20) & 0x1f; 1109 if (value > 28) 1110 *invalid = TRUE; 1111 return value; 1112 } 1113 1114 #define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \ 1115 static unsigned \ 1116 insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \ 1117 int value ATTRIBUTE_UNUSED, \ 1118 const char **errmsg ATTRIBUTE_UNUSED) \ 1119 { \ 1120 if (value < 1 || value > UPPER) \ 1121 *errmsg = _("Value must be in the range 1 to " #UPPER); \ 1122 if (value == UPPER) \ 1123 value = 0; \ 1124 return insn | (value << SHIFT); \ 1125 } \ 1126 \ 1127 static int \ 1128 extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \ 1129 bfd_boolean * invalid ATTRIBUTE_UNUSED) \ 1130 { \ 1131 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \ 1132 if (value == 0) \ 1133 value = UPPER; \ 1134 return value; \ 1135 } 1136 1137 MAKE_1BASED_INSERT_EXTRACT_FUNCS(field_size, 6, 8, 3) 1138 MAKE_1BASED_INSERT_EXTRACT_FUNCS(shift_factor, 9, 8, 3) 1139 MAKE_1BASED_INSERT_EXTRACT_FUNCS(bits_to_scramble, 12, 8, 3) 1140 MAKE_1BASED_INSERT_EXTRACT_FUNCS(bdlen_max_len, 5, 256, 8) 1141 1142 static unsigned 1143 insert_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED, 1144 int value ATTRIBUTE_UNUSED, 1145 const char **errmsg ATTRIBUTE_UNUSED) 1146 { 1147 if (value < 0 || value > 240) 1148 *errmsg = _("Value must be in the range 0 to 240"); 1149 if ((value % 16) != 0) 1150 *errmsg = _("Value must be a multiple of 16"); 1151 value = value / 16; 1152 return insn | (value << 6); 1153 } 1154 1155 static int 1156 extract_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED, 1157 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1158 { 1159 int value = (insn >> 6) & 0xF; 1160 return value * 16; 1161 } 1162 1163 /* Include the generic extract/insert functions. Order is important 1164 as some of the functions present in the .h may be disabled via 1165 defines. */ 1166 #include "arc-fxi.h" 1167 1168 /* The flag operands table. 1169 1170 The format of the table is 1171 NAME CODE BITS SHIFT FAVAIL. */ 1172 const struct arc_flag_operand arc_flag_operands[] = 1173 { 1174 #define F_NULL 0 1175 { 0, 0, 0, 0, 0}, 1176 #define F_ALWAYS (F_NULL + 1) 1177 { "al", 0, 0, 0, 0 }, 1178 #define F_RA (F_ALWAYS + 1) 1179 { "ra", 0, 0, 0, 0 }, 1180 #define F_EQUAL (F_RA + 1) 1181 { "eq", 1, 5, 0, 1 }, 1182 #define F_ZERO (F_EQUAL + 1) 1183 { "z", 1, 5, 0, 0 }, 1184 #define F_NOTEQUAL (F_ZERO + 1) 1185 { "ne", 2, 5, 0, 1 }, 1186 #define F_NOTZERO (F_NOTEQUAL + 1) 1187 { "nz", 2, 5, 0, 0 }, 1188 #define F_POZITIVE (F_NOTZERO + 1) 1189 { "p", 3, 5, 0, 1 }, 1190 #define F_PL (F_POZITIVE + 1) 1191 { "pl", 3, 5, 0, 0 }, 1192 #define F_NEGATIVE (F_PL + 1) 1193 { "n", 4, 5, 0, 1 }, 1194 #define F_MINUS (F_NEGATIVE + 1) 1195 { "mi", 4, 5, 0, 0 }, 1196 #define F_CARRY (F_MINUS + 1) 1197 { "c", 5, 5, 0, 1 }, 1198 #define F_CARRYSET (F_CARRY + 1) 1199 { "cs", 5, 5, 0, 0 }, 1200 #define F_LOWER (F_CARRYSET + 1) 1201 { "lo", 5, 5, 0, 0 }, 1202 #define F_CARRYCLR (F_LOWER + 1) 1203 { "cc", 6, 5, 0, 0 }, 1204 #define F_NOTCARRY (F_CARRYCLR + 1) 1205 { "nc", 6, 5, 0, 1 }, 1206 #define F_HIGHER (F_NOTCARRY + 1) 1207 { "hs", 6, 5, 0, 0 }, 1208 #define F_OVERFLOWSET (F_HIGHER + 1) 1209 { "vs", 7, 5, 0, 0 }, 1210 #define F_OVERFLOW (F_OVERFLOWSET + 1) 1211 { "v", 7, 5, 0, 1 }, 1212 #define F_NOTOVERFLOW (F_OVERFLOW + 1) 1213 { "nv", 8, 5, 0, 1 }, 1214 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1) 1215 { "vc", 8, 5, 0, 0 }, 1216 #define F_GT (F_OVERFLOWCLR + 1) 1217 { "gt", 9, 5, 0, 1 }, 1218 #define F_GE (F_GT + 1) 1219 { "ge", 10, 5, 0, 1 }, 1220 #define F_LT (F_GE + 1) 1221 { "lt", 11, 5, 0, 1 }, 1222 #define F_LE (F_LT + 1) 1223 { "le", 12, 5, 0, 1 }, 1224 #define F_HI (F_LE + 1) 1225 { "hi", 13, 5, 0, 1 }, 1226 #define F_LS (F_HI + 1) 1227 { "ls", 14, 5, 0, 1 }, 1228 #define F_PNZ (F_LS + 1) 1229 { "pnz", 15, 5, 0, 1 }, 1230 1231 /* FLAG. */ 1232 #define F_FLAG (F_PNZ + 1) 1233 { "f", 1, 1, 15, 1 }, 1234 #define F_FFAKE (F_FLAG + 1) 1235 { "f", 0, 0, 0, 1 }, 1236 1237 /* Delay slot. */ 1238 #define F_ND (F_FFAKE + 1) 1239 { "nd", 0, 1, 5, 0 }, 1240 #define F_D (F_ND + 1) 1241 { "d", 1, 1, 5, 1 }, 1242 #define F_DFAKE (F_D + 1) 1243 { "d", 0, 0, 0, 1 }, 1244 1245 /* Data size. */ 1246 #define F_SIZEB1 (F_DFAKE + 1) 1247 { "b", 1, 2, 1, 1 }, 1248 #define F_SIZEB7 (F_SIZEB1 + 1) 1249 { "b", 1, 2, 7, 1 }, 1250 #define F_SIZEB17 (F_SIZEB7 + 1) 1251 { "b", 1, 2, 17, 1 }, 1252 #define F_SIZEW1 (F_SIZEB17 + 1) 1253 { "w", 2, 2, 1, 0 }, 1254 #define F_SIZEW7 (F_SIZEW1 + 1) 1255 { "w", 2, 2, 7, 0 }, 1256 #define F_SIZEW17 (F_SIZEW7 + 1) 1257 { "w", 2, 2, 17, 0 }, 1258 1259 /* Sign extension. */ 1260 #define F_SIGN6 (F_SIZEW17 + 1) 1261 { "x", 1, 1, 6, 1 }, 1262 #define F_SIGN16 (F_SIGN6 + 1) 1263 { "x", 1, 1, 16, 1 }, 1264 #define F_SIGNX (F_SIGN16 + 1) 1265 { "x", 0, 0, 0, 1 }, 1266 1267 /* Address write-back modes. */ 1268 #define F_A3 (F_SIGNX + 1) 1269 { "a", 1, 2, 3, 0 }, 1270 #define F_A9 (F_A3 + 1) 1271 { "a", 1, 2, 9, 0 }, 1272 #define F_A22 (F_A9 + 1) 1273 { "a", 1, 2, 22, 0 }, 1274 #define F_AW3 (F_A22 + 1) 1275 { "aw", 1, 2, 3, 1 }, 1276 #define F_AW9 (F_AW3 + 1) 1277 { "aw", 1, 2, 9, 1 }, 1278 #define F_AW22 (F_AW9 + 1) 1279 { "aw", 1, 2, 22, 1 }, 1280 #define F_AB3 (F_AW22 + 1) 1281 { "ab", 2, 2, 3, 1 }, 1282 #define F_AB9 (F_AB3 + 1) 1283 { "ab", 2, 2, 9, 1 }, 1284 #define F_AB22 (F_AB9 + 1) 1285 { "ab", 2, 2, 22, 1 }, 1286 #define F_AS3 (F_AB22 + 1) 1287 { "as", 3, 2, 3, 1 }, 1288 #define F_AS9 (F_AS3 + 1) 1289 { "as", 3, 2, 9, 1 }, 1290 #define F_AS22 (F_AS9 + 1) 1291 { "as", 3, 2, 22, 1 }, 1292 #define F_ASFAKE (F_AS22 + 1) 1293 { "as", 0, 0, 0, 1 }, 1294 1295 /* Cache bypass. */ 1296 #define F_DI5 (F_ASFAKE + 1) 1297 { "di", 1, 1, 5, 1 }, 1298 #define F_DI11 (F_DI5 + 1) 1299 { "di", 1, 1, 11, 1 }, 1300 #define F_DI15 (F_DI11 + 1) 1301 { "di", 1, 1, 15, 1 }, 1302 1303 /* ARCv2 specific. */ 1304 #define F_NT (F_DI15 + 1) 1305 { "nt", 0, 1, 3, 1}, 1306 #define F_T (F_NT + 1) 1307 { "t", 1, 1, 3, 1}, 1308 #define F_H1 (F_T + 1) 1309 { "h", 2, 2, 1, 1 }, 1310 #define F_H7 (F_H1 + 1) 1311 { "h", 2, 2, 7, 1 }, 1312 #define F_H17 (F_H7 + 1) 1313 { "h", 2, 2, 17, 1 }, 1314 1315 /* Fake Flags. */ 1316 #define F_NE (F_H17 + 1) 1317 { "ne", 0, 0, 0, 1 }, 1318 1319 /* ARC NPS400 Support: See comment near head of file. */ 1320 #define F_NPS_CL (F_NE + 1) 1321 { "cl", 0, 0, 0, 1 }, 1322 1323 #define F_NPS_FLAG (F_NPS_CL + 1) 1324 { "f", 1, 1, 20, 1 }, 1325 1326 #define F_NPS_R (F_NPS_FLAG + 1) 1327 { "r", 1, 1, 15, 1 }, 1328 1329 #define F_NPS_RW (F_NPS_R + 1) 1330 { "rw", 0, 1, 7, 1 }, 1331 1332 #define F_NPS_RD (F_NPS_RW + 1) 1333 { "rd", 1, 1, 7, 1 }, 1334 1335 #define F_NPS_WFT (F_NPS_RD + 1) 1336 { "wft", 0, 0, 0, 1 }, 1337 1338 #define F_NPS_IE1 (F_NPS_WFT + 1) 1339 { "ie1", 1, 2, 8, 1 }, 1340 1341 #define F_NPS_IE2 (F_NPS_IE1 + 1) 1342 { "ie2", 2, 2, 8, 1 }, 1343 1344 #define F_NPS_IE12 (F_NPS_IE2 + 1) 1345 { "ie12", 3, 2, 8, 1 }, 1346 1347 #define F_NPS_SYNC_RD (F_NPS_IE12 + 1) 1348 { "rd", 0, 1, 6, 1 }, 1349 1350 #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1) 1351 { "wr", 1, 1, 6, 1 }, 1352 1353 #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1) 1354 { "off", 0, 0, 0, 1 }, 1355 1356 #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1) 1357 { "restore", 0, 0, 0, 1 }, 1358 1359 #define F_NPS_SX (F_NPS_HWS_RESTORE + 1) 1360 { "sx", 1, 1, 14, 1 }, 1361 1362 #define F_NPS_AR (F_NPS_SX + 1) 1363 { "ar", 0, 1, 0, 1 }, 1364 1365 #define F_NPS_AL (F_NPS_AR + 1) 1366 { "al", 1, 1, 0, 1 }, 1367 1368 #define F_NPS_S (F_NPS_AL + 1) 1369 { "s", 0, 0, 0, 1 }, 1370 1371 #define F_NPS_ZNCV_RD (F_NPS_S + 1) 1372 { "rd", 0, 1, 15, 1 }, 1373 1374 #define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1) 1375 { "wr", 1, 1, 15, 1 }, 1376 1377 #define F_NPS_P0 (F_NPS_ZNCV_WR + 1) 1378 { "p0", 0, 0, 0, 1 }, 1379 1380 #define F_NPS_P1 (F_NPS_P0 + 1) 1381 { "p1", 0, 0, 0, 1 }, 1382 1383 #define F_NPS_P2 (F_NPS_P1 + 1) 1384 { "p2", 0, 0, 0, 1 }, 1385 1386 #define F_NPS_P3 (F_NPS_P2 + 1) 1387 { "p3", 0, 0, 0, 1 }, 1388 1389 #define F_NPS_LDBIT_DI (F_NPS_P3 + 1) 1390 { "di", 0, 0, 0, 1 }, 1391 1392 #define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1) 1393 { "cl", 1, 1, 6, 1 }, 1394 1395 #define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1) 1396 { "cl", 1, 1, 16, 1 }, 1397 1398 #define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1) 1399 { "x2", 1, 2, 9, 1 }, 1400 1401 #define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1) 1402 { "x2", 1, 2, 22, 1 }, 1403 1404 #define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1) 1405 { "x4", 2, 2, 9, 1 }, 1406 1407 #define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1) 1408 { "x4", 2, 2, 22, 1 }, 1409 }; 1410 1411 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); 1412 1413 /* Table of the flag classes. 1414 1415 The format of the table is 1416 CLASS {FLAG_CODE}. */ 1417 const struct arc_flag_class arc_flag_classes[] = 1418 { 1419 #define C_EMPTY 0 1420 { F_CLASS_NONE, { F_NULL } }, 1421 1422 #define C_CC (C_EMPTY + 1) 1423 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, 1424 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, 1425 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, 1426 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 1427 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, 1428 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, 1429 F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 1430 1431 #define C_AA_ADDR3 (C_CC + 1) 1432 #define C_AA27 (C_CC + 1) 1433 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, 1434 #define C_AA_ADDR9 (C_AA_ADDR3 + 1) 1435 #define C_AA21 (C_AA_ADDR3 + 1) 1436 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, 1437 #define C_AA_ADDR22 (C_AA_ADDR9 + 1) 1438 #define C_AA8 (C_AA_ADDR9 + 1) 1439 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } }, 1440 1441 #define C_F (C_AA_ADDR22 + 1) 1442 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } }, 1443 #define C_FHARD (C_F + 1) 1444 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } }, 1445 1446 #define C_T (C_FHARD + 1) 1447 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } }, 1448 #define C_D (C_T + 1) 1449 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } }, 1450 1451 #define C_DHARD (C_D + 1) 1452 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } }, 1453 1454 #define C_DI20 (C_DHARD + 1) 1455 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }}, 1456 #define C_DI16 (C_DI20 + 1) 1457 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }}, 1458 #define C_DI26 (C_DI16 + 1) 1459 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }}, 1460 1461 #define C_X25 (C_DI26 + 1) 1462 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }}, 1463 #define C_X15 (C_X25 + 1) 1464 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }}, 1465 #define C_XHARD (C_X15 + 1) 1466 #define C_X (C_X15 + 1) 1467 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }}, 1468 1469 #define C_ZZ13 (C_X + 1) 1470 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}}, 1471 #define C_ZZ23 (C_ZZ13 + 1) 1472 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}}, 1473 #define C_ZZ29 (C_ZZ23 + 1) 1474 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}}, 1475 1476 #define C_AS (C_ZZ29 + 1) 1477 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}}, 1478 1479 #define C_NE (C_AS + 1) 1480 { F_CLASS_OPTIONAL, { F_NE, F_NULL}}, 1481 1482 /* ARC NPS400 Support: See comment near head of file. */ 1483 #define C_NPS_CL (C_NE + 1) 1484 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}}, 1485 1486 #define C_NPS_F (C_NPS_CL + 1) 1487 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}}, 1488 1489 #define C_NPS_R (C_NPS_F + 1) 1490 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}}, 1491 1492 #define C_NPS_SCHD_RW (C_NPS_R + 1) 1493 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}}, 1494 1495 #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1) 1496 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}}, 1497 1498 #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1) 1499 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}}, 1500 1501 #define C_NPS_SYNC (C_NPS_SCHD_IE + 1) 1502 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}}, 1503 1504 #define C_NPS_HWS_OFF (C_NPS_SYNC + 1) 1505 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}}, 1506 1507 #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1) 1508 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}}, 1509 1510 #define C_NPS_SX (C_NPS_HWS_RESTORE + 1) 1511 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}}, 1512 1513 #define C_NPS_AR_AL (C_NPS_SX + 1) 1514 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}}, 1515 1516 #define C_NPS_S (C_NPS_AR_AL + 1) 1517 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}}, 1518 1519 #define C_NPS_ZNCV (C_NPS_S + 1) 1520 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}}, 1521 1522 #define C_NPS_P0 (C_NPS_ZNCV + 1) 1523 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }}, 1524 1525 #define C_NPS_P1 (C_NPS_P0 + 1) 1526 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }}, 1527 1528 #define C_NPS_P2 (C_NPS_P1 + 1) 1529 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }}, 1530 1531 #define C_NPS_P3 (C_NPS_P2 + 1) 1532 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }}, 1533 1534 #define C_NPS_LDBIT_DI (C_NPS_P3 + 1) 1535 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }}, 1536 1537 #define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1) 1538 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }}, 1539 1540 #define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1) 1541 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }}, 1542 1543 #define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1) 1544 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }}, 1545 1546 #define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1) 1547 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }}, 1548 }; 1549 1550 const unsigned char flags_none[] = { 0 }; 1551 const unsigned char flags_f[] = { C_F }; 1552 const unsigned char flags_cc[] = { C_CC }; 1553 const unsigned char flags_ccf[] = { C_CC, C_F }; 1554 1555 /* The operands table. 1556 1557 The format of the operands table is: 1558 1559 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */ 1560 const struct arc_operand arc_operands[] = 1561 { 1562 /* The fields are bits, shift, insert, extract, flags. The zero 1563 index is used to indicate end-of-list. */ 1564 #define UNUSED 0 1565 { 0, 0, 0, 0, 0, 0 }, 1566 1567 #define IGNORED (UNUSED + 1) 1568 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 }, 1569 1570 /* The plain integer register fields. Used by 32 bit 1571 instructions. */ 1572 #define RA (IGNORED + 1) 1573 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 }, 1574 #define RB (RA + 1) 1575 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb }, 1576 #define RC (RB + 1) 1577 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 }, 1578 #define RBdup (RC + 1) 1579 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb }, 1580 1581 #define RAD (RBdup + 1) 1582 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, 1583 #define RCD (RAD + 1) 1584 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 }, 1585 1586 /* The plain integer register fields. Used by short 1587 instructions. */ 1588 #define RA16 (RCD + 1) 1589 #define RA_S (RCD + 1) 1590 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras }, 1591 #define RB16 (RA16 + 1) 1592 #define RB_S (RA16 + 1) 1593 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs }, 1594 #define RB16dup (RB16 + 1) 1595 #define RB_Sdup (RB16 + 1) 1596 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs }, 1597 #define RC16 (RB16dup + 1) 1598 #define RC_S (RB16dup + 1) 1599 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs }, 1600 #define R6H (RC16 + 1) /* 6bit register field 'h' used 1601 by V1 cpus. */ 1602 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 }, 1603 #define R5H (R6H + 1) /* 5bit register field 'h' used 1604 by V2 cpus. */ 1605 #define RH_S (R6H + 1) /* 5bit register field 'h' used 1606 by V2 cpus. */ 1607 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 }, 1608 #define R5Hdup (R5H + 1) 1609 #define RH_Sdup (R5H + 1) 1610 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, 1611 insert_rhv2, extract_rhv2 }, 1612 1613 #define RG (R5Hdup + 1) 1614 #define G_S (R5Hdup + 1) 1615 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s }, 1616 1617 /* Fix registers. */ 1618 #define R0 (RG + 1) 1619 #define R0_S (RG + 1) 1620 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 }, 1621 #define R1 (R0 + 1) 1622 #define R1_S (R0 + 1) 1623 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 }, 1624 #define R2 (R1 + 1) 1625 #define R2_S (R1 + 1) 1626 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 }, 1627 #define R3 (R2 + 1) 1628 #define R3_S (R2 + 1) 1629 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 }, 1630 #define RSP (R3 + 1) 1631 #define SP_S (R3 + 1) 1632 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp }, 1633 #define SPdup (RSP + 1) 1634 #define SP_Sdup (RSP + 1) 1635 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp }, 1636 #define GP (SPdup + 1) 1637 #define GP_S (SPdup + 1) 1638 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp }, 1639 1640 #define PCL_S (GP + 1) 1641 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl }, 1642 1643 #define BLINK (PCL_S + 1) 1644 #define BLINK_S (PCL_S + 1) 1645 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink }, 1646 1647 #define ILINK1 (BLINK + 1) 1648 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 }, 1649 #define ILINK2 (ILINK1 + 1) 1650 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 }, 1651 1652 /* Long immediate. */ 1653 #define LIMM (ILINK2 + 1) 1654 #define LIMM_S (ILINK2 + 1) 1655 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 }, 1656 #define LIMMdup (LIMM + 1) 1657 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 }, 1658 1659 /* Special operands. */ 1660 #define ZA (LIMMdup + 1) 1661 #define ZB (LIMMdup + 1) 1662 #define ZA_S (LIMMdup + 1) 1663 #define ZB_S (LIMMdup + 1) 1664 #define ZC_S (LIMMdup + 1) 1665 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 }, 1666 1667 #define RRANGE_EL (ZA + 1) 1668 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, 1669 insert_rrange, extract_rrange}, 1670 #define FP_EL (RRANGE_EL + 1) 1671 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, 1672 insert_fpel, extract_fpel }, 1673 #define BLINK_EL (FP_EL + 1) 1674 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, 1675 insert_blinkel, extract_blinkel }, 1676 #define PCL_EL (BLINK_EL + 1) 1677 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, 1678 insert_pclel, extract_pclel }, 1679 1680 /* Fake operand to handle the T flag. */ 1681 #define BRAKET (PCL_EL + 1) 1682 #define BRAKETdup (PCL_EL + 1) 1683 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 }, 1684 1685 /* Fake operand to handle the T flag. */ 1686 #define FKT_T (BRAKET + 1) 1687 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 }, 1688 /* Fake operand to handle the T flag. */ 1689 #define FKT_NT (FKT_T + 1) 1690 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 }, 1691 1692 /* UIMM6_20 mask = 00000000000000000000111111000000. */ 1693 #define UIMM6_20 (FKT_NT + 1) 1694 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20}, 1695 1696 /* SIMM12_20 mask = 00000000000000000000111111222222. */ 1697 #define SIMM12_20 (UIMM6_20 + 1) 1698 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20}, 1699 1700 /* SIMM3_5_S mask = 0000011100000000. */ 1701 #define SIMM3_5_S (SIMM12_20 + 1) 1702 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, 1703 insert_simm3s, extract_simm3s}, 1704 1705 /* UIMM7_A32_11_S mask = 0000000000011111. */ 1706 #define UIMM7_A32_11_S (SIMM3_5_S + 1) 1707 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 1708 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, 1709 extract_uimm7_a32_11_s}, 1710 1711 /* UIMM7_9_S mask = 0000000001111111. */ 1712 #define UIMM7_9_S (UIMM7_A32_11_S + 1) 1713 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s}, 1714 1715 /* UIMM3_13_S mask = 0000000000000111. */ 1716 #define UIMM3_13_S (UIMM7_9_S + 1) 1717 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s}, 1718 1719 /* SIMM11_A32_7_S mask = 0000000111111111. */ 1720 #define SIMM11_A32_7_S (UIMM3_13_S + 1) 1721 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 1722 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s}, 1723 1724 /* UIMM6_13_S mask = 0000000002220111. */ 1725 #define UIMM6_13_S (SIMM11_A32_7_S + 1) 1726 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s}, 1727 /* UIMM5_11_S mask = 0000000000011111. */ 1728 #define UIMM5_11_S (UIMM6_13_S + 1) 1729 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, 1730 extract_uimm5_11_s}, 1731 1732 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */ 1733 #define SIMM9_A16_8 (UIMM5_11_S + 1) 1734 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 1735 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, 1736 extract_simm9_a16_8}, 1737 1738 /* UIMM6_8 mask = 00000000000000000000111111000000. */ 1739 #define UIMM6_8 (SIMM9_A16_8 + 1) 1740 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8}, 1741 1742 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */ 1743 #define SIMM21_A16_5 (UIMM6_8 + 1) 1744 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED 1745 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, 1746 insert_simm21_a16_5, extract_simm21_a16_5}, 1747 1748 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */ 1749 #define SIMM25_A16_5 (SIMM21_A16_5 + 1) 1750 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED 1751 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, 1752 insert_simm25_a16_5, extract_simm25_a16_5}, 1753 1754 /* SIMM10_A16_7_S mask = 0000000111111111. */ 1755 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1) 1756 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 1757 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, 1758 extract_simm10_a16_7_s}, 1759 1760 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1) 1761 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 1762 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s}, 1763 1764 /* SIMM7_A16_10_S mask = 0000000000111111. */ 1765 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1) 1766 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 1767 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, 1768 extract_simm7_a16_10_s}, 1769 1770 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */ 1771 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1) 1772 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 1773 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, 1774 extract_simm21_a32_5}, 1775 1776 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */ 1777 #define SIMM25_A32_5 (SIMM21_A32_5 + 1) 1778 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 1779 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, 1780 extract_simm25_a32_5}, 1781 1782 /* SIMM13_A32_5_S mask = 0000011111111111. */ 1783 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1) 1784 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 1785 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, 1786 extract_simm13_a32_5_s}, 1787 1788 /* SIMM8_A16_9_S mask = 0000000001111111. */ 1789 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1) 1790 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 1791 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, 1792 extract_simm8_a16_9_s}, 1793 1794 /* UIMM3_23 mask = 00000000000000000000000111000000. */ 1795 #define UIMM3_23 (SIMM8_A16_9_S + 1) 1796 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23}, 1797 1798 /* UIMM10_6_S mask = 0000001111111111. */ 1799 #define UIMM10_6_S (UIMM3_23 + 1) 1800 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s}, 1801 1802 /* UIMM6_11_S mask = 0000002200011110. */ 1803 #define UIMM6_11_S (UIMM10_6_S + 1) 1804 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s}, 1805 1806 /* SIMM9_8 mask = 00000000111111112000000000000000. */ 1807 #define SIMM9_8 (UIMM6_11_S + 1) 1808 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, 1809 insert_simm9_8, extract_simm9_8}, 1810 1811 /* UIMM10_A32_8_S mask = 0000000011111111. */ 1812 #define UIMM10_A32_8_S (SIMM9_8 + 1) 1813 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 1814 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, 1815 extract_uimm10_a32_8_s}, 1816 1817 /* SIMM9_7_S mask = 0000000111111111. */ 1818 #define SIMM9_7_S (UIMM10_A32_8_S + 1) 1819 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, 1820 extract_simm9_7_s}, 1821 1822 /* UIMM6_A16_11_S mask = 0000000000011111. */ 1823 #define UIMM6_A16_11_S (SIMM9_7_S + 1) 1824 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 1825 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, 1826 extract_uimm6_a16_11_s}, 1827 1828 /* UIMM5_A32_11_S mask = 0000020000011000. */ 1829 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1) 1830 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 1831 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, 1832 extract_uimm5_a32_11_s}, 1833 1834 /* SIMM11_A32_13_S mask = 0000022222200111. */ 1835 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1) 1836 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 1837 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s}, 1838 1839 /* UIMM7_13_S mask = 0000000022220111. */ 1840 #define UIMM7_13_S (SIMM11_A32_13_S + 1) 1841 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s}, 1842 1843 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */ 1844 #define UIMM6_A16_21 (UIMM7_13_S + 1) 1845 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 1846 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21}, 1847 1848 /* UIMM7_11_S mask = 0000022200011110. */ 1849 #define UIMM7_11_S (UIMM6_A16_21 + 1) 1850 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s}, 1851 1852 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */ 1853 #define UIMM7_A16_20 (UIMM7_11_S + 1) 1854 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 1855 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, 1856 extract_uimm7_a16_20}, 1857 1858 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */ 1859 #define SIMM13_A16_20 (UIMM7_A16_20 + 1) 1860 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 1861 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, 1862 extract_simm13_a16_20}, 1863 1864 /* UIMM8_8_S mask = 0000000011111111. */ 1865 #define UIMM8_8_S (SIMM13_A16_20 + 1) 1866 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s}, 1867 1868 /* W6 mask = 00000000000000000000111111000000. */ 1869 #define W6 (UIMM8_8_S + 1) 1870 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6}, 1871 1872 /* UIMM6_5_S mask = 0000011111100000. */ 1873 #define UIMM6_5_S (W6 + 1) 1874 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s}, 1875 1876 /* ARC NPS400 Support: See comment near head of file. */ 1877 #define NPS_R_DST_3B (UIMM6_5_S + 1) 1878 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst }, 1879 1880 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1) 1881 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst }, 1882 1883 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1) 1884 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 }, 1885 1886 #define NPS_R_DST (NPS_R_SRC2_3B + 1) 1887 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL }, 1888 1889 #define NPS_R_SRC1 (NPS_R_DST + 1) 1890 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL }, 1891 1892 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1) 1893 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, 1894 1895 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1) 1896 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, 1897 1898 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1) 1899 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size }, 1900 1901 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1) 1902 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size }, 1903 1904 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1) 1905 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b }, 1906 1907 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1) 1908 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 }, 1909 1910 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1) 1911 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 1912 1913 #define NPS_SIMM16 (NPS_UIMM16 + 1) 1914 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL }, 1915 1916 #define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1) 1917 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 }, 1918 1919 #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1) 1920 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 }, 1921 1922 #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1) 1923 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos }, 1924 1925 #define NPS_SRC1_POS (NPS_SRC2_POS + 1) 1926 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos }, 1927 1928 #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1) 1929 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size }, 1930 1931 #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1) 1932 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size }, 1933 1934 #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1) 1935 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size }, 1936 1937 #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1) 1938 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size }, 1939 1940 #define NPS_R_XLDST (NPS_WXORB_SIZE + 1) 1941 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL }, 1942 1943 #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1) 1944 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 1945 1946 #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1) 1947 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size }, 1948 1949 #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1) 1950 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 }, 1951 1952 #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1) 1953 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 }, 1954 1955 #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1) 1956 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 }, 1957 1958 #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1) 1959 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size }, 1960 1961 #define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1) 1962 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst_short, extract_nps_3bit_dst_short }, 1963 1964 #define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1) 1965 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst_short, extract_nps_3bit_dst_short }, 1966 1967 #define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1) 1968 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2_short, extract_nps_3bit_src2_short }, 1969 1970 #define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1) 1971 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size }, 1972 1973 #define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1) 1974 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size }, 1975 1976 #define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1) 1977 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 }, 1978 1979 #define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1) 1980 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 1981 1982 #define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1) 1983 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 1984 1985 #define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1) 1986 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 1987 1988 #define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1) 1989 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 1990 1991 #define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1) 1992 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 1993 1994 #define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1) 1995 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 1996 1997 #define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1) 1998 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 1999 2000 #define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1) 2001 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2002 2003 #define NPS_BITOP_MOD4_MSB (NPS_BITOP_SRC_POS1 + 1) 2004 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4_msb, extract_nps_bitop_mod4_msb }, 2005 2006 #define NPS_BITOP_MOD4_LSB (NPS_BITOP_MOD4_MSB + 1) 2007 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4_lsb, extract_nps_bitop_mod4_lsb }, 2008 2009 #define NPS_BITOP_MOD3 (NPS_BITOP_MOD4_LSB + 1) 2010 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2011 2012 #define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1) 2013 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2014 2015 #define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1) 2016 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2017 2018 #define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1) 2019 { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext }, 2020 2021 #define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1) 2022 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2023 2024 #define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1) 2025 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size }, 2026 2027 #define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1) 2028 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor }, 2029 2030 #define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1) 2031 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble }, 2032 2033 #define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1) 2034 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2035 2036 #define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1) 2037 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len }, 2038 2039 #define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1) 2040 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs }, 2041 2042 #define NPS_PSBC (NPS_MIN_HOFS + 1) 2043 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2044 2045 #define NPS_DPI_DST (NPS_PSBC + 1) 2046 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL }, 2047 2048 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B but doesn't duplicate an operand */ 2049 #define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1) 2050 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst }, 2051 2052 #define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1) 2053 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width }, 2054 2055 #define NPS_HASH_PERM (NPS_HASH_WIDTH + 1) 2056 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2057 2058 #define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1) 2059 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2060 2061 #define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1) 2062 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2063 2064 #define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1) 2065 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len }, 2066 2067 #define NPS_HASH_OFS (NPS_HASH_LEN + 1) 2068 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2069 2070 #define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1) 2071 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2072 2073 #define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1) 2074 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2075 2076 #define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1) 2077 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2078 2079 #define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1) 2080 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2081 2082 #define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1) 2083 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 }, 2084 }; 2085 2086 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); 2087 2088 const unsigned arc_Toperand = FKT_T; 2089 const unsigned arc_NToperand = FKT_NT; 2090 2091 const unsigned char arg_none[] = { 0 }; 2092 const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC }; 2093 const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC }; 2094 const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC }; 2095 const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 }; 2096 const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 }; 2097 const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 }; 2098 const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 }; 2099 const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC }; 2100 const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM }; 2101 const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC }; 2102 const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM }; 2103 2104 const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM }; 2105 const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 }; 2106 const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 }; 2107 2108 const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 }; 2109 const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup }; 2110 const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup }; 2111 2112 const unsigned char arg_32bit_rbrc[] = { RB, RC }; 2113 const unsigned char arg_32bit_zarc[] = { ZA, RC }; 2114 const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 }; 2115 const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 }; 2116 const unsigned char arg_32bit_rblimm[] = { RB, LIMM }; 2117 const unsigned char arg_32bit_zalimm[] = { ZA, LIMM }; 2118 2119 const unsigned char arg_32bit_limmrc[] = { LIMM, RC }; 2120 const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 }; 2121 const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 }; 2122 const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup }; 2123 2124 const unsigned char arg_32bit_rc[] = { RC }; 2125 const unsigned char arg_32bit_u6[] = { UIMM6_20 }; 2126 const unsigned char arg_32bit_limm[] = { LIMM }; 2127 2128 /* The opcode table. 2129 2130 The format of the opcode table is: 2131 2132 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. 2133 2134 The table is organised such that, where possible, all instructions with 2135 the same mnemonic are together in a block. When the assembler searches 2136 for a suitable instruction the entries are checked in table order, so 2137 more specific, or specialised cases should appear earlier in the table. 2138 2139 As an example, consider two instructions 'add a,b,u6' and 'add 2140 a,b,limm'. The first takes a 6-bit immediate that is encoded within the 2141 32-bit instruction, while the second takes a 32-bit immediate that is 2142 encoded in a follow-on 32-bit, making the total instruction length 2143 64-bits. In this case the u6 variant must appear first in the table, as 2144 all u6 immediates could also be encoded using the 'limm' extension, 2145 however, we want to use the shorter instruction wherever possible. 2146 2147 It is possible though to split instructions with the same mnemonic into 2148 multiple groups. However, the instructions are still checked in table 2149 order, even across groups. The only time that instructions with the 2150 same mnemonic should be split into different groups is when different 2151 variants of the instruction appear in different architectures, in which 2152 case, grouping all instructions from a particular architecture together 2153 might be preferable to merging the instruction into the main instruction 2154 table. 2155 2156 An example of this split instruction groups can be found with the 'sync' 2157 instruction. The core arc architecture provides a 'sync' instruction, 2158 while the nps instruction set extension provides 'sync.rd' and 2159 'sync.wr'. The rd/wr flags are instruction flags, not part of the 2160 mnemonic, so we end up with two groups for the sync instruction, the 2161 first within the core arc instruction table, and the second within the 2162 nps extension instructions. */ 2163 const struct arc_opcode arc_opcodes[] = 2164 { 2165 #include "arc-tbl.h" 2166 #include "arc-nps400-tbl.h" 2167 #include "arc-ext-tbl.h" 2168 2169 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } 2170 }; 2171 2172 /* List with special cases instructions and the applicable flags. */ 2173 const struct arc_flag_special arc_flag_special_cases[] = 2174 { 2175 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2176 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2177 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2178 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2179 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2180 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2181 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2182 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2183 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2184 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2185 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2186 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2187 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2188 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2189 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2190 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2191 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2192 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2193 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2194 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2195 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2196 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2197 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2198 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2199 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2200 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2201 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2202 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2203 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, 2204 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } 2205 }; 2206 2207 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases); 2208 2209 /* Relocations. */ 2210 const struct arc_reloc_equiv_tab arc_reloc_equiv[] = 2211 { 2212 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL }, 2213 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, 2214 { "sda", "st", { F_ASFAKE, F_H1, F_NULL }, 2215 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, 2216 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL }, 2217 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, 2218 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL }, 2219 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, 2220 2221 /* Next two entries will cover the undefined behavior ldb/stb with 2222 address scaling. */ 2223 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL }, 2224 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, 2225 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL }, 2226 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST}, 2227 2228 { "sda", "ld", { F_ASFAKE, F_NULL }, 2229 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, 2230 { "sda", "st", { F_ASFAKE, F_NULL }, 2231 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, 2232 { "sda", "ldd", { F_ASFAKE, F_NULL }, 2233 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, 2234 { "sda", "std", { F_ASFAKE, F_NULL }, 2235 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, 2236 2237 /* Short instructions. */ 2238 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD }, 2239 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 }, 2240 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 }, 2241 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 }, 2242 2243 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME }, 2244 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, 2245 2246 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL, 2247 BFD_RELOC_ARC_S25H_PCREL_PLT }, 2248 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL, 2249 BFD_RELOC_ARC_S21H_PCREL_PLT }, 2250 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL, 2251 BFD_RELOC_ARC_S25W_PCREL_PLT }, 2252 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL, 2253 BFD_RELOC_ARC_S21W_PCREL_PLT }, 2254 2255 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 } 2256 }; 2257 2258 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv); 2259 2260 const struct arc_pseudo_insn arc_pseudo_insns[] = 2261 { 2262 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, 2263 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 }, 2264 { BRAKETdup, 1, 0, 4} } }, 2265 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, 2266 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 }, 2267 { BRAKETdup, 1, 0, 4} } }, 2268 2269 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, 2270 { SIMM9_A16_8, 0, 0, 2 } } }, 2271 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2272 { SIMM9_A16_8, 0, 0, 2 } } }, 2273 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, 2274 { SIMM9_A16_8, 0, 0, 2 } } }, 2275 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, 2276 { SIMM9_A16_8, 0, 0, 2 } } }, 2277 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2278 { SIMM9_A16_8, 0, 0, 2 } } }, 2279 2280 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, 2281 { SIMM9_A16_8, 0, 0, 2 } } }, 2282 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2283 { SIMM9_A16_8, 0, 0, 2 } } }, 2284 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, 2285 { SIMM9_A16_8, 0, 0, 2 } } }, 2286 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, 2287 { SIMM9_A16_8, 0, 0, 2 } } }, 2288 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2289 { SIMM9_A16_8, 0, 0, 2 } } }, 2290 2291 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, 2292 { SIMM9_A16_8, 0, 0, 2 } } }, 2293 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2294 { SIMM9_A16_8, 0, 0, 2 } } }, 2295 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, 2296 { SIMM9_A16_8, 0, 0, 2 } } }, 2297 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, 2298 { SIMM9_A16_8, 0, 0, 2 } } }, 2299 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2300 { SIMM9_A16_8, 0, 0, 2 } } }, 2301 2302 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, 2303 { SIMM9_A16_8, 0, 0, 2 } } }, 2304 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2305 { SIMM9_A16_8, 0, 0, 2 } } }, 2306 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, 2307 { SIMM9_A16_8, 0, 0, 2 } } }, 2308 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, 2309 { SIMM9_A16_8, 0, 0, 2 } } }, 2310 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2311 { SIMM9_A16_8, 0, 0, 2 } } }, 2312 }; 2313 2314 const unsigned arc_num_pseudo_insn = 2315 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns); 2316 2317 const struct arc_aux_reg arc_aux_regs[] = 2318 { 2319 #undef DEF 2320 #define DEF(ADDR, CPU, SUBCLASS, NAME) \ 2321 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 }, 2322 2323 #include "arc-regs.h" 2324 2325 #undef DEF 2326 }; 2327 2328 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs); 2329 2330 /* NOTE: The order of this array MUST be consistent with 'enum 2331 arc_rlx_types' located in tc-arc.h! */ 2332 const struct arc_opcode arc_relax_opcodes[] = 2333 { 2334 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } }, 2335 2336 /* bl_s s13 11111sssssssssss. */ 2337 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2338 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, 2339 { SIMM13_A32_5_S }, { 0 }}, 2340 2341 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ 2342 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2343 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, 2344 { SIMM25_A32_5 }, { C_D }}, 2345 2346 /* b_s s10 1111000sssssssss. */ 2347 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2348 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, 2349 { SIMM10_A16_7_S }, { 0 }}, 2350 2351 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */ 2352 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2353 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, 2354 { SIMM25_A16_5 }, { C_D }}, 2355 2356 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */ 2357 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2358 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2359 { RC_S, RB_S, UIMM3_13_S }, { 0 }}, 2360 2361 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants 2362 UIMM6_20_PCREL. */ 2363 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2364 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2365 { RA, RB, UIMM6_20 }, { C_F }}, 2366 2367 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */ 2368 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2369 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2370 { RA, RB, LIMM }, { C_F }}, 2371 2372 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */ 2373 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2374 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2375 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, 2376 2377 /* ld<.di><.aa><.x><zz> a,b,s9 2378 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */ 2379 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2380 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2381 { RA, BRAKET, RB, SIMM9_8, BRAKETdup }, 2382 { C_ZZ23, C_DI20, C_AA21, C_X25 }}, 2383 2384 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */ 2385 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2386 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2387 { RA, BRAKET, RB, LIMM, BRAKETdup }, 2388 { C_ZZ13, C_DI16, C_AA8, C_X15 }}, 2389 2390 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */ 2391 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2392 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2393 { RB_S, UIMM8_8_S }, { 0 }}, 2394 2395 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants 2396 SIMM12_20_PCREL. */ 2397 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2398 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2399 { RB, SIMM12_20 }, { C_F }}, 2400 2401 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */ 2402 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2403 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2404 { RB, LIMM }, { C_F }}, 2405 2406 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */ 2407 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2408 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2409 { RC_S, RB_S, UIMM3_13_S }, { 0 }}, 2410 2411 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. 2412 UIMM6_20_PCREL. */ 2413 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2414 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2415 { RA, RB, UIMM6_20 }, { C_F }}, 2416 2417 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ 2418 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2419 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2420 { RA, RB, LIMM }, { C_F }}, 2421 2422 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. 2423 UIMM6_20_PCREL. */ 2424 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM 2425 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }}, 2426 2427 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */ 2428 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM 2429 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }}, 2430 2431 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. 2432 UIMM6_20_PCREL. */ 2433 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2434 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2435 { RB, UIMM6_20 }, { C_F, C_CC }}, 2436 2437 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */ 2438 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2439 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2440 { RB, LIMM }, { C_F, C_CC }}, 2441 2442 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. 2443 UIMM6_20_PCREL. */ 2444 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2445 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2446 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, 2447 2448 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */ 2449 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2450 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2451 { RB, RBdup, LIMM }, { C_F, C_CC }} 2452 }; 2453 2454 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes); 2455 2456 /* The following instructions are all either 48 or 64 bits long, and 2457 require special handling in the assembler and disassembler. 2458 2459 The first part of each ARC_LONG_OPCODE is the base ARC_OPCODE, this is 2460 either the 16 or 32 bit base instruction, and its opcode list will 2461 always end in a LIMM. 2462 2463 The rest of the ARC_LONG_OPCODE describes how to build the LIMM from the 2464 instruction operands. There are therefore two lists of operands for 2465 each ARC_LONG_OPCODE, the second list contains operands that are merged 2466 into the limm template, in the same way that a standard 32-bit 2467 instruction is built. This generated limm is then added to the list of 2468 tokens that is passed to the standard instruction encoder, along with 2469 the first list of operands (from the base arc_opcode). 2470 2471 The first list of operands then, describes how to build the base 2472 instruction, and includes the 32-bit limm that was previously generated 2473 as the last operand. 2474 2475 In most cases operands are either encoded into the base instruction or 2476 into the limm. When this happens the operand slot will be filled with 2477 an operand identifier in one list, and will be IGNORED in the other 2478 list, this special operand value causes the operand to be ignored, 2479 without being encoded at this point. 2480 2481 However, in some cases, an operand is split between the base instruction 2482 and the 32-bit limm, in this case the operand slot will be filled in 2483 both operand lists (see mov4b for one example of this). */ 2484 const struct arc_long_opcode arc_long_opcodes[] = 2485 { 2486 /* mrgb - (48 bit instruction). */ 2487 { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }}, 2488 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }}, 2489 2490 /* mrgb.cl - (48 bit instruction). */ 2491 { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }}, 2492 0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }}, 2493 2494 /* mov2b - (48 bit instruction). */ 2495 { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }}, 2496 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }}, 2497 2498 /* mov2b.cl - (48 bit instruction). */ 2499 { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }}, 2500 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }}, 2501 2502 /* ext4 - (48 bit instruction). */ 2503 { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }}, 2504 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }}, 2505 2506 /* ext4.cl - (48 bit instruction). */ 2507 { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }}, 2508 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }}, 2509 2510 /* ins4 - (48 bit instruction). */ 2511 { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }}, 2512 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }}, 2513 2514 /* ins4.cl - (48 bit instruction). */ 2515 { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }}, 2516 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }}, 2517 2518 /* mov3b - (64 bit instruction). */ 2519 { { "mov3b", 0x58100000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }}, 2520 0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }}, 2521 2522 /* mov4b - (64 bit instruction). */ 2523 { { "mov4b", 0x58100000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }}, 2524 0x00000000, 0x00000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}}, 2525 2526 /* mov3bcl - (64 bit instruction). */ 2527 { { "mov3bcl", 0x58110000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }}, 2528 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }}, 2529 2530 /* mov4bcl - (64 bit instruction). */ 2531 { { "mov4bcl", 0x58110000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }}, 2532 0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}}, 2533 2534 /* mov3b.cl - (64 bit instruction). */ 2535 { { "mov3b", 0x58110000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { C_NPS_CL }}, 2536 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }}, 2537 2538 /* mov4b.cl - (64 bit instruction). */ 2539 { { "mov4b", 0x58110000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { C_NPS_CL }}, 2540 0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}}, 2541 }; 2542 2543 const unsigned arc_num_long_opcodes = ARRAY_SIZE (arc_long_opcodes); 2544
