1 /* ppc-opc.c -- PowerPC opcode list 2 Copyright (C) 1994-2016 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include <stdio.h> 24 #include "opcode/ppc.h" 25 #include "opintl.h" 26 27 /* This file holds the PowerPC opcode table. The opcode table 28 includes almost all of the extended instruction mnemonics. This 29 permits the disassembler to use them, and simplifies the assembler 30 logic, at the cost of increasing the table size. The table is 31 strictly constant data, so the compiler should be able to put it in 32 the .text section. 33 34 This file also holds the operand table. All knowledge about 35 inserting operands into instructions and vice-versa is kept in this 36 file. */ 37 38 /* Local insertion and extraction functions. */ 40 41 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **); 42 static long extract_arx (unsigned long, ppc_cpu_t, int *); 43 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **); 44 static long extract_ary (unsigned long, ppc_cpu_t, int *); 45 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **); 46 static long extract_bat (unsigned long, ppc_cpu_t, int *); 47 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **); 48 static long extract_bba (unsigned long, ppc_cpu_t, int *); 49 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **); 50 static long extract_bdm (unsigned long, ppc_cpu_t, int *); 51 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **); 52 static long extract_bdp (unsigned long, ppc_cpu_t, int *); 53 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **); 54 static long extract_bo (unsigned long, ppc_cpu_t, int *); 55 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **); 56 static long extract_boe (unsigned long, ppc_cpu_t, int *); 57 static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **); 58 static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **); 59 static long extract_dcmxs (unsigned long, ppc_cpu_t, int *); 60 static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **); 61 static long extract_dxd (unsigned long, ppc_cpu_t, int *); 62 static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **); 63 static long extract_dxdn (unsigned long, ppc_cpu_t, int *); 64 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); 65 static long extract_fxm (unsigned long, ppc_cpu_t, int *); 66 static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **); 67 static long extract_l0 (unsigned long, ppc_cpu_t, int *); 68 static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **); 69 static long extract_l1 (unsigned long, ppc_cpu_t, int *); 70 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **); 71 static long extract_li20 (unsigned long, ppc_cpu_t, int *); 72 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **); 73 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **); 74 static long extract_mbe (unsigned long, ppc_cpu_t, int *); 75 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **); 76 static long extract_mb6 (unsigned long, ppc_cpu_t, int *); 77 static long extract_nb (unsigned long, ppc_cpu_t, int *); 78 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **); 79 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **); 80 static long extract_nsi (unsigned long, ppc_cpu_t, int *); 81 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **); 82 static long extract_oimm (unsigned long, ppc_cpu_t, int *); 83 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **); 84 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **); 85 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **); 86 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **); 87 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **); 88 static long extract_rbs (unsigned long, ppc_cpu_t, int *); 89 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **); 90 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **); 91 static long extract_rx (unsigned long, ppc_cpu_t, int *); 92 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **); 93 static long extract_ry (unsigned long, ppc_cpu_t, int *); 94 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **); 95 static long extract_sh6 (unsigned long, ppc_cpu_t, int *); 96 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **); 97 static long extract_sci8 (unsigned long, ppc_cpu_t, int *); 98 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **); 99 static long extract_sci8n (unsigned long, ppc_cpu_t, int *); 100 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **); 101 static long extract_sd4h (unsigned long, ppc_cpu_t, int *); 102 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **); 103 static long extract_sd4w (unsigned long, ppc_cpu_t, int *); 104 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **); 105 static long extract_spr (unsigned long, ppc_cpu_t, int *); 106 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **); 107 static long extract_sprg (unsigned long, ppc_cpu_t, int *); 108 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **); 109 static long extract_tbr (unsigned long, ppc_cpu_t, int *); 110 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **); 111 static long extract_xt6 (unsigned long, ppc_cpu_t, int *); 112 static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **); 113 static long extract_xtq6 (unsigned long, ppc_cpu_t, int *); 114 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **); 115 static long extract_xa6 (unsigned long, ppc_cpu_t, int *); 116 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **); 117 static long extract_xb6 (unsigned long, ppc_cpu_t, int *); 118 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **); 119 static long extract_xb6s (unsigned long, ppc_cpu_t, int *); 120 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **); 121 static long extract_xc6 (unsigned long, ppc_cpu_t, int *); 122 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **); 123 static long extract_dm (unsigned long, ppc_cpu_t, int *); 124 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **); 125 static long extract_vlesi (unsigned long, ppc_cpu_t, int *); 126 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **); 127 static long extract_vlensi (unsigned long, ppc_cpu_t, int *); 128 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **); 129 static long extract_vleui (unsigned long, ppc_cpu_t, int *); 130 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **); 131 static long extract_vleil (unsigned long, ppc_cpu_t, int *); 132 133 /* The operands table. 135 136 The fields are bitm, shift, insert, extract, flags. 137 138 We used to put parens around the various additions, like the one 139 for BA just below. However, that caused trouble with feeble 140 compilers with a limit on depth of a parenthesized expression, like 141 (reportedly) the compiler in Microsoft Developer Studio 5. So we 142 omit the parens, since the macros are never used in a context where 143 the addition will be ambiguous. */ 144 145 const struct powerpc_operand powerpc_operands[] = 146 { 147 /* The zero index is used to indicate the end of the list of 148 operands. */ 149 #define UNUSED 0 150 { 0, 0, NULL, NULL, 0 }, 151 152 /* The BA field in an XL form instruction. */ 153 #define BA UNUSED + 1 154 /* The BI field in a B form or XL form instruction. */ 155 #define BI BA 156 #define BI_MASK (0x1f << 16) 157 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, 158 159 /* The BA field in an XL form instruction when it must be the same 160 as the BT field in the same instruction. */ 161 #define BAT BA + 1 162 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, 163 164 /* The BB field in an XL form instruction. */ 165 #define BB BAT + 1 166 #define BB_MASK (0x1f << 11) 167 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, 168 169 /* The BB field in an XL form instruction when it must be the same 170 as the BA field in the same instruction. */ 171 #define BBA BB + 1 172 /* The VB field in a VX form instruction when it must be the same 173 as the VA field in the same instruction. */ 174 #define VBA BBA 175 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, 176 177 /* The BD field in a B form instruction. The lower two bits are 178 forced to zero. */ 179 #define BD BBA + 1 180 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 181 182 /* The BD field in a B form instruction when absolute addressing is 183 used. */ 184 #define BDA BD + 1 185 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 186 187 /* The BD field in a B form instruction when the - modifier is used. 188 This sets the y bit of the BO field appropriately. */ 189 #define BDM BDA + 1 190 { 0xfffc, 0, insert_bdm, extract_bdm, 191 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 192 193 /* The BD field in a B form instruction when the - modifier is used 194 and absolute address is used. */ 195 #define BDMA BDM + 1 196 { 0xfffc, 0, insert_bdm, extract_bdm, 197 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 198 199 /* The BD field in a B form instruction when the + modifier is used. 200 This sets the y bit of the BO field appropriately. */ 201 #define BDP BDMA + 1 202 { 0xfffc, 0, insert_bdp, extract_bdp, 203 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 204 205 /* The BD field in a B form instruction when the + modifier is used 206 and absolute addressing is used. */ 207 #define BDPA BDP + 1 208 { 0xfffc, 0, insert_bdp, extract_bdp, 209 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 210 211 /* The BF field in an X or XL form instruction. */ 212 #define BF BDPA + 1 213 /* The CRFD field in an X form instruction. */ 214 #define CRFD BF 215 /* The CRD field in an XL form instruction. */ 216 #define CRD BF 217 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, 218 219 /* The BF field in an X or XL form instruction. */ 220 #define BFF BF + 1 221 { 0x7, 23, NULL, NULL, 0 }, 222 223 /* An optional BF field. This is used for comparison instructions, 224 in which an omitted BF field is taken as zero. */ 225 #define OBF BFF + 1 226 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 227 228 /* The BFA field in an X or XL form instruction. */ 229 #define BFA OBF + 1 230 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, 231 232 /* The BO field in a B form instruction. Certain values are 233 illegal. */ 234 #define BO BFA + 1 235 #define BO_MASK (0x1f << 21) 236 { 0x1f, 21, insert_bo, extract_bo, 0 }, 237 238 /* The BO field in a B form instruction when the + or - modifier is 239 used. This is like the BO field, but it must be even. */ 240 #define BOE BO + 1 241 { 0x1e, 21, insert_boe, extract_boe, 0 }, 242 243 /* The RM field in an X form instruction. */ 244 #define RM BOE + 1 245 { 0x3, 11, NULL, NULL, 0 }, 246 247 #define BH RM + 1 248 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 249 250 /* The BT field in an X or XL form instruction. */ 251 #define BT BH + 1 252 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, 253 254 /* The BI16 field in a BD8 form instruction. */ 255 #define BI16 BT + 1 256 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, 257 258 /* The BI32 field in a BD15 form instruction. */ 259 #define BI32 BI16 + 1 260 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, 261 262 /* The BO32 field in a BD15 form instruction. */ 263 #define BO32 BI32 + 1 264 { 0x3, 20, NULL, NULL, 0 }, 265 266 /* The B8 field in a BD8 form instruction. */ 267 #define B8 BO32 + 1 268 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 269 270 /* The B15 field in a BD15 form instruction. The lowest bit is 271 forced to zero. */ 272 #define B15 B8 + 1 273 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 274 275 /* The B24 field in a BD24 form instruction. The lowest bit is 276 forced to zero. */ 277 #define B24 B15 + 1 278 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 279 280 /* The condition register number portion of the BI field in a B form 281 or XL form instruction. This is used for the extended 282 conditional branch mnemonics, which set the lower two bits of the 283 BI field. This field is optional. */ 284 #define CR B24 + 1 285 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 286 287 /* The CRB field in an X form instruction. */ 288 #define CRB CR + 1 289 /* The MB field in an M form instruction. */ 290 #define MB CRB 291 #define MB_MASK (0x1f << 6) 292 { 0x1f, 6, NULL, NULL, 0 }, 293 294 /* The CRD32 field in an XL form instruction. */ 295 #define CRD32 CRB + 1 296 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, 297 298 /* The CRFS field in an X form instruction. */ 299 #define CRFS CRD32 + 1 300 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, 301 302 #define CRS CRFS + 1 303 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 304 305 /* The CT field in an X form instruction. */ 306 #define CT CRS + 1 307 /* The MO field in an mbar instruction. */ 308 #define MO CT 309 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 310 311 /* The D field in a D form instruction. This is a displacement off 312 a register, and implies that the next operand is a register in 313 parentheses. */ 314 #define D CT + 1 315 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 316 317 /* The D8 field in a D form instruction. This is a displacement off 318 a register, and implies that the next operand is a register in 319 parentheses. */ 320 #define D8 D + 1 321 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 322 323 /* The DCMX field in an X form instruction. */ 324 #define DCMX D8 + 1 325 { 0x7f, 16, NULL, NULL, 0 }, 326 327 /* The split DCMX field in an X form instruction. */ 328 #define DCMXS DCMX + 1 329 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 }, 330 331 /* The DQ field in a DQ form instruction. This is like D, but the 332 lower four bits are forced to zero. */ 333 #define DQ DCMXS + 1 334 { 0xfff0, 0, NULL, NULL, 335 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 336 337 /* The DS field in a DS form instruction. This is like D, but the 338 lower two bits are forced to zero. */ 339 #define DS DQ + 1 340 { 0xfffc, 0, NULL, NULL, 341 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 342 343 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits 344 unsigned imediate */ 345 #define DUIS DS + 1 346 #define BHRBE DUIS 347 { 0x3ff, 11, NULL, NULL, 0 }, 348 349 /* The split D field in a DX form instruction. */ 350 #define DXD DUIS + 1 351 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd, 352 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, 353 354 /* The split ND field in a DX form instruction. 355 This is the same as the DX field, only negated. */ 356 #define NDXD DXD + 1 357 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn, 358 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, 359 360 /* The E field in a wrteei instruction. */ 361 /* And the W bit in the pair singles instructions. */ 362 /* And the ST field in a VX form instruction. */ 363 #define E NDXD + 1 364 #define PSW E 365 #define ST E 366 { 0x1, 15, NULL, NULL, 0 }, 367 368 /* The FL1 field in a POWER SC form instruction. */ 369 #define FL1 E + 1 370 /* The U field in an X form instruction. */ 371 #define U FL1 372 { 0xf, 12, NULL, NULL, 0 }, 373 374 /* The FL2 field in a POWER SC form instruction. */ 375 #define FL2 FL1 + 1 376 { 0x7, 2, NULL, NULL, 0 }, 377 378 /* The FLM field in an XFL form instruction. */ 379 #define FLM FL2 + 1 380 { 0xff, 17, NULL, NULL, 0 }, 381 382 /* The FRA field in an X or A form instruction. */ 383 #define FRA FLM + 1 384 #define FRA_MASK (0x1f << 16) 385 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, 386 387 /* The FRAp field of DFP instructions. */ 388 #define FRAp FRA + 1 389 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR }, 390 391 /* The FRB field in an X or A form instruction. */ 392 #define FRB FRAp + 1 393 #define FRB_MASK (0x1f << 11) 394 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, 395 396 /* The FRBp field of DFP instructions. */ 397 #define FRBp FRB + 1 398 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR }, 399 400 /* The FRC field in an A form instruction. */ 401 #define FRC FRBp + 1 402 #define FRC_MASK (0x1f << 6) 403 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, 404 405 /* The FRS field in an X form instruction or the FRT field in a D, X 406 or A form instruction. */ 407 #define FRS FRC + 1 408 #define FRT FRS 409 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, 410 411 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP 412 instructions. */ 413 #define FRSp FRS + 1 414 #define FRTp FRSp 415 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR }, 416 417 /* The FXM field in an XFX instruction. */ 418 #define FXM FRSp + 1 419 { 0xff, 12, insert_fxm, extract_fxm, 0 }, 420 421 /* Power4 version for mfcr. */ 422 #define FXM4 FXM + 1 423 { 0xff, 12, insert_fxm, extract_fxm, 424 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, 425 /* If the FXM4 operand is ommitted, use the sentinel value -1. */ 426 { -1, -1, NULL, NULL, 0}, 427 428 /* The IMM20 field in an LI instruction. */ 429 #define IMM20 FXM4 + 2 430 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, 431 432 /* The L field in a D or X form instruction. */ 433 #define L IMM20 + 1 434 /* The R field in a HTM X form instruction. */ 435 #define HTM_R L 436 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 437 438 /* The L field in an X form instruction which must be zero. */ 439 #define L0 L + 1 440 { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL }, 441 442 /* The L field in an X form instruction which must be one. */ 443 #define L1 L0 + 1 444 { 0x1, 21, insert_l1, extract_l1, 0 }, 445 446 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */ 447 #define SVC_LEV L1 + 1 448 { 0x7f, 5, NULL, NULL, 0 }, 449 450 /* The LEV field in an SC form instruction. */ 451 #define LEV SVC_LEV + 1 452 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, 453 454 /* The LI field in an I form instruction. The lower two bits are 455 forced to zero. */ 456 #define LI LEV + 1 457 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 458 459 /* The LI field in an I form instruction when used as an absolute 460 address. */ 461 #define LIA LI + 1 462 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 463 464 /* The LS or WC field in an X (sync or wait) form instruction. */ 465 #define LS LIA + 1 466 #define WC LS 467 { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL }, 468 469 /* The ME field in an M form instruction. */ 470 #define ME LS + 1 471 #define ME_MASK (0x1f << 1) 472 { 0x1f, 1, NULL, NULL, 0 }, 473 474 /* The MB and ME fields in an M form instruction expressed a single 475 operand which is a bitmask indicating which bits to select. This 476 is a two operand form using PPC_OPERAND_NEXT. See the 477 description in opcode/ppc.h for what this means. */ 478 #define MBE ME + 1 479 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, 480 { -1, 0, insert_mbe, extract_mbe, 0 }, 481 482 /* The MB or ME field in an MD or MDS form instruction. The high 483 bit is wrapped to the low end. */ 484 #define MB6 MBE + 2 485 #define ME6 MB6 486 #define MB6_MASK (0x3f << 5) 487 { 0x3f, 5, insert_mb6, extract_mb6, 0 }, 488 489 /* The NB field in an X form instruction. The value 32 is stored as 490 0. */ 491 #define NB MB6 + 1 492 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, 493 494 /* The NBI field in an lswi instruction, which has special value 495 restrictions. The value 32 is stored as 0. */ 496 #define NBI NB + 1 497 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 }, 498 499 /* The NSI field in a D form instruction. This is the same as the 500 SI field, only negated. */ 501 #define NSI NBI + 1 502 { 0xffff, 0, insert_nsi, extract_nsi, 503 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 504 505 /* The NSI field in a D form instruction when we accept a wide range 506 of positive values. */ 507 #define NSISIGNOPT NSI + 1 508 { 0xffff, 0, insert_nsi, extract_nsi, 509 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 510 511 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 512 #define RA NSISIGNOPT + 1 513 #define RA_MASK (0x1f << 16) 514 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, 515 516 /* As above, but 0 in the RA field means zero, not r0. */ 517 #define RA0 RA + 1 518 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, 519 520 /* The RA field in the DQ form lq or an lswx instruction, which have special 521 value restrictions. */ 522 #define RAQ RA0 + 1 523 #define RAX RAQ 524 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, 525 526 /* The RA field in a D or X form instruction which is an updating 527 load, which means that the RA field may not be zero and may not 528 equal the RT field. */ 529 #define RAL RAQ + 1 530 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, 531 532 /* The RA field in an lmw instruction, which has special value 533 restrictions. */ 534 #define RAM RAL + 1 535 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, 536 537 /* The RA field in a D or X form instruction which is an updating 538 store or an updating floating point load, which means that the RA 539 field may not be zero. */ 540 #define RAS RAM + 1 541 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, 542 543 /* The RA field of the tlbwe, dccci and iccci instructions, 544 which are optional. */ 545 #define RAOPT RAS + 1 546 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 547 548 /* The RB field in an X, XO, M, or MDS form instruction. */ 549 #define RB RAOPT + 1 550 #define RB_MASK (0x1f << 11) 551 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, 552 553 /* The RB field in an X form instruction when it must be the same as 554 the RS field in the instruction. This is used for extended 555 mnemonics like mr. */ 556 #define RBS RB + 1 557 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, 558 559 /* The RB field in an lswx instruction, which has special value 560 restrictions. */ 561 #define RBX RBS + 1 562 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR }, 563 564 /* The RB field of the dccci and iccci instructions, which are optional. */ 565 #define RBOPT RBX + 1 566 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 567 568 /* The RC register field in an maddld, maddhd or maddhdu instruction. */ 569 #define RC RBOPT + 1 570 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR }, 571 572 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 573 instruction or the RT field in a D, DS, X, XFX or XO form 574 instruction. */ 575 #define RS RC + 1 576 #define RT RS 577 #define RT_MASK (0x1f << 21) 578 #define RD RS 579 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, 580 581 /* The RS and RT fields of the DS form stq and DQ form lq instructions, 582 which have special value restrictions. */ 583 #define RSQ RS + 1 584 #define RTQ RSQ 585 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR }, 586 587 /* The RS field of the tlbwe instruction, which is optional. */ 588 #define RSO RSQ + 1 589 #define RTO RSO 590 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 591 592 /* The RX field of the SE_RR form instruction. */ 593 #define RX RSO + 1 594 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, 595 596 /* The ARX field of the SE_RR form instruction. */ 597 #define ARX RX + 1 598 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, 599 600 /* The RY field of the SE_RR form instruction. */ 601 #define RY ARX + 1 602 #define RZ RY 603 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, 604 605 /* The ARY field of the SE_RR form instruction. */ 606 #define ARY RY + 1 607 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, 608 609 /* The SCLSCI8 field in a D form instruction. */ 610 #define SCLSCI8 ARY + 1 611 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, 612 613 /* The SCLSCI8N field in a D form instruction. This is the same as the 614 SCLSCI8 field, only negated. */ 615 #define SCLSCI8N SCLSCI8 + 1 616 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, 617 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 618 619 /* The SD field of the SD4 form instruction. */ 620 #define SE_SD SCLSCI8N + 1 621 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, 622 623 /* The SD field of the SD4 form instruction, for halfword. */ 624 #define SE_SDH SE_SD + 1 625 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS }, 626 627 /* The SD field of the SD4 form instruction, for word. */ 628 #define SE_SDW SE_SDH + 1 629 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS }, 630 631 /* The SH field in an X or M form instruction. */ 632 #define SH SE_SDW + 1 633 #define SH_MASK (0x1f << 11) 634 /* The other UIMM field in a EVX form instruction. */ 635 #define EVUIMM SH 636 /* The FC field in an atomic X form instruction. */ 637 #define FC SH 638 { 0x1f, 11, NULL, NULL, 0 }, 639 640 /* The SI field in a HTM X form instruction. */ 641 #define HTM_SI SH + 1 642 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, 643 644 /* The SH field in an MD form instruction. This is split. */ 645 #define SH6 HTM_SI + 1 646 #define SH6_MASK ((0x1f << 11) | (1 << 1)) 647 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, 648 649 /* The SH field of the tlbwe instruction, which is optional. */ 650 #define SHO SH6 + 1 651 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 652 653 /* The SI field in a D form instruction. */ 654 #define SI SHO + 1 655 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 656 657 /* The SI field in a D form instruction when we accept a wide range 658 of positive values. */ 659 #define SISIGNOPT SI + 1 660 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 661 662 /* The SI8 field in a D form instruction. */ 663 #define SI8 SISIGNOPT + 1 664 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 665 666 /* The SPR field in an XFX form instruction. This is flipped--the 667 lower 5 bits are stored in the upper 5 and vice- versa. */ 668 #define SPR SI8 + 1 669 #define PMR SPR 670 #define TMR SPR 671 #define SPR_MASK (0x3ff << 11) 672 { 0x3ff, 11, insert_spr, extract_spr, 0 }, 673 674 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 675 #define SPRBAT SPR + 1 676 #define SPRBAT_MASK (0x3 << 17) 677 { 0x3, 17, NULL, NULL, 0 }, 678 679 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 680 #define SPRG SPRBAT + 1 681 { 0x1f, 16, insert_sprg, extract_sprg, 0 }, 682 683 /* The SR field in an X form instruction. */ 684 #define SR SPRG + 1 685 /* The 4-bit UIMM field in a VX form instruction. */ 686 #define UIMM4 SR 687 { 0xf, 16, NULL, NULL, 0 }, 688 689 /* The STRM field in an X AltiVec form instruction. */ 690 #define STRM SR + 1 691 /* The T field in a tlbilx form instruction. */ 692 #define T STRM 693 { 0x3, 21, NULL, NULL, 0 }, 694 695 /* The ESYNC field in an X (sync) form instruction. */ 696 #define ESYNC STRM + 1 697 { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL }, 698 699 /* The SV field in a POWER SC form instruction. */ 700 #define SV ESYNC + 1 701 { 0x3fff, 2, NULL, NULL, 0 }, 702 703 /* The TBR field in an XFX form instruction. This is like the SPR 704 field, but it is optional. */ 705 #define TBR SV + 1 706 { 0x3ff, 11, insert_tbr, extract_tbr, 707 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, 708 /* If the TBR operand is ommitted, use the value 268. */ 709 { -1, 268, NULL, NULL, 0}, 710 711 /* The TO field in a D or X form instruction. */ 712 #define TO TBR + 2 713 #define DUI TO 714 #define TO_MASK (0x1f << 21) 715 { 0x1f, 21, NULL, NULL, 0 }, 716 717 /* The UI field in a D form instruction. */ 718 #define UI TO + 1 719 { 0xffff, 0, NULL, NULL, 0 }, 720 721 #define UISIGNOPT UI + 1 722 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT }, 723 724 /* The IMM field in an SE_IM5 instruction. */ 725 #define UI5 UISIGNOPT + 1 726 { 0x1f, 4, NULL, NULL, 0 }, 727 728 /* The OIMM field in an SE_OIM5 instruction. */ 729 #define OIMM5 UI5 + 1 730 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, 731 732 /* The UI7 field in an SE_LI instruction. */ 733 #define UI7 OIMM5 + 1 734 { 0x7f, 4, NULL, NULL, 0 }, 735 736 /* The VA field in a VA, VX or VXR form instruction. */ 737 #define VA UI7 + 1 738 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, 739 740 /* The VB field in a VA, VX or VXR form instruction. */ 741 #define VB VA + 1 742 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, 743 744 /* The VC field in a VA form instruction. */ 745 #define VC VB + 1 746 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, 747 748 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 749 #define VD VC + 1 750 #define VS VD 751 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, 752 753 /* The SIMM field in a VX form instruction, and TE in Z form. */ 754 #define SIMM VD + 1 755 #define TE SIMM 756 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, 757 758 /* The UIMM field in a VX form instruction. */ 759 #define UIMM SIMM + 1 760 #define DCTL UIMM 761 { 0x1f, 16, NULL, NULL, 0 }, 762 763 /* The 3-bit UIMM field in a VX form instruction. */ 764 #define UIMM3 UIMM + 1 765 { 0x7, 16, NULL, NULL, 0 }, 766 767 /* The 6-bit UIM field in a X form instruction. */ 768 #define UIM6 UIMM3 + 1 769 { 0x3f, 16, NULL, NULL, 0 }, 770 771 /* The SIX field in a VX form instruction. */ 772 #define SIX UIM6 + 1 773 { 0xf, 11, NULL, NULL, 0 }, 774 775 /* The PS field in a VX form instruction. */ 776 #define PS SIX + 1 777 { 0x1, 9, NULL, NULL, 0 }, 778 779 /* The SHB field in a VA form instruction. */ 780 #define SHB PS + 1 781 { 0xf, 6, NULL, NULL, 0 }, 782 783 /* The other UIMM field in a half word EVX form instruction. */ 784 #define EVUIMM_2 SHB + 1 785 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, 786 787 /* The other UIMM field in a word EVX form instruction. */ 788 #define EVUIMM_4 EVUIMM_2 + 1 789 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, 790 791 /* The other UIMM field in a double EVX form instruction. */ 792 #define EVUIMM_8 EVUIMM_4 + 1 793 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, 794 795 /* The WS or DRM field in an X form instruction. */ 796 #define WS EVUIMM_8 + 1 797 #define DRM WS 798 { 0x7, 11, NULL, NULL, 0 }, 799 800 /* PowerPC paired singles extensions. */ 801 /* W bit in the pair singles instructions for x type instructions. */ 802 #define PSWM WS + 1 803 /* The BO16 field in a BD8 form instruction. */ 804 #define BO16 PSWM 805 { 0x1, 10, 0, 0, 0 }, 806 807 /* IDX bits for quantization in the pair singles instructions. */ 808 #define PSQ PSWM + 1 809 { 0x7, 12, 0, 0, 0 }, 810 811 /* IDX bits for quantization in the pair singles x-type instructions. */ 812 #define PSQM PSQ + 1 813 { 0x7, 7, 0, 0, 0 }, 814 815 /* Smaller D field for quantization in the pair singles instructions. */ 816 #define PSD PSQM + 1 817 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 818 819 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */ 820 #define A_L PSD + 1 821 #define W A_L 822 #define X_R A_L 823 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 824 825 /* The RMC or CY field in a Z23 form instruction. */ 826 #define RMC A_L + 1 827 #define CY RMC 828 { 0x3, 9, NULL, NULL, 0 }, 829 830 #define R RMC + 1 831 { 0x1, 16, NULL, NULL, 0 }, 832 833 #define RIC R + 1 834 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL }, 835 836 #define PRS RIC + 1 837 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, 838 839 #define SP PRS + 1 840 { 0x3, 19, NULL, NULL, 0 }, 841 842 #define S SP + 1 843 { 0x1, 20, NULL, NULL, 0 }, 844 845 /* The S field in a XL form instruction. */ 846 #define SXL S + 1 847 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, 848 /* If the SXL operand is ommitted, use the value 1. */ 849 { -1, 1, NULL, NULL, 0}, 850 851 /* SH field starting at bit position 16. */ 852 #define SH16 SXL + 2 853 /* The DCM and DGM fields in a Z form instruction. */ 854 #define DCM SH16 855 #define DGM DCM 856 { 0x3f, 10, NULL, NULL, 0 }, 857 858 /* The EH field in larx instruction. */ 859 #define EH SH16 + 1 860 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, 861 862 /* The L field in an mtfsf or XFL form instruction. */ 863 /* The A field in a HTM X form instruction. */ 864 #define XFL_L EH + 1 865 #define HTM_A XFL_L 866 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, 867 868 /* Xilinx APU related masks and macros */ 869 #define FCRT XFL_L + 1 870 #define FCRT_MASK (0x1f << 21) 871 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, 872 873 /* Xilinx FSL related masks and macros */ 874 #define FSL FCRT + 1 875 #define FSL_MASK (0x1f << 11) 876 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, 877 878 /* Xilinx UDI related masks and macros */ 879 #define URT FSL + 1 880 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, 881 882 #define URA URT + 1 883 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, 884 885 #define URB URA + 1 886 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, 887 888 #define URC URB + 1 889 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, 890 891 /* The VLESIMM field in a D form instruction. */ 892 #define VLESIMM URC + 1 893 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, 894 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 895 896 /* The VLENSIMM field in a D form instruction. */ 897 #define VLENSIMM VLESIMM + 1 898 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, 899 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 900 901 /* The VLEUIMM field in a D form instruction. */ 902 #define VLEUIMM VLENSIMM + 1 903 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, 904 905 /* The VLEUIMML field in a D form instruction. */ 906 #define VLEUIMML VLEUIMM + 1 907 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, 908 909 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ 910 #define XS6 VLEUIMML + 1 911 #define XT6 XS6 912 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, 913 914 /* The XT and XS fields in an DQ form VSX instruction. This is split. */ 915 #define XSQ6 XT6 + 1 916 #define XTQ6 XSQ6 917 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, 918 919 /* The XA field in an XX3 form instruction. This is split. */ 920 #define XA6 XTQ6 + 1 921 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, 922 923 /* The XB field in an XX2 or XX3 form instruction. This is split. */ 924 #define XB6 XA6 + 1 925 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, 926 927 /* The XB field in an XX3 form instruction when it must be the same as 928 the XA field in the instruction. This is used in extended mnemonics 929 like xvmovdp. This is split. */ 930 #define XB6S XB6 + 1 931 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, 932 933 /* The XC field in an XX4 form instruction. This is split. */ 934 #define XC6 XB6S + 1 935 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, 936 937 /* The DM or SHW field in an XX3 form instruction. */ 938 #define DM XC6 + 1 939 #define SHW DM 940 { 0x3, 8, NULL, NULL, 0 }, 941 942 /* The DM field in an extended mnemonic XX3 form instruction. */ 943 #define DMEX DM + 1 944 { 0x3, 8, insert_dm, extract_dm, 0 }, 945 946 /* The UIM field in an XX2 form instruction. */ 947 #define UIM DMEX + 1 948 /* The 2-bit UIMM field in a VX form instruction. */ 949 #define UIMM2 UIM 950 /* The 2-bit L field in a darn instruction. */ 951 #define LRAND UIM 952 { 0x3, 16, NULL, NULL, 0 }, 953 954 #define ERAT_T UIM + 1 955 { 0x7, 21, NULL, NULL, 0 }, 956 957 #define IH ERAT_T + 1 958 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 959 960 /* The 8-bit IMM8 field in a XX1 form instruction. */ 961 #define IMM8 IH + 1 962 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT }, 963 }; 964 965 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) 966 / sizeof (powerpc_operands[0])); 967 968 /* The functions used to insert and extract complicated operands. */ 969 970 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ 971 972 static unsigned long 973 insert_arx (unsigned long insn, 974 long value, 975 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 976 const char **errmsg ATTRIBUTE_UNUSED) 977 { 978 if (value >= 8 && value < 24) 979 return insn | ((value - 8) & 0xf); 980 else 981 { 982 *errmsg = _("invalid register"); 983 return 0; 984 } 985 } 986 987 static long 988 extract_arx (unsigned long insn, 989 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 990 int *invalid ATTRIBUTE_UNUSED) 991 { 992 return (insn & 0xf) + 8; 993 } 994 995 static unsigned long 996 insert_ary (unsigned long insn, 997 long value, 998 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 999 const char **errmsg ATTRIBUTE_UNUSED) 1000 { 1001 if (value >= 8 && value < 24) 1002 return insn | (((value - 8) & 0xf) << 4); 1003 else 1004 { 1005 *errmsg = _("invalid register"); 1006 return 0; 1007 } 1008 } 1009 1010 static long 1011 extract_ary (unsigned long insn, 1012 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1013 int *invalid ATTRIBUTE_UNUSED) 1014 { 1015 return ((insn >> 4) & 0xf) + 8; 1016 } 1017 1018 static unsigned long 1019 insert_rx (unsigned long insn, 1020 long value, 1021 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1022 const char **errmsg) 1023 { 1024 if (value >= 0 && value < 8) 1025 return insn | value; 1026 else if (value >= 24 && value <= 31) 1027 return insn | (value - 16); 1028 else 1029 { 1030 *errmsg = _("invalid register"); 1031 return 0; 1032 } 1033 } 1034 1035 static long 1036 extract_rx (unsigned long insn, 1037 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1038 int *invalid ATTRIBUTE_UNUSED) 1039 { 1040 int value = insn & 0xf; 1041 if (value >= 0 && value < 8) 1042 return value; 1043 else 1044 return value + 16; 1045 } 1046 1047 static unsigned long 1048 insert_ry (unsigned long insn, 1049 long value, 1050 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1051 const char **errmsg) 1052 { 1053 if (value >= 0 && value < 8) 1054 return insn | (value << 4); 1055 else if (value >= 24 && value <= 31) 1056 return insn | ((value - 16) << 4); 1057 else 1058 { 1059 *errmsg = _("invalid register"); 1060 return 0; 1061 } 1062 } 1063 1064 static long 1065 extract_ry (unsigned long insn, 1066 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1067 int *invalid ATTRIBUTE_UNUSED) 1068 { 1069 int value = (insn >> 4) & 0xf; 1070 if (value >= 0 && value < 8) 1071 return value; 1072 else 1073 return value + 16; 1074 } 1075 1076 /* The BA field in an XL form instruction when it must be the same as 1077 the BT field in the same instruction. This operand is marked FAKE. 1078 The insertion function just copies the BT field into the BA field, 1079 and the extraction function just checks that the fields are the 1080 same. */ 1081 1082 static unsigned long 1083 insert_bat (unsigned long insn, 1084 long value ATTRIBUTE_UNUSED, 1085 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1086 const char **errmsg ATTRIBUTE_UNUSED) 1087 { 1088 return insn | (((insn >> 21) & 0x1f) << 16); 1089 } 1090 1091 static long 1092 extract_bat (unsigned long insn, 1093 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1094 int *invalid) 1095 { 1096 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 1097 *invalid = 1; 1098 return 0; 1099 } 1100 1101 /* The BB field in an XL form instruction when it must be the same as 1102 the BA field in the same instruction. This operand is marked FAKE. 1103 The insertion function just copies the BA field into the BB field, 1104 and the extraction function just checks that the fields are the 1105 same. */ 1106 1107 static unsigned long 1108 insert_bba (unsigned long insn, 1109 long value ATTRIBUTE_UNUSED, 1110 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1111 const char **errmsg ATTRIBUTE_UNUSED) 1112 { 1113 return insn | (((insn >> 16) & 0x1f) << 11); 1114 } 1115 1116 static long 1117 extract_bba (unsigned long insn, 1118 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1119 int *invalid) 1120 { 1121 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 1122 *invalid = 1; 1123 return 0; 1124 } 1125 1126 /* The BD field in a B form instruction when the - modifier is used. 1127 This modifier means that the branch is not expected to be taken. 1128 For chips built to versions of the architecture prior to version 2 1129 (ie. not Power4 compatible), we set the y bit of the BO field to 1 1130 if the offset is negative. When extracting, we require that the y 1131 bit be 1 and that the offset be positive, since if the y bit is 0 1132 we just want to print the normal form of the instruction. 1133 Power4 compatible targets use two bits, "a", and "t", instead of 1134 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, 1135 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 1136 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 1137 for branch on CTR. We only handle the taken/not-taken hint here. 1138 Note that we don't relax the conditions tested here when 1139 disassembling with -Many because insns using extract_bdm and 1140 extract_bdp always occur in pairs. One or the other will always 1141 be valid. */ 1142 1143 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) 1144 1145 static unsigned long 1146 insert_bdm (unsigned long insn, 1147 long value, 1148 ppc_cpu_t dialect, 1149 const char **errmsg ATTRIBUTE_UNUSED) 1150 { 1151 if ((dialect & ISA_V2) == 0) 1152 { 1153 if ((value & 0x8000) != 0) 1154 insn |= 1 << 21; 1155 } 1156 else 1157 { 1158 if ((insn & (0x14 << 21)) == (0x04 << 21)) 1159 insn |= 0x02 << 21; 1160 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 1161 insn |= 0x08 << 21; 1162 } 1163 return insn | (value & 0xfffc); 1164 } 1165 1166 static long 1167 extract_bdm (unsigned long insn, 1168 ppc_cpu_t dialect, 1169 int *invalid) 1170 { 1171 if ((dialect & ISA_V2) == 0) 1172 { 1173 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) 1174 *invalid = 1; 1175 } 1176 else 1177 { 1178 if ((insn & (0x17 << 21)) != (0x06 << 21) 1179 && (insn & (0x1d << 21)) != (0x18 << 21)) 1180 *invalid = 1; 1181 } 1182 1183 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1184 } 1185 1186 /* The BD field in a B form instruction when the + modifier is used. 1187 This is like BDM, above, except that the branch is expected to be 1188 taken. */ 1189 1190 static unsigned long 1191 insert_bdp (unsigned long insn, 1192 long value, 1193 ppc_cpu_t dialect, 1194 const char **errmsg ATTRIBUTE_UNUSED) 1195 { 1196 if ((dialect & ISA_V2) == 0) 1197 { 1198 if ((value & 0x8000) == 0) 1199 insn |= 1 << 21; 1200 } 1201 else 1202 { 1203 if ((insn & (0x14 << 21)) == (0x04 << 21)) 1204 insn |= 0x03 << 21; 1205 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 1206 insn |= 0x09 << 21; 1207 } 1208 return insn | (value & 0xfffc); 1209 } 1210 1211 static long 1212 extract_bdp (unsigned long insn, 1213 ppc_cpu_t dialect, 1214 int *invalid) 1215 { 1216 if ((dialect & ISA_V2) == 0) 1217 { 1218 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) 1219 *invalid = 1; 1220 } 1221 else 1222 { 1223 if ((insn & (0x17 << 21)) != (0x07 << 21) 1224 && (insn & (0x1d << 21)) != (0x19 << 21)) 1225 *invalid = 1; 1226 } 1227 1228 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1229 } 1230 1231 static inline int 1232 valid_bo_pre_v2 (long value) 1233 { 1234 /* Certain encodings have bits that are required to be zero. 1235 These are (z must be zero, y may be anything): 1236 0000y 1237 0001y 1238 001zy 1239 0100y 1240 0101y 1241 011zy 1242 1z00y 1243 1z01y 1244 1z1zz 1245 */ 1246 if ((value & 0x14) == 0) 1247 return 1; 1248 else if ((value & 0x14) == 0x4) 1249 return (value & 0x2) == 0; 1250 else if ((value & 0x14) == 0x10) 1251 return (value & 0x8) == 0; 1252 else 1253 return value == 0x14; 1254 } 1255 1256 static inline int 1257 valid_bo_post_v2 (long value) 1258 { 1259 /* Certain encodings have bits that are required to be zero. 1260 These are (z must be zero, a & t may be anything): 1261 0000z 1262 0001z 1263 001at 1264 0100z 1265 0101z 1266 011at 1267 1a00t 1268 1a01t 1269 1z1zz 1270 */ 1271 if ((value & 0x14) == 0) 1272 return (value & 0x1) == 0; 1273 else if ((value & 0x14) == 0x14) 1274 return value == 0x14; 1275 else 1276 return 1; 1277 } 1278 1279 /* Check for legal values of a BO field. */ 1280 1281 static int 1282 valid_bo (long value, ppc_cpu_t dialect, int extract) 1283 { 1284 int valid_y = valid_bo_pre_v2 (value); 1285 int valid_at = valid_bo_post_v2 (value); 1286 1287 /* When disassembling with -Many, accept either encoding on the 1288 second pass through opcodes. */ 1289 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY) 1290 return valid_y || valid_at; 1291 if ((dialect & ISA_V2) == 0) 1292 return valid_y; 1293 else 1294 return valid_at; 1295 } 1296 1297 /* The BO field in a B form instruction. Warn about attempts to set 1298 the field to an illegal value. */ 1299 1300 static unsigned long 1301 insert_bo (unsigned long insn, 1302 long value, 1303 ppc_cpu_t dialect, 1304 const char **errmsg) 1305 { 1306 if (!valid_bo (value, dialect, 0)) 1307 *errmsg = _("invalid conditional option"); 1308 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) 1309 *errmsg = _("invalid counter access"); 1310 return insn | ((value & 0x1f) << 21); 1311 } 1312 1313 static long 1314 extract_bo (unsigned long insn, 1315 ppc_cpu_t dialect, 1316 int *invalid) 1317 { 1318 long value; 1319 1320 value = (insn >> 21) & 0x1f; 1321 if (!valid_bo (value, dialect, 1)) 1322 *invalid = 1; 1323 return value; 1324 } 1325 1326 /* The BO field in a B form instruction when the + or - modifier is 1327 used. This is like the BO field, but it must be even. When 1328 extracting it, we force it to be even. */ 1329 1330 static unsigned long 1331 insert_boe (unsigned long insn, 1332 long value, 1333 ppc_cpu_t dialect, 1334 const char **errmsg) 1335 { 1336 if (!valid_bo (value, dialect, 0)) 1337 *errmsg = _("invalid conditional option"); 1338 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) 1339 *errmsg = _("invalid counter access"); 1340 else if ((value & 1) != 0) 1341 *errmsg = _("attempt to set y bit when using + or - modifier"); 1342 1343 return insn | ((value & 0x1f) << 21); 1344 } 1345 1346 static long 1347 extract_boe (unsigned long insn, 1348 ppc_cpu_t dialect, 1349 int *invalid) 1350 { 1351 long value; 1352 1353 value = (insn >> 21) & 0x1f; 1354 if (!valid_bo (value, dialect, 1)) 1355 *invalid = 1; 1356 return value & 0x1e; 1357 } 1358 1359 /* The DCMX field in a X form instruction when the field is split 1360 into separate DC, DM and DX fields. */ 1361 1362 static unsigned long 1363 insert_dcmxs (unsigned long insn, 1364 long value, 1365 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1366 const char **errmsg ATTRIBUTE_UNUSED) 1367 { 1368 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40); 1369 } 1370 1371 static long 1372 extract_dcmxs (unsigned long insn, 1373 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1374 int *invalid ATTRIBUTE_UNUSED) 1375 { 1376 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); 1377 } 1378 1379 /* The D field in a DX form instruction when the field is split 1380 into separate D0, D1 and D2 fields. */ 1381 1382 static unsigned long 1383 insert_dxd (unsigned long insn, 1384 long value, 1385 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1386 const char **errmsg ATTRIBUTE_UNUSED) 1387 { 1388 return insn | (value & 0xffc1) | ((value & 0x3e) << 15); 1389 } 1390 1391 static long 1392 extract_dxd (unsigned long insn, 1393 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1394 int *invalid ATTRIBUTE_UNUSED) 1395 { 1396 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e); 1397 return (dxd ^ 0x8000) - 0x8000; 1398 } 1399 1400 static unsigned long 1401 insert_dxdn (unsigned long insn, 1402 long value, 1403 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1404 const char **errmsg ATTRIBUTE_UNUSED) 1405 { 1406 return insert_dxd (insn, -value, dialect, errmsg); 1407 } 1408 1409 static long 1410 extract_dxdn (unsigned long insn, 1411 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1412 int *invalid ATTRIBUTE_UNUSED) 1413 { 1414 return -extract_dxd (insn, dialect, invalid); 1415 } 1416 1417 /* FXM mask in mfcr and mtcrf instructions. */ 1418 1419 static unsigned long 1420 insert_fxm (unsigned long insn, 1421 long value, 1422 ppc_cpu_t dialect, 1423 const char **errmsg) 1424 { 1425 /* If we're handling the mfocrf and mtocrf insns ensure that exactly 1426 one bit of the mask field is set. */ 1427 if ((insn & (1 << 20)) != 0) 1428 { 1429 if (value == 0 || (value & -value) != value) 1430 { 1431 *errmsg = _("invalid mask field"); 1432 value = 0; 1433 } 1434 } 1435 1436 /* If only one bit of the FXM field is set, we can use the new form 1437 of the instruction, which is faster. Unlike the Power4 branch hint 1438 encoding, this is not backward compatible. Do not generate the 1439 new form unless -mpower4 has been given, or -many and the two 1440 operand form of mfcr was used. */ 1441 else if (value > 0 1442 && (value & -value) == value 1443 && ((dialect & PPC_OPCODE_POWER4) != 0 1444 || ((dialect & PPC_OPCODE_ANY) != 0 1445 && (insn & (0x3ff << 1)) == 19 << 1))) 1446 insn |= 1 << 20; 1447 1448 /* Any other value on mfcr is an error. */ 1449 else if ((insn & (0x3ff << 1)) == 19 << 1) 1450 { 1451 /* A value of -1 means we used the one operand form of 1452 mfcr which is valid. */ 1453 if (value != -1) 1454 *errmsg = _("invalid mfcr mask"); 1455 value = 0; 1456 } 1457 1458 return insn | ((value & 0xff) << 12); 1459 } 1460 1461 static long 1462 extract_fxm (unsigned long insn, 1463 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1464 int *invalid) 1465 { 1466 long mask = (insn >> 12) & 0xff; 1467 1468 /* Is this a Power4 insn? */ 1469 if ((insn & (1 << 20)) != 0) 1470 { 1471 /* Exactly one bit of MASK should be set. */ 1472 if (mask == 0 || (mask & -mask) != mask) 1473 *invalid = 1; 1474 } 1475 1476 /* Check that non-power4 form of mfcr has a zero MASK. */ 1477 else if ((insn & (0x3ff << 1)) == 19 << 1) 1478 { 1479 if (mask != 0) 1480 *invalid = 1; 1481 else 1482 mask = -1; 1483 } 1484 1485 return mask; 1486 } 1487 1488 /* The L field in an X form instruction which must have the value zero. */ 1489 1490 static unsigned long 1491 insert_l0 (unsigned long insn, 1492 long value, 1493 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1494 const char **errmsg) 1495 { 1496 if (value != 0) 1497 *errmsg = _("invalid operand constant"); 1498 return insn & ~(0x1 << 21); 1499 } 1500 1501 static long 1502 extract_l0 (unsigned long insn, 1503 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1504 int *invalid) 1505 { 1506 long value; 1507 1508 value = (insn >> 21) & 0x1; 1509 if (value != 0) 1510 *invalid = 1; 1511 return value; 1512 } 1513 1514 /* The L field in an X form instruction which must have the value one. */ 1515 1516 static unsigned long 1517 insert_l1 (unsigned long insn, 1518 long value, 1519 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1520 const char **errmsg) 1521 { 1522 if (value != 1) 1523 *errmsg = _("invalid operand constant"); 1524 return insn | (0x1 << 21); 1525 } 1526 1527 static long 1528 extract_l1 (unsigned long insn, 1529 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1530 int *invalid) 1531 { 1532 long value; 1533 1534 value = (insn >> 21) & 0x1; 1535 if (value != 1) 1536 *invalid = 1; 1537 return value; 1538 } 1539 1540 static unsigned long 1541 insert_li20 (unsigned long insn, 1542 long value, 1543 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1544 const char **errmsg ATTRIBUTE_UNUSED) 1545 { 1546 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff); 1547 } 1548 1549 static long 1550 extract_li20 (unsigned long insn, 1551 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1552 int *invalid ATTRIBUTE_UNUSED) 1553 { 1554 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000; 1555 1556 return ext 1557 | (((insn >> 11) & 0xf) << 16) 1558 | (((insn >> 17) & 0xf) << 12) 1559 | (((insn >> 16) & 0x1) << 11) 1560 | (insn & 0x7ff); 1561 } 1562 1563 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction. 1564 For SYNC, some L values are reserved: 1565 * Value 3 is reserved on newer server cpus. 1566 * Values 2 and 3 are reserved on all other cpus. */ 1567 1568 static unsigned long 1569 insert_ls (unsigned long insn, 1570 long value, 1571 ppc_cpu_t dialect, 1572 const char **errmsg) 1573 { 1574 /* For SYNC, some L values are illegal. */ 1575 if (((insn >> 1) & 0x3ff) == 598) 1576 { 1577 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; 1578 if (value > max_lvalue) 1579 { 1580 *errmsg = _("illegal L operand value"); 1581 return insn; 1582 } 1583 } 1584 1585 return insn | ((value & 0x3) << 21); 1586 } 1587 1588 /* The 4-bit E field in a sync instruction that accepts 2 operands. 1589 If ESYNC is non-zero, then the L field must be either 0 or 1 and 1590 the complement of ESYNC-bit2. */ 1591 1592 static unsigned long 1593 insert_esync (unsigned long insn, 1594 long value, 1595 ppc_cpu_t dialect, 1596 const char **errmsg) 1597 { 1598 unsigned long ls = (insn >> 21) & 0x03; 1599 1600 if (value == 0) 1601 { 1602 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1) 1603 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2)) 1604 *errmsg = _("illegal L operand value"); 1605 return insn; 1606 } 1607 1608 if ((ls & ~0x1) 1609 || (((value >> 1) & 0x1) ^ ls) == 0) 1610 *errmsg = _("incompatible L operand value"); 1611 1612 return insn | ((value & 0xf) << 16); 1613 } 1614 1615 /* The MB and ME fields in an M form instruction expressed as a single 1616 operand which is itself a bitmask. The extraction function always 1617 marks it as invalid, since we never want to recognize an 1618 instruction which uses a field of this type. */ 1619 1620 static unsigned long 1621 insert_mbe (unsigned long insn, 1622 long value, 1623 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1624 const char **errmsg) 1625 { 1626 unsigned long uval, mask; 1627 int mb, me, mx, count, last; 1628 1629 uval = value; 1630 1631 if (uval == 0) 1632 { 1633 *errmsg = _("illegal bitmask"); 1634 return insn; 1635 } 1636 1637 mb = 0; 1638 me = 32; 1639 if ((uval & 1) != 0) 1640 last = 1; 1641 else 1642 last = 0; 1643 count = 0; 1644 1645 /* mb: location of last 0->1 transition */ 1646 /* me: location of last 1->0 transition */ 1647 /* count: # transitions */ 1648 1649 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) 1650 { 1651 if ((uval & mask) && !last) 1652 { 1653 ++count; 1654 mb = mx; 1655 last = 1; 1656 } 1657 else if (!(uval & mask) && last) 1658 { 1659 ++count; 1660 me = mx; 1661 last = 0; 1662 } 1663 } 1664 if (me == 0) 1665 me = 32; 1666 1667 if (count != 2 && (count != 0 || ! last)) 1668 *errmsg = _("illegal bitmask"); 1669 1670 return insn | (mb << 6) | ((me - 1) << 1); 1671 } 1672 1673 static long 1674 extract_mbe (unsigned long insn, 1675 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1676 int *invalid) 1677 { 1678 long ret; 1679 int mb, me; 1680 int i; 1681 1682 *invalid = 1; 1683 1684 mb = (insn >> 6) & 0x1f; 1685 me = (insn >> 1) & 0x1f; 1686 if (mb < me + 1) 1687 { 1688 ret = 0; 1689 for (i = mb; i <= me; i++) 1690 ret |= 1L << (31 - i); 1691 } 1692 else if (mb == me + 1) 1693 ret = ~0; 1694 else /* (mb > me + 1) */ 1695 { 1696 ret = ~0; 1697 for (i = me + 1; i < mb; i++) 1698 ret &= ~(1L << (31 - i)); 1699 } 1700 return ret; 1701 } 1702 1703 /* The MB or ME field in an MD or MDS form instruction. The high bit 1704 is wrapped to the low end. */ 1705 1706 static unsigned long 1707 insert_mb6 (unsigned long insn, 1708 long value, 1709 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1710 const char **errmsg ATTRIBUTE_UNUSED) 1711 { 1712 return insn | ((value & 0x1f) << 6) | (value & 0x20); 1713 } 1714 1715 static long 1716 extract_mb6 (unsigned long insn, 1717 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1718 int *invalid ATTRIBUTE_UNUSED) 1719 { 1720 return ((insn >> 6) & 0x1f) | (insn & 0x20); 1721 } 1722 1723 /* The NB field in an X form instruction. The value 32 is stored as 1724 0. */ 1725 1726 static long 1727 extract_nb (unsigned long insn, 1728 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1729 int *invalid ATTRIBUTE_UNUSED) 1730 { 1731 long ret; 1732 1733 ret = (insn >> 11) & 0x1f; 1734 if (ret == 0) 1735 ret = 32; 1736 return ret; 1737 } 1738 1739 /* The NB field in an lswi instruction, which has special value 1740 restrictions. The value 32 is stored as 0. */ 1741 1742 static unsigned long 1743 insert_nbi (unsigned long insn, 1744 long value, 1745 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1746 const char **errmsg ATTRIBUTE_UNUSED) 1747 { 1748 long rtvalue = (insn & RT_MASK) >> 21; 1749 long ravalue = (insn & RA_MASK) >> 16; 1750 1751 if (value == 0) 1752 value = 32; 1753 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32 1754 : ravalue)) 1755 *errmsg = _("address register in load range"); 1756 return insn | ((value & 0x1f) << 11); 1757 } 1758 1759 /* The NSI field in a D form instruction. This is the same as the SI 1760 field, only negated. The extraction function always marks it as 1761 invalid, since we never want to recognize an instruction which uses 1762 a field of this type. */ 1763 1764 static unsigned long 1765 insert_nsi (unsigned long insn, 1766 long value, 1767 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1768 const char **errmsg ATTRIBUTE_UNUSED) 1769 { 1770 return insn | (-value & 0xffff); 1771 } 1772 1773 static long 1774 extract_nsi (unsigned long insn, 1775 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1776 int *invalid) 1777 { 1778 *invalid = 1; 1779 return -(((insn & 0xffff) ^ 0x8000) - 0x8000); 1780 } 1781 1782 /* The RA field in a D or X form instruction which is an updating 1783 load, which means that the RA field may not be zero and may not 1784 equal the RT field. */ 1785 1786 static unsigned long 1787 insert_ral (unsigned long insn, 1788 long value, 1789 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1790 const char **errmsg) 1791 { 1792 if (value == 0 1793 || (unsigned long) value == ((insn >> 21) & 0x1f)) 1794 *errmsg = "invalid register operand when updating"; 1795 return insn | ((value & 0x1f) << 16); 1796 } 1797 1798 /* The RA field in an lmw instruction, which has special value 1799 restrictions. */ 1800 1801 static unsigned long 1802 insert_ram (unsigned long insn, 1803 long value, 1804 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1805 const char **errmsg) 1806 { 1807 if ((unsigned long) value >= ((insn >> 21) & 0x1f)) 1808 *errmsg = _("index register in load range"); 1809 return insn | ((value & 0x1f) << 16); 1810 } 1811 1812 /* The RA field in the DQ form lq or an lswx instruction, which have special 1813 value restrictions. */ 1814 1815 static unsigned long 1816 insert_raq (unsigned long insn, 1817 long value, 1818 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1819 const char **errmsg) 1820 { 1821 long rtvalue = (insn & RT_MASK) >> 21; 1822 1823 if (value == rtvalue) 1824 *errmsg = _("source and target register operands must be different"); 1825 return insn | ((value & 0x1f) << 16); 1826 } 1827 1828 /* The RA field in a D or X form instruction which is an updating 1829 store or an updating floating point load, which means that the RA 1830 field may not be zero. */ 1831 1832 static unsigned long 1833 insert_ras (unsigned long insn, 1834 long value, 1835 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1836 const char **errmsg) 1837 { 1838 if (value == 0) 1839 *errmsg = _("invalid register operand when updating"); 1840 return insn | ((value & 0x1f) << 16); 1841 } 1842 1843 /* The RB field in an X form instruction when it must be the same as 1844 the RS field in the instruction. This is used for extended 1845 mnemonics like mr. This operand is marked FAKE. The insertion 1846 function just copies the BT field into the BA field, and the 1847 extraction function just checks that the fields are the same. */ 1848 1849 static unsigned long 1850 insert_rbs (unsigned long insn, 1851 long value ATTRIBUTE_UNUSED, 1852 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1853 const char **errmsg ATTRIBUTE_UNUSED) 1854 { 1855 return insn | (((insn >> 21) & 0x1f) << 11); 1856 } 1857 1858 static long 1859 extract_rbs (unsigned long insn, 1860 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1861 int *invalid) 1862 { 1863 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) 1864 *invalid = 1; 1865 return 0; 1866 } 1867 1868 /* The RB field in an lswx instruction, which has special value 1869 restrictions. */ 1870 1871 static unsigned long 1872 insert_rbx (unsigned long insn, 1873 long value, 1874 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1875 const char **errmsg) 1876 { 1877 long rtvalue = (insn & RT_MASK) >> 21; 1878 1879 if (value == rtvalue) 1880 *errmsg = _("source and target register operands must be different"); 1881 return insn | ((value & 0x1f) << 11); 1882 } 1883 1884 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */ 1885 static unsigned long 1886 insert_sci8 (unsigned long insn, 1887 long value, 1888 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1889 const char **errmsg) 1890 { 1891 unsigned int fill_scale = 0; 1892 unsigned long ui8 = value; 1893 1894 if ((ui8 & 0xffffff00) == 0) 1895 ; 1896 else if ((ui8 & 0xffffff00) == 0xffffff00) 1897 fill_scale = 0x400; 1898 else if ((ui8 & 0xffff00ff) == 0) 1899 { 1900 fill_scale = 1 << 8; 1901 ui8 >>= 8; 1902 } 1903 else if ((ui8 & 0xffff00ff) == 0xffff00ff) 1904 { 1905 fill_scale = 0x400 | (1 << 8); 1906 ui8 >>= 8; 1907 } 1908 else if ((ui8 & 0xff00ffff) == 0) 1909 { 1910 fill_scale = 2 << 8; 1911 ui8 >>= 16; 1912 } 1913 else if ((ui8 & 0xff00ffff) == 0xff00ffff) 1914 { 1915 fill_scale = 0x400 | (2 << 8); 1916 ui8 >>= 16; 1917 } 1918 else if ((ui8 & 0x00ffffff) == 0) 1919 { 1920 fill_scale = 3 << 8; 1921 ui8 >>= 24; 1922 } 1923 else if ((ui8 & 0x00ffffff) == 0x00ffffff) 1924 { 1925 fill_scale = 0x400 | (3 << 8); 1926 ui8 >>= 24; 1927 } 1928 else 1929 { 1930 *errmsg = _("illegal immediate value"); 1931 ui8 = 0; 1932 } 1933 1934 return insn | fill_scale | (ui8 & 0xff); 1935 } 1936 1937 static long 1938 extract_sci8 (unsigned long insn, 1939 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1940 int *invalid ATTRIBUTE_UNUSED) 1941 { 1942 int fill = insn & 0x400; 1943 int scale_factor = (insn & 0x300) >> 5; 1944 long value = (insn & 0xff) << scale_factor; 1945 1946 if (fill != 0) 1947 value |= ~((long) 0xff << scale_factor); 1948 return value; 1949 } 1950 1951 static unsigned long 1952 insert_sci8n (unsigned long insn, 1953 long value, 1954 ppc_cpu_t dialect, 1955 const char **errmsg) 1956 { 1957 return insert_sci8 (insn, -value, dialect, errmsg); 1958 } 1959 1960 static long 1961 extract_sci8n (unsigned long insn, 1962 ppc_cpu_t dialect, 1963 int *invalid) 1964 { 1965 return -extract_sci8 (insn, dialect, invalid); 1966 } 1967 1968 static unsigned long 1969 insert_sd4h (unsigned long insn, 1970 long value, 1971 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1972 const char **errmsg ATTRIBUTE_UNUSED) 1973 { 1974 return insn | ((value & 0x1e) << 7); 1975 } 1976 1977 static long 1978 extract_sd4h (unsigned long insn, 1979 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1980 int *invalid ATTRIBUTE_UNUSED) 1981 { 1982 return ((insn >> 8) & 0xf) << 1; 1983 } 1984 1985 static unsigned long 1986 insert_sd4w (unsigned long insn, 1987 long value, 1988 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1989 const char **errmsg ATTRIBUTE_UNUSED) 1990 { 1991 return insn | ((value & 0x3c) << 6); 1992 } 1993 1994 static long 1995 extract_sd4w (unsigned long insn, 1996 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1997 int *invalid ATTRIBUTE_UNUSED) 1998 { 1999 return ((insn >> 8) & 0xf) << 2; 2000 } 2001 2002 static unsigned long 2003 insert_oimm (unsigned long insn, 2004 long value, 2005 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2006 const char **errmsg ATTRIBUTE_UNUSED) 2007 { 2008 return insn | (((value - 1) & 0x1f) << 4); 2009 } 2010 2011 static long 2012 extract_oimm (unsigned long insn, 2013 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2014 int *invalid ATTRIBUTE_UNUSED) 2015 { 2016 return ((insn >> 4) & 0x1f) + 1; 2017 } 2018 2019 /* The SH field in an MD form instruction. This is split. */ 2020 2021 static unsigned long 2022 insert_sh6 (unsigned long insn, 2023 long value, 2024 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2025 const char **errmsg ATTRIBUTE_UNUSED) 2026 { 2027 /* SH6 operand in the rldixor instructions. */ 2028 if (PPC_OP (insn) == 4) 2029 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5); 2030 else 2031 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 2032 } 2033 2034 static long 2035 extract_sh6 (unsigned long insn, 2036 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2037 int *invalid ATTRIBUTE_UNUSED) 2038 { 2039 /* SH6 operand in the rldixor instructions. */ 2040 if (PPC_OP (insn) == 4) 2041 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20); 2042 else 2043 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 2044 } 2045 2046 /* The SPR field in an XFX form instruction. This is flipped--the 2047 lower 5 bits are stored in the upper 5 and vice- versa. */ 2048 2049 static unsigned long 2050 insert_spr (unsigned long insn, 2051 long value, 2052 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2053 const char **errmsg ATTRIBUTE_UNUSED) 2054 { 2055 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 2056 } 2057 2058 static long 2059 extract_spr (unsigned long insn, 2060 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2061 int *invalid ATTRIBUTE_UNUSED) 2062 { 2063 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 2064 } 2065 2066 /* Some dialects have 8 SPRG registers instead of the standard 4. */ 2067 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) 2068 2069 static unsigned long 2070 insert_sprg (unsigned long insn, 2071 long value, 2072 ppc_cpu_t dialect, 2073 const char **errmsg) 2074 { 2075 if (value > 7 2076 || (value > 3 && (dialect & ALLOW8_SPRG) == 0)) 2077 *errmsg = _("invalid sprg number"); 2078 2079 /* If this is mfsprg4..7 then use spr 260..263 which can be read in 2080 user mode. Anything else must use spr 272..279. */ 2081 if (value <= 3 || (insn & 0x100) != 0) 2082 value |= 0x10; 2083 2084 return insn | ((value & 0x17) << 16); 2085 } 2086 2087 static long 2088 extract_sprg (unsigned long insn, 2089 ppc_cpu_t dialect, 2090 int *invalid) 2091 { 2092 unsigned long val = (insn >> 16) & 0x1f; 2093 2094 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 2095 If not BOOKE, 405 or VLE, then both use only 272..275. */ 2096 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) 2097 || (val - 0x10 > 7 && (insn & 0x100) != 0) 2098 || val <= 3 2099 || (val & 8) != 0) 2100 *invalid = 1; 2101 return val & 7; 2102 } 2103 2104 /* The TBR field in an XFX instruction. This is just like SPR, but it 2105 is optional. */ 2106 2107 static unsigned long 2108 insert_tbr (unsigned long insn, 2109 long value, 2110 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2111 const char **errmsg) 2112 { 2113 if (value != 268 && value != 269) 2114 *errmsg = _("invalid tbr number"); 2115 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 2116 } 2117 2118 static long 2119 extract_tbr (unsigned long insn, 2120 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2121 int *invalid) 2122 { 2123 long ret; 2124 2125 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 2126 if (ret != 268 && ret != 269) 2127 *invalid = 1; 2128 return ret; 2129 } 2130 2131 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ 2132 2133 static unsigned long 2134 insert_xt6 (unsigned long insn, 2135 long value, 2136 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2137 const char **errmsg ATTRIBUTE_UNUSED) 2138 { 2139 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); 2140 } 2141 2142 static long 2143 extract_xt6 (unsigned long insn, 2144 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2145 int *invalid ATTRIBUTE_UNUSED) 2146 { 2147 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); 2148 } 2149 2150 /* The XT and XS fields in an DQ form VSX instruction. This is split. */ 2151 static unsigned long 2152 insert_xtq6 (unsigned long insn, 2153 long value, 2154 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2155 const char **errmsg ATTRIBUTE_UNUSED) 2156 { 2157 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2); 2158 } 2159 2160 static long 2161 extract_xtq6 (unsigned long insn, 2162 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2163 int *invalid ATTRIBUTE_UNUSED) 2164 { 2165 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f); 2166 } 2167 2168 /* The XA field in an XX3 form instruction. This is split. */ 2169 2170 static unsigned long 2171 insert_xa6 (unsigned long insn, 2172 long value, 2173 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2174 const char **errmsg ATTRIBUTE_UNUSED) 2175 { 2176 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); 2177 } 2178 2179 static long 2180 extract_xa6 (unsigned long insn, 2181 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2182 int *invalid ATTRIBUTE_UNUSED) 2183 { 2184 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); 2185 } 2186 2187 /* The XB field in an XX3 form instruction. This is split. */ 2188 2189 static unsigned long 2190 insert_xb6 (unsigned long insn, 2191 long value, 2192 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2193 const char **errmsg ATTRIBUTE_UNUSED) 2194 { 2195 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 2196 } 2197 2198 static long 2199 extract_xb6 (unsigned long insn, 2200 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2201 int *invalid ATTRIBUTE_UNUSED) 2202 { 2203 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); 2204 } 2205 2206 /* The XB field in an XX3 form instruction when it must be the same as 2207 the XA field in the instruction. This is used for extended 2208 mnemonics like xvmovdp. This operand is marked FAKE. The insertion 2209 function just copies the XA field into the XB field, and the 2210 extraction function just checks that the fields are the same. */ 2211 2212 static unsigned long 2213 insert_xb6s (unsigned long insn, 2214 long value ATTRIBUTE_UNUSED, 2215 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2216 const char **errmsg ATTRIBUTE_UNUSED) 2217 { 2218 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1); 2219 } 2220 2221 static long 2222 extract_xb6s (unsigned long insn, 2223 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2224 int *invalid) 2225 { 2226 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 2227 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1))) 2228 *invalid = 1; 2229 return 0; 2230 } 2231 2232 /* The XC field in an XX4 form instruction. This is split. */ 2233 2234 static unsigned long 2235 insert_xc6 (unsigned long insn, 2236 long value, 2237 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2238 const char **errmsg ATTRIBUTE_UNUSED) 2239 { 2240 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); 2241 } 2242 2243 static long 2244 extract_xc6 (unsigned long insn, 2245 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2246 int *invalid ATTRIBUTE_UNUSED) 2247 { 2248 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); 2249 } 2250 2251 static unsigned long 2252 insert_dm (unsigned long insn, 2253 long value, 2254 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2255 const char **errmsg) 2256 { 2257 if (value != 0 && value != 1) 2258 *errmsg = _("invalid constant"); 2259 return insn | (((value) ? 3 : 0) << 8); 2260 } 2261 2262 static long 2263 extract_dm (unsigned long insn, 2264 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2265 int *invalid) 2266 { 2267 long value; 2268 2269 value = (insn >> 8) & 3; 2270 if (value != 0 && value != 3) 2271 *invalid = 1; 2272 return (value) ? 1 : 0; 2273 } 2274 2275 /* The VLESIMM field in an I16A form instruction. This is split. */ 2276 2277 static unsigned long 2278 insert_vlesi (unsigned long insn, 2279 long value, 2280 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2281 const char **errmsg ATTRIBUTE_UNUSED) 2282 { 2283 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 2284 } 2285 2286 static long 2287 extract_vlesi (unsigned long insn, 2288 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2289 int *invalid ATTRIBUTE_UNUSED) 2290 { 2291 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); 2292 value = (value ^ 0x8000) - 0x8000; 2293 return value; 2294 } 2295 2296 static unsigned long 2297 insert_vlensi (unsigned long insn, 2298 long value, 2299 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2300 const char **errmsg ATTRIBUTE_UNUSED) 2301 { 2302 value = -value; 2303 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 2304 } 2305 static long 2306 extract_vlensi (unsigned long insn, 2307 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2308 int *invalid ATTRIBUTE_UNUSED) 2309 { 2310 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); 2311 value = (value ^ 0x8000) - 0x8000; 2312 /* Don't use for disassembly. */ 2313 *invalid = 1; 2314 return -value; 2315 } 2316 2317 /* The VLEUIMM field in an I16A form instruction. This is split. */ 2318 2319 static unsigned long 2320 insert_vleui (unsigned long insn, 2321 long value, 2322 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2323 const char **errmsg ATTRIBUTE_UNUSED) 2324 { 2325 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 2326 } 2327 2328 static long 2329 extract_vleui (unsigned long insn, 2330 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2331 int *invalid ATTRIBUTE_UNUSED) 2332 { 2333 return ((insn >> 10) & 0xf800) | (insn & 0x7ff); 2334 } 2335 2336 /* The VLEUIMML field in an I16L form instruction. This is split. */ 2337 2338 static unsigned long 2339 insert_vleil (unsigned long insn, 2340 long value, 2341 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2342 const char **errmsg ATTRIBUTE_UNUSED) 2343 { 2344 return insn | ((value & 0xf800) << 5) | (value & 0x7ff); 2345 } 2346 2347 static long 2348 extract_vleil (unsigned long insn, 2349 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2350 int *invalid ATTRIBUTE_UNUSED) 2351 { 2352 return ((insn >> 5) & 0xf800) | (insn & 0x7ff); 2353 } 2354 2355 2356 /* Macros used to form opcodes. */ 2358 2359 /* The main opcode. */ 2360 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) 2361 #define OP_MASK OP (0x3f) 2362 2363 /* The main opcode combined with a trap code in the TO field of a D 2364 form instruction. Used for extended mnemonics for the trap 2365 instructions. */ 2366 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) 2367 #define OPTO_MASK (OP_MASK | TO_MASK) 2368 2369 /* The main opcode combined with a comparison size bit in the L field 2370 of a D form or X form instruction. Used for extended mnemonics for 2371 the comparison instructions. */ 2372 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) 2373 #define OPL_MASK OPL (0x3f,1) 2374 2375 /* The main opcode combined with an update code in D form instruction. 2376 Used for extended mnemonics for VLE memory instructions. */ 2377 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8)) 2378 #define OPVUP_MASK OPVUP (0x3f, 0xff) 2379 2380 /* An A form instruction. */ 2381 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) 2382 #define A_MASK A (0x3f, 0x1f, 1) 2383 2384 /* An A_MASK with the FRB field fixed. */ 2385 #define AFRB_MASK (A_MASK | FRB_MASK) 2386 2387 /* An A_MASK with the FRC field fixed. */ 2388 #define AFRC_MASK (A_MASK | FRC_MASK) 2389 2390 /* An A_MASK with the FRA and FRC fields fixed. */ 2391 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 2392 2393 /* An AFRAFRC_MASK, but with L bit clear. */ 2394 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) 2395 2396 /* A B form instruction. */ 2397 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) 2398 #define B_MASK B (0x3f, 1, 1) 2399 2400 /* A BD8 form instruction. This is a 16-bit instruction. */ 2401 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8)) 2402 #define BD8_MASK BD8 (0x3f, 1, 1) 2403 2404 /* Another BD8 form instruction. This is a 16-bit instruction. */ 2405 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11) 2406 #define BD8IO_MASK BD8IO (0x1f) 2407 2408 /* A BD8 form instruction for simplified mnemonics. */ 2409 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) 2410 /* A mask that excludes BO32 and BI32. */ 2411 #define EBD8IO1_MASK 0xf800 2412 /* A mask that includes BO32 and excludes BI32. */ 2413 #define EBD8IO2_MASK 0xfc00 2414 /* A mask that include BO32 AND BI32. */ 2415 #define EBD8IO3_MASK 0xff00 2416 2417 /* A BD15 form instruction. */ 2418 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1)) 2419 #define BD15_MASK BD15 (0x3f, 0xf, 1) 2420 2421 /* A BD15 form instruction for extended conditional branch mnemonics. */ 2422 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1) 2423 #define EBD15_MASK 0xfff00001 2424 2425 /* A BD15 form instruction for extended conditional branch mnemonics with BI. */ 2426 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \ 2427 | (((aa) & 0xf) << 22) \ 2428 | (((bo) & 0x3) << 20) \ 2429 | (((bi) & 0x3) << 16) \ 2430 | ((lk) & 1) 2431 #define EBD15BI_MASK 0xfff30001 2432 2433 /* A BD24 form instruction. */ 2434 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1)) 2435 #define BD24_MASK BD24 (0x3f, 1, 1) 2436 2437 /* A B form instruction setting the BO field. */ 2438 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 2439 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 2440 2441 /* A BBO_MASK with the y bit of the BO field removed. This permits 2442 matching a conditional branch regardless of the setting of the y 2443 bit. Similarly for the 'at' bits used for power4 branch hints. */ 2444 #define Y_MASK (((unsigned long) 1) << 21) 2445 #define AT1_MASK (((unsigned long) 3) << 21) 2446 #define AT2_MASK (((unsigned long) 9) << 21) 2447 #define BBOY_MASK (BBO_MASK &~ Y_MASK) 2448 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) 2449 2450 /* A B form instruction setting the BO field and the condition bits of 2451 the BI field. */ 2452 #define BBOCB(op, bo, cb, aa, lk) \ 2453 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) 2454 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) 2455 2456 /* A BBOCB_MASK with the y bit of the BO field removed. */ 2457 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) 2458 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) 2459 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) 2460 2461 /* A BBOYCB_MASK in which the BI field is fixed. */ 2462 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 2463 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) 2464 2465 /* A VLE C form instruction. */ 2466 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1)) 2467 #define C_LK_MASK C_LK(0x7fff, 1) 2468 #define C(x) ((((unsigned long)(x)) & 0xffff)) 2469 #define C_MASK C(0xffff) 2470 2471 /* An Context form instruction. */ 2472 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) 2473 #define CTX_MASK CTX(0x3f, 0x7) 2474 2475 /* An User Context form instruction. */ 2476 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 2477 #define UCTX_MASK UCTX(0x3f, 0x1f) 2478 2479 /* The main opcode mask with the RA field clear. */ 2480 #define DRA_MASK (OP_MASK | RA_MASK) 2481 2482 /* A DQ form VSX instruction. */ 2483 #define DQX(op, xop) (OP (op) | ((xop) & 0x7)) 2484 #define DQX_MASK DQX (0x3f, 7) 2485 2486 /* A DS form instruction. */ 2487 #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 2488 #define DS_MASK DSO (0x3f, 3) 2489 2490 /* An DX form instruction. */ 2491 #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 2492 #define DX_MASK DX (0x3f, 0x1f) 2493 /* An DX form instruction with the D bits specified. */ 2494 #define NODX_MASK (DX_MASK | 0x1fffc1) 2495 2496 /* An EVSEL form instruction. */ 2497 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) 2498 #define EVSEL_MASK EVSEL(0x3f, 0xff) 2499 2500 /* An IA16 form instruction. */ 2501 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) 2502 #define IA16_MASK IA16(0x3f, 0x1f) 2503 2504 /* An I16A form instruction. */ 2505 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) 2506 #define I16A_MASK I16A(0x3f, 0x1f) 2507 2508 /* An I16L form instruction. */ 2509 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) 2510 #define I16L_MASK I16L(0x3f, 0x1f) 2511 2512 /* An IM7 form instruction. */ 2513 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11) 2514 #define IM7_MASK IM7(0x1f) 2515 2516 /* An M form instruction. */ 2517 #define M(op, rc) (OP (op) | ((rc) & 1)) 2518 #define M_MASK M (0x3f, 1) 2519 2520 /* An LI20 form instruction. */ 2521 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15) 2522 #define LI20_MASK LI20(0x3f, 0x1) 2523 2524 /* An M form instruction with the ME field specified. */ 2525 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) 2526 2527 /* An M_MASK with the MB and ME fields fixed. */ 2528 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) 2529 2530 /* An M_MASK with the SH and ME fields fixed. */ 2531 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) 2532 2533 /* An MD form instruction. */ 2534 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) 2535 #define MD_MASK MD (0x3f, 0x7, 1) 2536 2537 /* An MD_MASK with the MB field fixed. */ 2538 #define MDMB_MASK (MD_MASK | MB6_MASK) 2539 2540 /* An MD_MASK with the SH field fixed. */ 2541 #define MDSH_MASK (MD_MASK | SH6_MASK) 2542 2543 /* An MDS form instruction. */ 2544 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) 2545 #define MDS_MASK MDS (0x3f, 0xf, 1) 2546 2547 /* An MDS_MASK with the MB field fixed. */ 2548 #define MDSMB_MASK (MDS_MASK | MB6_MASK) 2549 2550 /* An SC form instruction. */ 2551 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) 2552 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) 2553 2554 /* An SCI8 form instruction. */ 2555 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11)) 2556 #define SCI8_MASK SCI8(0x3f, 0x1f) 2557 2558 /* An SCI8 form instruction. */ 2559 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23)) 2560 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) 2561 2562 /* An SD4 form instruction. This is a 16-bit instruction. */ 2563 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12) 2564 #define SD4_MASK SD4(0xf) 2565 2566 /* An SE_IM5 form instruction. This is a 16-bit instruction. */ 2567 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9)) 2568 #define SE_IM5_MASK SE_IM5(0x3f, 1) 2569 2570 /* An SE_R form instruction. This is a 16-bit instruction. */ 2571 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4)) 2572 #define SE_R_MASK SE_R(0x3f, 0x3f) 2573 2574 /* An SE_RR form instruction. This is a 16-bit instruction. */ 2575 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8)) 2576 #define SE_RR_MASK SE_RR(0x3f, 3) 2577 2578 /* A VX form instruction. */ 2579 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) 2580 2581 /* The mask for an VX form instruction. */ 2582 #define VX_MASK VX(0x3f, 0x7ff) 2583 2584 /* A VX_MASK with the VA field fixed. */ 2585 #define VXVA_MASK (VX_MASK | (0x1f << 16)) 2586 2587 /* A VX_MASK with the VB field fixed. */ 2588 #define VXVB_MASK (VX_MASK | (0x1f << 11)) 2589 2590 /* A VX_MASK with the VA and VB fields fixed. */ 2591 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11)) 2592 2593 /* A VX_MASK with the VD and VA fields fixed. */ 2594 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16)) 2595 2596 /* A VX_MASK with a UIMM4 field. */ 2597 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20)) 2598 2599 /* A VX_MASK with a UIMM3 field. */ 2600 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19)) 2601 2602 /* A VX_MASK with a UIMM2 field. */ 2603 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) 2604 2605 /* A VX_MASK with a PS field. */ 2606 #define VXPS_MASK (VX_MASK & ~(0x1 << 9)) 2607 2608 /* A VX_MASK with the VA field fixed with a PS field. */ 2609 #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9)) 2610 2611 /* A VA form instruction. */ 2612 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) 2613 2614 /* The mask for an VA form instruction. */ 2615 #define VXA_MASK VXA(0x3f, 0x3f) 2616 2617 /* A VXA_MASK with a SHB field. */ 2618 #define VXASHB_MASK (VXA_MASK | (1 << 10)) 2619 2620 /* A VXR form instruction. */ 2621 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) 2622 2623 /* The mask for a VXR form instruction. */ 2624 #define VXR_MASK VXR(0x3f, 0x3ff, 1) 2625 2626 /* A VX form instruction with a VA tertiary opcode. */ 2627 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) 2628 2629 #define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 2630 #define VXASH_MASK VXASH (0x3f, 0x1f) 2631 2632 /* An X form instruction. */ 2633 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 2634 2635 /* A X form instruction for Quad-Precision FP Instructions. */ 2636 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16)) 2637 2638 /* An EX form instruction. */ 2639 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) 2640 2641 /* The mask for an EX form instruction. */ 2642 #define EX_MASK EX (0x3f, 0x7ff) 2643 2644 /* An XX2 form instruction. */ 2645 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2)) 2646 2647 /* A XX2 form instruction with the VA bits specified. */ 2648 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16)) 2649 2650 /* An XX3 form instruction. */ 2651 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3)) 2652 2653 /* An XX3 form instruction with the RC bit specified. */ 2654 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3)) 2655 2656 /* An XX4 form instruction. */ 2657 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4)) 2658 2659 /* A Z form instruction. */ 2660 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) 2661 2662 /* An X form instruction with the RC bit specified. */ 2663 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 2664 2665 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */ 2666 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) 2667 2668 /* An X form instruction with the RA bits specified as two ops. */ 2669 #define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16) 2670 2671 /* A Z form instruction with the RC bit specified. */ 2672 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) 2673 2674 /* The mask for an X form instruction. */ 2675 #define X_MASK XRC (0x3f, 0x3ff, 1) 2676 2677 /* The mask for an X form instruction with the BF bits specified. */ 2678 #define XBF_MASK (X_MASK | (3 << 21)) 2679 2680 /* An X form wait instruction with everything filled in except the WC field. */ 2681 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) 2682 2683 /* The mask for an XX1 form instruction. */ 2684 #define XX1_MASK X (0x3f, 0x3ff) 2685 2686 /* An XX1_MASK with the RB field fixed. */ 2687 #define XX1RB_MASK (XX1_MASK | RB_MASK) 2688 2689 /* The mask for an XX2 form instruction. */ 2690 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) 2691 2692 /* The mask for an XX2 form instruction with the UIM bits specified. */ 2693 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) 2694 2695 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */ 2696 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20)) 2697 2698 /* The mask for an XX2 form instruction with the BF bits specified. */ 2699 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) 2700 2701 /* The mask for an XX2 form instruction with the BF and DCMX bits specified. */ 2702 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1) 2703 2704 /* The mask for an XX2 form instruction with a split DCMX bits specified. */ 2705 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee) 2706 2707 /* The mask for an XX3 form instruction. */ 2708 #define XX3_MASK XX3 (0x3f, 0xff) 2709 2710 /* The mask for an XX3 form instruction with the BF bits specified. */ 2711 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) 2712 2713 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */ 2714 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) 2715 #define XX3SHW_MASK XX3DM_MASK 2716 2717 /* The mask for an XX4 form instruction. */ 2718 #define XX4_MASK XX4 (0x3f, 0x3) 2719 2720 /* An X form wait instruction with everything filled in except the WC field. */ 2721 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) 2722 2723 /* The mask for an XMMF form instruction. */ 2724 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1)) 2725 2726 /* The mask for a Z form instruction. */ 2727 #define Z_MASK ZRC (0x3f, 0x1ff, 1) 2728 #define Z2_MASK ZRC (0x3f, 0xff, 1) 2729 2730 /* An X_MASK with the RA/VA field fixed. */ 2731 #define XRA_MASK (X_MASK | RA_MASK) 2732 #define XVA_MASK XRA_MASK 2733 2734 /* An XRA_MASK with the A_L/W field clear. */ 2735 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) 2736 #define XRLA_MASK XWRA_MASK 2737 2738 /* An X_MASK with the RB field fixed. */ 2739 #define XRB_MASK (X_MASK | RB_MASK) 2740 2741 /* An X_MASK with the RT field fixed. */ 2742 #define XRT_MASK (X_MASK | RT_MASK) 2743 2744 /* An XRT_MASK mask with the L bits clear. */ 2745 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) 2746 2747 /* An X_MASK with the RA and RB fields fixed. */ 2748 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 2749 2750 /* An XBF_MASK with the RA and RB fields fixed. */ 2751 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK) 2752 2753 /* An XRARB_MASK, but with the L bit clear. */ 2754 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) 2755 2756 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */ 2757 #define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16)) 2758 2759 /* An X_MASK with the RT and RA fields fixed. */ 2760 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 2761 2762 /* An X_MASK with the RT and RB fields fixed. */ 2763 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) 2764 2765 /* An XRTRA_MASK, but with L bit clear. */ 2766 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) 2767 2768 /* An X_MASK with the RT, RA and RB fields fixed. */ 2769 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) 2770 2771 /* An XRTRARB_MASK, but with L bit clear. */ 2772 #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21)) 2773 2774 /* An XRTRARB_MASK, but with A bit clear. */ 2775 #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25)) 2776 2777 /* An XRTRARB_MASK, but with BF bits clear. */ 2778 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23)) 2779 2780 /* An X form instruction with the L bit specified. */ 2781 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) 2782 2783 /* An X form instruction with the L bits specified. */ 2784 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) 2785 2786 /* An X form instruction with the L bit and RC bit specified. */ 2787 #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21)) 2788 2789 /* An X form instruction with RT fields specified */ 2790 #define XRT(op, xop, rt) (X ((op), (xop)) \ 2791 | ((((unsigned long)(rt)) & 0x1f) << 21)) 2792 2793 /* An X form instruction with RT and RA fields specified */ 2794 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \ 2795 | ((((unsigned long)(rt)) & 0x1f) << 21) \ 2796 | ((((unsigned long)(ra)) & 0x1f) << 16)) 2797 2798 /* The mask for an X form comparison instruction. */ 2799 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) 2800 2801 /* The mask for an X form comparison instruction with the L field 2802 fixed. */ 2803 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) 2804 2805 /* An X form trap instruction with the TO field specified. */ 2806 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) 2807 #define XTO_MASK (X_MASK | TO_MASK) 2808 2809 /* An X form tlb instruction with the SH field specified. */ 2810 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) 2811 #define XTLB_MASK (X_MASK | SH_MASK) 2812 2813 /* An X form sync instruction. */ 2814 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) 2815 2816 /* An X form sync instruction with everything filled in except the LS field. */ 2817 #define XSYNC_MASK (0xff9fffff) 2818 2819 /* An X form sync instruction with everything filled in except the L and E fields. */ 2820 #define XSYNCLE_MASK (0xff90ffff) 2821 2822 /* An X_MASK, but with the EH bit clear. */ 2823 #define XEH_MASK (X_MASK & ~((unsigned long )1)) 2824 2825 /* An X form AltiVec dss instruction. */ 2826 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) 2827 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) 2828 2829 /* An XFL form instruction. */ 2830 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 2831 #define XFL_MASK XFL (0x3f, 0x3ff, 1) 2832 2833 /* An X form isel instruction. */ 2834 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 2835 #define XISEL_MASK XISEL(0x3f, 0x1f) 2836 2837 /* An XL form instruction with the LK field set to 0. */ 2838 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 2839 2840 /* An XL form instruction which uses the LK field. */ 2841 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) 2842 2843 /* The mask for an XL form instruction. */ 2844 #define XL_MASK XLLK (0x3f, 0x3ff, 1) 2845 2846 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */ 2847 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11)) 2848 2849 /* An XL form instruction which explicitly sets the BO field. */ 2850 #define XLO(op, bo, xop, lk) \ 2851 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 2852 #define XLO_MASK (XL_MASK | BO_MASK) 2853 2854 /* An XL form instruction which explicitly sets the y bit of the BO 2855 field. */ 2856 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) 2857 #define XLYLK_MASK (XL_MASK | Y_MASK) 2858 2859 /* An XL form instruction which sets the BO field and the condition 2860 bits of the BI field. */ 2861 #define XLOCB(op, bo, cb, xop, lk) \ 2862 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) 2863 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) 2864 2865 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ 2866 #define XLBB_MASK (XL_MASK | BB_MASK) 2867 #define XLYBB_MASK (XLYLK_MASK | BB_MASK) 2868 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) 2869 2870 /* A mask for branch instructions using the BH field. */ 2871 #define XLBH_MASK (XL_MASK | (0x1c << 11)) 2872 2873 /* An XL_MASK with the BO and BB fields fixed. */ 2874 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) 2875 2876 /* An XL_MASK with the BO, BI and BB fields fixed. */ 2877 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) 2878 2879 /* An X form mbar instruction with MO field. */ 2880 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21)) 2881 2882 /* An XO form instruction. */ 2883 #define XO(op, xop, oe, rc) \ 2884 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) 2885 #define XO_MASK XO (0x3f, 0x1ff, 1, 1) 2886 2887 /* An XO_MASK with the RB field fixed. */ 2888 #define XORB_MASK (XO_MASK | RB_MASK) 2889 2890 /* An XOPS form instruction for paired singles. */ 2891 #define XOPS(op, xop, rc) \ 2892 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 2893 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1) 2894 2895 2896 /* An XS form instruction. */ 2897 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) 2898 #define XS_MASK XS (0x3f, 0x1ff, 1) 2899 2900 /* A mask for the FXM version of an XFX form instruction. */ 2901 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) 2902 2903 /* An XFX form instruction with the FXM field filled in. */ 2904 #define XFXM(op, xop, fxm, p4) \ 2905 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \ 2906 | ((unsigned long)(p4) << 20)) 2907 2908 /* An XFX form instruction with the SPR field filled in. */ 2909 #define XSPR(op, xop, spr) \ 2910 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) 2911 #define XSPR_MASK (X_MASK | SPR_MASK) 2912 2913 /* An XFX form instruction with the SPR field filled in except for the 2914 SPRBAT field. */ 2915 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) 2916 2917 /* An XFX form instruction with the SPR field filled in except for the 2918 SPRG field. */ 2919 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) 2920 2921 /* An X form instruction with everything filled in except the E field. */ 2922 #define XE_MASK (0xffff7fff) 2923 2924 /* An X form user context instruction. */ 2925 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 2926 #define XUC_MASK XUC(0x3f, 0x1f) 2927 2928 /* An XW form instruction. */ 2929 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1)) 2930 /* The mask for a G form instruction. rc not supported at present. */ 2931 #define XW_MASK XW (0x3f, 0x3f, 0) 2932 2933 /* An APU form instruction. */ 2934 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1)) 2935 2936 /* The mask for an APU form instruction. */ 2937 #define APU_MASK APU (0x3f, 0x3ff, 1) 2938 #define APU_RT_MASK (APU_MASK | RT_MASK) 2939 #define APU_RA_MASK (APU_MASK | RA_MASK) 2940 2941 /* The BO encodings used in extended conditional branch mnemonics. */ 2942 #define BODNZF (0x0) 2943 #define BODNZFP (0x1) 2944 #define BODZF (0x2) 2945 #define BODZFP (0x3) 2946 #define BODNZT (0x8) 2947 #define BODNZTP (0x9) 2948 #define BODZT (0xa) 2949 #define BODZTP (0xb) 2950 2951 #define BOF (0x4) 2952 #define BOFP (0x5) 2953 #define BOFM4 (0x6) 2954 #define BOFP4 (0x7) 2955 #define BOT (0xc) 2956 #define BOTP (0xd) 2957 #define BOTM4 (0xe) 2958 #define BOTP4 (0xf) 2959 2960 #define BODNZ (0x10) 2961 #define BODNZP (0x11) 2962 #define BODZ (0x12) 2963 #define BODZP (0x13) 2964 #define BODNZM4 (0x18) 2965 #define BODNZP4 (0x19) 2966 #define BODZM4 (0x1a) 2967 #define BODZP4 (0x1b) 2968 2969 #define BOU (0x14) 2970 2971 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */ 2972 #define BO16F (0x0) 2973 #define BO16T (0x1) 2974 2975 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */ 2976 #define BO32F (0x0) 2977 #define BO32T (0x1) 2978 #define BO32DNZ (0x2) 2979 #define BO32DZ (0x3) 2980 2981 /* The BI condition bit encodings used in extended conditional branch 2982 mnemonics. */ 2983 #define CBLT (0) 2984 #define CBGT (1) 2985 #define CBEQ (2) 2986 #define CBSO (3) 2987 2988 /* The TO encodings used in extended trap mnemonics. */ 2989 #define TOLGT (0x1) 2990 #define TOLLT (0x2) 2991 #define TOEQ (0x4) 2992 #define TOLGE (0x5) 2993 #define TOLNL (0x5) 2994 #define TOLLE (0x6) 2995 #define TOLNG (0x6) 2996 #define TOGT (0x8) 2997 #define TOGE (0xc) 2998 #define TONL (0xc) 2999 #define TOLT (0x10) 3000 #define TOLE (0x14) 3001 #define TONG (0x14) 3002 #define TONE (0x18) 3003 #define TOU (0x1f) 3004 3005 /* Smaller names for the flags so each entry in the opcodes table will 3007 fit on a single line. */ 3008 #undef PPC 3009 #define PPC PPC_OPCODE_PPC 3010 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 3011 #define POWER4 PPC_OPCODE_POWER4 3012 #define POWER5 PPC_OPCODE_POWER5 3013 #define POWER6 PPC_OPCODE_POWER6 3014 #define POWER7 PPC_OPCODE_POWER7 3015 #define POWER8 PPC_OPCODE_POWER8 3016 #define POWER9 PPC_OPCODE_POWER9 3017 #define CELL PPC_OPCODE_CELL 3018 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE 3019 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ 3020 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) 3021 #define PPC403 PPC_OPCODE_403 3022 #define PPC405 PPC_OPCODE_405 3023 #define PPC440 PPC_OPCODE_440 3024 #define PPC464 PPC440 3025 #define PPC476 PPC_OPCODE_476 3026 #define PPC750 PPC_OPCODE_750 3027 #define PPC7450 PPC_OPCODE_7450 3028 #define PPC860 PPC_OPCODE_860 3029 #define PPCPS PPC_OPCODE_PPCPS 3030 #define PPCVEC PPC_OPCODE_ALTIVEC 3031 #define PPCVEC2 PPC_OPCODE_ALTIVEC2 3032 #define PPCVEC3 PPC_OPCODE_ALTIVEC2 3033 #define PPCVSX PPC_OPCODE_VSX 3034 #define PPCVSX2 PPC_OPCODE_VSX 3035 #define PPCVSX3 PPC_OPCODE_VSX3 3036 #define POWER PPC_OPCODE_POWER 3037 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 3038 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON 3039 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON 3040 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON 3041 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 3042 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON 3043 #define MFDEC1 PPC_OPCODE_POWER 3044 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN 3045 #define BOOKE PPC_OPCODE_BOOKE 3046 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS 3047 #define PPCE300 PPC_OPCODE_E300 3048 #define PPCSPE PPC_OPCODE_SPE 3049 #define PPCISEL PPC_OPCODE_ISEL 3050 #define PPCEFS PPC_OPCODE_EFS 3051 #define PPCBRLK PPC_OPCODE_BRLOCK 3052 #define PPCPMR PPC_OPCODE_PMR 3053 #define PPCTMR PPC_OPCODE_TMR 3054 #define PPCCHLK PPC_OPCODE_CACHELCK 3055 #define PPCRFMCI PPC_OPCODE_RFMCI 3056 #define E500MC PPC_OPCODE_E500MC 3057 #define PPCA2 PPC_OPCODE_A2 3058 #define TITAN PPC_OPCODE_TITAN 3059 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN 3060 #define E500 PPC_OPCODE_E500 3061 #define E6500 PPC_OPCODE_E6500 3062 #define PPCVLE PPC_OPCODE_VLE 3063 #define PPCHTM PPC_OPCODE_HTM 3064 /* The list of embedded processors that use the embedded operand ordering 3065 for the 3 operand dcbt and dcbtst instructions. */ 3066 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ 3067 | PPC_OPCODE_A2) 3068 3069 3070 3071 /* The opcode table. 3073 3074 The format of the opcode table is: 3075 3076 NAME OPCODE MASK FLAGS ANTI {OPERANDS} 3077 3078 NAME is the name of the instruction. 3079 OPCODE is the instruction opcode. 3080 MASK is the opcode mask; this is used to tell the disassembler 3081 which bits in the actual opcode must match OPCODE. 3082 FLAGS are flags indicating which processors support the instruction. 3083 ANTI indicates which processors don't support the instruction. 3084 OPERANDS is the list of operands. 3085 3086 The disassembler reads the table in order and prints the first 3087 instruction which matches, so this table is sorted to put more 3088 specific instructions before more general instructions. 3089 3090 This table must be sorted by major opcode. Please try to keep it 3091 vaguely sorted within major opcode too, except of course where 3092 constrained otherwise by disassembler operation. */ 3093 3094 const struct powerpc_opcode powerpc_opcodes[] = { 3095 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, 3096 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3097 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3098 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3099 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3100 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3101 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3102 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3103 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3104 {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3105 {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3106 {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3107 {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3108 {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3109 {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3110 {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3111 {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}}, 3112 3113 {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3114 {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3115 {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3116 {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3117 {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3118 {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3119 {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3120 {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3121 {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3122 {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3123 {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3124 {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3125 {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3126 {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3127 {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3128 {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3129 {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3130 {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3131 {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3132 {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3133 {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3134 {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3135 {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3136 {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3137 {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3138 {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3139 {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3140 {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3141 {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3142 {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3143 {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}}, 3144 {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}}, 3145 3146 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3147 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3148 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, 3149 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3150 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3151 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3152 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3153 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3154 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3155 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, 3156 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3157 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, 3158 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3159 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3160 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3161 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3162 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3163 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3164 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3165 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3166 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3167 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3168 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3169 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3170 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3171 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3172 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3173 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3174 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3175 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3176 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3177 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3178 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, 3179 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3180 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3181 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3182 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3183 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3184 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3185 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3186 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3187 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3188 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3189 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3190 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3191 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3192 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3193 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}}, 3194 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3195 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3196 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, 3197 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3198 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, 3199 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3200 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 3201 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3202 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 3203 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3204 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3205 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 3206 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3207 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3208 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3209 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3210 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3211 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3212 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, 3213 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3214 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3215 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3216 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3217 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3218 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3219 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3220 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3221 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3222 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3223 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3224 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3225 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3226 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3227 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3228 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3229 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3230 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, 3231 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3232 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, 3233 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3234 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3235 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3236 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3237 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3238 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3239 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3240 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3241 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3242 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3243 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3244 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3245 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3246 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3247 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3248 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3249 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3250 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3251 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3252 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3253 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3254 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3255 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3256 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3257 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3258 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3259 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3260 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3261 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3262 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3263 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3264 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3265 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3266 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3267 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3268 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3269 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3270 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3271 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3272 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3273 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3274 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3275 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3276 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3277 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3278 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3279 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3280 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3281 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3282 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3283 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3284 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3285 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3286 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3287 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3288 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3289 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3290 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3291 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3292 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3293 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3294 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3295 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3296 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3297 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3298 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3299 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3300 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3301 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3302 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3303 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3304 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3305 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3306 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3307 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3308 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3309 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3310 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3311 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3312 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3313 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3314 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3315 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3316 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3317 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3318 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3319 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3320 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, 3321 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, 3322 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3323 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3324 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, 3325 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3326 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, 3327 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, 3328 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3329 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, 3330 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3331 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, 3332 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, 3333 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3334 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, 3335 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, 3336 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}}, 3337 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3338 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, 3339 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, 3340 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3341 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3342 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3343 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3344 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3345 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3346 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3347 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, 3348 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3349 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3350 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, 3351 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3352 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3353 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3354 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3355 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3356 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3357 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3358 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3359 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3360 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3361 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3362 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 3363 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3364 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 3365 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3366 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3367 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3368 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3369 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3370 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3371 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3372 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3373 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3374 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3375 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3376 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3377 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3378 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3379 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3380 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3381 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3382 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}}, 3383 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3384 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3385 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3386 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, 3387 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3388 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3389 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3390 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3391 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3392 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, 3393 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3394 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, 3395 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, 3396 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3397 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3398 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3399 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3400 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3401 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3402 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, 3403 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3404 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3405 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3406 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3407 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, 3408 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, 3409 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, 3410 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, 3411 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, 3412 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, 3413 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, 3414 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, 3415 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, 3416 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3417 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, 3418 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3419 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3420 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3421 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3422 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3423 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3424 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3425 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, 3426 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3427 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, 3428 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, 3429 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3430 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3431 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3432 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3433 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3434 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3435 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3436 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3437 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3438 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3439 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, 3440 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, 3441 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, 3442 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, 3443 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, 3444 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, 3445 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, 3446 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, 3447 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, 3448 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, 3449 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3450 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, 3451 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3452 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3453 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3454 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3455 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3456 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}}, 3457 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}}, 3458 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, 3459 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, 3460 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, 3461 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3462 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3463 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}}, 3464 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}}, 3465 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3466 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3467 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3468 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, 3469 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}}, 3470 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}}, 3471 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, 3472 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, 3473 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, 3474 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, 3475 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, 3476 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, 3477 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}}, 3478 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3479 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}}, 3480 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3481 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3482 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3483 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3484 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3485 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3486 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3487 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3488 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3489 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3490 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3491 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3492 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3493 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3494 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3495 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 3496 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3497 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3498 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3499 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 3500 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3501 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 3502 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3503 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3504 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 3505 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3506 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3507 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3508 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3509 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3510 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3511 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3512 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3513 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3514 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3515 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3516 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3517 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3518 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3519 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3520 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3521 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3522 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3523 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3524 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3525 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3526 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3527 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3528 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3529 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3530 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3531 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3532 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3533 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3534 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3535 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3536 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3537 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3538 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3539 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3540 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3541 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 3542 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3543 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3544 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3545 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3546 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3547 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3548 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3549 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3550 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3551 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3552 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3553 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3554 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3555 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3556 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3557 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 3558 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3559 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3560 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3561 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3562 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3563 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3564 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3565 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3566 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3567 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3568 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3569 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3570 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3571 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3572 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3573 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3574 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, 3575 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3576 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3577 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3578 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3579 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3580 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3581 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3582 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3583 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3584 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3585 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3586 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3587 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3588 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3589 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3590 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3591 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3592 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3593 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3594 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3595 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3596 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3597 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3598 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3599 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3600 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3601 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3602 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3603 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3604 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3605 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3606 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, 3607 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3608 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3609 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3610 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3611 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3612 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3613 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3614 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3615 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3616 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3617 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3618 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3619 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3620 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3621 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3622 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3623 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3624 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3625 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3626 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3627 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3628 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3629 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3630 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3631 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3632 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3633 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3634 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3635 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3636 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3637 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3638 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3639 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3640 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3641 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3642 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3643 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3644 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3645 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3646 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}}, 3647 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3648 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3649 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3650 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3651 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3652 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3653 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3654 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3655 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3656 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3657 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3658 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, 3659 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 3660 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, 3661 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, 3662 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, 3663 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, 3664 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3665 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3666 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3667 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3668 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3669 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3670 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3671 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3672 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, 3673 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, 3674 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, 3675 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, 3676 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3677 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3678 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3679 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3680 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3681 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3682 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3683 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3684 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3685 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 3686 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3687 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3688 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3689 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3690 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}}, 3691 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3692 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3693 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3694 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3695 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3696 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3697 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3698 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3699 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3700 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3701 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3702 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3703 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3704 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3705 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3706 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3707 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3708 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3709 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3710 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3711 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3712 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3713 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3714 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3715 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3716 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3717 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3718 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3719 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3720 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3721 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3722 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3723 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3724 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3725 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3726 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3727 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3728 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3729 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3730 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3731 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3732 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3733 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3734 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3735 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3736 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3737 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3738 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3739 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3740 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3741 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 3742 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 3743 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3744 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 3745 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 3746 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 3747 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3748 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3749 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3750 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3751 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3752 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3753 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3754 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3755 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3756 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3757 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3758 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3759 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3760 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3761 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3762 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3763 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3764 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3765 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3766 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3767 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3768 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3769 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3770 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3771 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 3772 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3773 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3774 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3775 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3776 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3777 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, 3778 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3779 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3780 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3781 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3782 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3783 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3784 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3785 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3786 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3787 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3788 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3789 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3790 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3791 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, 3792 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, 3793 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3794 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3795 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3796 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3797 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3798 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3799 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3800 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3801 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3802 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3803 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3804 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3805 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3806 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3807 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}}, 3808 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3809 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3810 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3811 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3812 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3813 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3814 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}}, 3815 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3816 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3817 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3818 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3819 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3820 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3821 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3822 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, 3823 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3824 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3825 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3826 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3827 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3828 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3829 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3830 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, 3831 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3832 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3833 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3834 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3835 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3836 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3837 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3838 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3839 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3840 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3841 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3842 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3843 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3844 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3845 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3846 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3847 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3848 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3849 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3850 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3851 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3852 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3853 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3854 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3855 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3856 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3857 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3858 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3859 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3860 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3861 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3862 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3863 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3864 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3865 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3866 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3867 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3868 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3869 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3870 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3871 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3872 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3873 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3874 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3875 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3876 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3877 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3878 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3879 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3880 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3881 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, 3882 3883 {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 3884 {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 3885 3886 {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 3887 {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 3888 3889 {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}}, 3890 3891 {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}}, 3892 {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}}, 3893 {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L, RA, UISIGNOPT}}, 3894 {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}}, 3895 3896 {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}}, 3897 {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}}, 3898 {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L, RA, SI}}, 3899 {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}}, 3900 3901 {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 3902 {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 3903 {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, 3904 3905 {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 3906 {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 3907 {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, 3908 3909 {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}}, 3910 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}}, 3911 {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}}, 3912 {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 3913 {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}}, 3914 {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, 3915 3916 {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}}, 3917 {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}}, 3918 {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, 3919 {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, 3920 {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}}, 3921 3922 {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 3923 {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 3924 {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, 3925 {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, 3926 {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 3927 {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 3928 {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, 3929 {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, 3930 {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 3931 {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 3932 {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, 3933 {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, 3934 {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 3935 {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 3936 {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, 3937 {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, 3938 {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 3939 {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 3940 {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}}, 3941 {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 3942 {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 3943 {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}}, 3944 {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 3945 {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 3946 {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}}, 3947 {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 3948 {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 3949 {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}}, 3950 3951 {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 3952 {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 3953 {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 3954 {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 3955 {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 3956 {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 3957 {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 3958 {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 3959 {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 3960 {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 3961 {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 3962 {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 3963 {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 3964 {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 3965 {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 3966 {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 3967 {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 3968 {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 3969 {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 3970 {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 3971 {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 3972 {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 3973 {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 3974 {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 3975 {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 3976 {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 3977 {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 3978 {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 3979 {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 3980 {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 3981 {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 3982 {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 3983 {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 3984 {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 3985 {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 3986 {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 3987 {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 3988 {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 3989 {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 3990 {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 3991 {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 3992 {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 3993 {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 3994 {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 3995 {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 3996 {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 3997 {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 3998 {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 3999 {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4000 {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4001 {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4002 {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4003 {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4004 {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4005 {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4006 {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4007 {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4008 {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4009 {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4010 {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4011 {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4012 {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4013 {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4014 {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4015 {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4016 {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4017 {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4018 {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4019 {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4020 {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4021 {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4022 {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4023 {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4024 {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4025 {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4026 {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4027 {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4028 {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4029 {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4030 {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4031 {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4032 {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4033 {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4034 {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4035 4036 {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4037 {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4038 {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4039 {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4040 {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4041 {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4042 {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4043 {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4044 {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4045 {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4046 {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4047 {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4048 {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4049 {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4050 {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4051 {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4052 {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4053 {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4054 {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4055 {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4056 {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4057 {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4058 {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4059 {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4060 {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4061 {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4062 {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4063 {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4064 {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4065 {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4066 {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4067 {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4068 {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4069 {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4070 {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4071 {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4072 {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4073 {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4074 {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4075 {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4076 {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4077 {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4078 {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4079 {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4080 {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4081 {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4082 {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4083 {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4084 {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4085 {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4086 {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4087 {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4088 {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4089 {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4090 {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4091 {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4092 {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4093 {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4094 {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4095 {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4096 4097 {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4098 {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4099 {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4100 {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4101 {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4102 {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4103 {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4104 {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4105 {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4106 {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4107 {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4108 {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4109 {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4110 {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4111 {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4112 {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4113 {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4114 {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4115 {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4116 {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4117 {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4118 {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4119 {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4120 {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4121 4122 {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4123 {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4124 {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4125 {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4126 {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4127 {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4128 {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4129 {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4130 {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4131 {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4132 {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4133 {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4134 {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4135 {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4136 {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4137 {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4138 4139 {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4140 {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4141 {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4142 {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4143 {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4144 {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4145 {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4146 {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4147 {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4148 {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4149 {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4150 {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4151 {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4152 {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4153 {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4154 {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4155 {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4156 {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4157 {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4158 {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4159 {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4160 {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4161 {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4162 {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4163 4164 {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4165 {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4166 {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4167 {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4168 {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4169 {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4170 {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4171 {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4172 {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4173 {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4174 {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4175 {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4176 {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4177 {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4178 {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4179 {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4180 4181 {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, 4182 {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, 4183 {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}}, 4184 {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, 4185 {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, 4186 {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}}, 4187 {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, 4188 {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, 4189 {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, 4190 {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, 4191 {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, 4192 {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, 4193 4194 {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, 4195 {"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}}, 4196 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, 4197 {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, 4198 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, 4199 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}}, 4200 4201 {"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}}, 4202 {"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}}, 4203 {"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}}, 4204 {"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}}, 4205 4206 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, 4207 4208 {"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}}, 4209 {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, 4210 {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}}, 4211 4212 {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4213 {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4214 {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4215 {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4216 {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4217 {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4218 {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4219 {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4220 {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4221 {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4222 {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4223 {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4224 {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4225 {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, 4226 {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4227 {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, 4228 {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4229 {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4230 {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4231 {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4232 {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4233 {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4234 {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4235 {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4236 4237 {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4238 {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4239 {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4240 {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4241 {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4242 {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4243 {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4244 {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4245 {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4246 {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4247 {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4248 {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4249 {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4250 {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4251 {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4252 {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4253 {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4254 {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4255 {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4256 {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4257 {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4258 {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4259 {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4260 {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4261 {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4262 {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4263 {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4264 {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4265 {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4266 {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4267 {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4268 {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4269 {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4270 {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4271 {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4272 {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4273 {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4274 {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4275 {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4276 {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4277 {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4278 {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4279 {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4280 {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4281 {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4282 {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4283 {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4284 {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4285 {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4286 {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4287 {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4288 {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4289 {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4290 {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4291 {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4292 {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4293 {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4294 {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4295 {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4296 {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4297 {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4298 {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4299 {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4300 {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4301 {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4302 {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4303 {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4304 {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4305 {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4306 {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4307 {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4308 {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4309 {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4310 {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4311 {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4312 {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4313 {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4314 {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4315 {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4316 {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4317 {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4318 {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4319 {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4320 {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4321 {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4322 {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4323 {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4324 {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4325 {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4326 {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4327 {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4328 {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4329 {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4330 {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4331 {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4332 {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4333 {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4334 {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4335 {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4336 {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4337 {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4338 {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4339 {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4340 {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4341 {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4342 {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4343 {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4344 {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4345 {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4346 {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4347 {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4348 {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4349 {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4350 {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4351 {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4352 {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4353 {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4354 {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4355 {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4356 {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4357 {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4358 {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4359 {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4360 {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4361 {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4362 {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4363 {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4364 {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4365 {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4366 {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4367 {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4368 {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4369 {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4370 {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4371 {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4372 {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4373 {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4374 {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4375 {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4376 {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4377 4378 {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4379 {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4380 {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4381 {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4382 {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4383 {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4384 {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4385 {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4386 {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4387 {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4388 {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4389 {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4390 {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4391 {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4392 {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4393 {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4394 {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4395 {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4396 {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4397 {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4398 {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4399 {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4400 {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4401 {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4402 {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4403 {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4404 {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4405 {"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4406 {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4407 {"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4408 {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4409 {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4410 {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4411 {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4412 {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4413 {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4414 {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4415 {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4416 {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4417 {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4418 {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4419 {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4420 {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4421 {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4422 {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4423 {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4424 {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4425 {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4426 4427 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4428 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4429 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4430 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4431 {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 4432 {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 4433 {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 4434 {"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 4435 4436 {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}}, 4437 4438 {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}}, 4439 {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4440 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, 4441 4442 {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}}, 4443 {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, 4444 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, 4445 4446 {"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}}, 4447 {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, 4448 4449 {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, 4450 4451 {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4452 4453 {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}}, 4454 4455 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4456 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}}, 4457 4458 {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}}, 4459 {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4460 4461 {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}}, 4462 4463 {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4464 4465 {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4466 4467 {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}}, 4468 4469 {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}}, 4470 {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4471 4472 {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}}, 4473 {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}}, 4474 4475 {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 4476 4477 {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4478 4479 {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 4480 4481 {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}}, 4482 {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4483 4484 {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 4485 {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 4486 4487 {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}}, 4488 {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}}, 4489 4490 {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4491 {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4492 {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4493 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4494 {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4495 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4496 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4497 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4498 {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4499 {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4500 {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4501 {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4502 {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4503 {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4504 {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4505 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4506 {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4507 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4508 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4509 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4510 {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4511 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4512 {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4513 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4514 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4515 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4516 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4517 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4518 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4519 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4520 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4521 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4522 {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4523 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4524 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4525 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4526 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4527 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4528 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4529 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4530 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4531 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4532 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4533 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4534 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4535 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4536 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4537 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4538 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4539 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4540 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4541 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4542 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4543 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4544 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4545 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4546 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4547 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4548 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4549 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4550 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4551 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4552 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4553 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4554 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4555 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4556 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4557 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4558 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4559 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4560 {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4561 {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4562 {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4563 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4564 {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4565 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4566 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4567 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4568 {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4569 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4570 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4571 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4572 {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4573 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4574 {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4575 {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4576 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4577 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4578 {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4579 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4580 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4581 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4582 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4583 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4584 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4585 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4586 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4587 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4588 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4589 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4590 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4591 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4592 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4593 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4594 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4595 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4596 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4597 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4598 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4599 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4600 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4601 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4602 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4603 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4604 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4605 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4606 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4607 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4608 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4609 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4610 4611 {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4612 {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4613 {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4614 {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4615 {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4616 {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4617 {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4618 {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4619 {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4620 {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4621 {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4622 {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4623 {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4624 {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4625 {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4626 {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4627 {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4628 {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4629 {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4630 {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4631 4632 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4633 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4634 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4635 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4636 {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 4637 {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 4638 {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 4639 {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 4640 4641 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 4642 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 4643 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 4644 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 4645 {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, 4646 {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, 4647 4648 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4649 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4650 4651 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4652 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4653 4654 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, 4655 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, 4656 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4657 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4658 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, 4659 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, 4660 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4661 {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4662 4663 {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, 4664 {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, 4665 4666 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, 4667 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 4668 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 4669 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, 4670 {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 4671 {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 4672 4673 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4674 {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4675 {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4676 4677 {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4678 {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4679 4680 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4681 {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4682 {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4683 4684 {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4685 {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4686 4687 {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4688 {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4689 4690 {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4691 {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4692 4693 {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, 4694 {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, 4695 {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4696 {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, 4697 {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, 4698 {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4699 4700 {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, 4701 {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, 4702 4703 {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4704 {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4705 4706 {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4707 {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4708 4709 {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, 4710 {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, 4711 {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, 4712 {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, 4713 4714 {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, 4715 {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, 4716 4717 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, 4718 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, 4719 {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L, RA, RB}}, 4720 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, 4721 4722 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4723 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4724 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4725 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4726 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4727 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4728 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4729 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4730 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4731 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4732 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4733 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4734 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4735 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4736 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4737 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4738 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4739 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4740 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4741 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4742 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4743 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4744 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4745 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4746 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4747 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4748 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4749 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4750 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, 4751 {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4752 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4753 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, 4754 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}}, 4755 4756 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4757 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4758 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 4759 4760 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4761 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4762 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 4763 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4764 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4765 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 4766 4767 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 4768 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 4769 4770 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4771 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4772 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4773 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4774 4775 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 4776 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 4777 4778 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 4779 4780 {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, 4781 4782 {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}}, 4783 {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}}, 4784 {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 4785 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}}, 4786 4787 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}}, 4788 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}}, 4789 4790 {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, 4791 4792 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, 4793 4794 {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}}, 4795 4796 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, 4797 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 4798 4799 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 4800 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 4801 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 4802 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 4803 4804 {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, 4805 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, 4806 {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, 4807 {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, 4808 4809 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 4810 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 4811 4812 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, 4813 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, 4814 4815 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, 4816 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, 4817 4818 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 4819 4820 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, 4821 {"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}}, 4822 4823 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 4824 4825 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, 4826 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, 4827 {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L, RA, RB}}, 4828 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, 4829 4830 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4831 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4832 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 4833 4834 {"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, 4835 4836 {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, 4837 4838 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4839 4840 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, 4841 4842 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 4843 4844 {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, 4845 4846 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, 4847 4848 {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 4849 {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}}, 4850 {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 4851 {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}}, 4852 4853 {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, 4854 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, 4855 {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, 4856 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}}, 4857 4858 {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, 4859 4860 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}}, 4861 4862 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, 4863 4864 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}}, 4865 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 4866 4867 {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, 4868 {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, 4869 4870 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, 4871 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, 4872 4873 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, 4874 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, 4875 {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}}, 4876 4877 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 4878 4879 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}}, 4880 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}}, 4881 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}}, 4882 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}}, 4883 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}}, 4884 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}}, 4885 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}}, 4886 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}}, 4887 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}}, 4888 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}}, 4889 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}}, 4890 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}}, 4891 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}}, 4892 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}}, 4893 {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}}, 4894 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}}, 4895 4896 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 4897 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 4898 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 4899 4900 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 4901 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 4902 4903 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, 4904 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, 4905 4906 {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}}, 4907 4908 {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}}, 4909 4910 {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, 4911 4912 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}}, 4913 {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L}}, 4914 4915 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, 4916 4917 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 4918 4919 {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}}, 4920 4921 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4922 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 4923 4924 {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}}, 4925 {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}}, 4926 4927 {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 4928 {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 4929 4930 {"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, 4931 4932 {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, 4933 4934 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, 4935 {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, 4936 {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, 4937 4938 {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, 4939 4940 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, 4941 4942 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}}, 4943 4944 {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}}, 4945 4946 {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}}, 4947 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, 4948 {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}}, 4949 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, 4950 4951 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 4952 4953 {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, 4954 4955 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, 4956 4957 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 4958 4959 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 4960 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 4961 4962 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4963 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4964 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4965 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4966 4967 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4968 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4969 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4970 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4971 4972 {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, 4973 4974 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}}, 4975 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, 4976 4977 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}}, 4978 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}}, 4979 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}}, 4980 4981 {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}}, 4982 4983 {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}}, 4984 4985 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 4986 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 4987 4988 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, 4989 4990 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, 4991 4992 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, 4993 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, 4994 4995 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, 4996 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, 4997 4998 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, 4999 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, 5000 5001 {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, 5002 5003 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5004 5005 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5006 5007 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}}, 5008 5009 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5010 5011 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5012 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5013 5014 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, 5015 5016 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, 5017 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, 5018 5019 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}}, 5020 5021 {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 5022 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5023 {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, 5024 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}}, 5025 5026 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, 5027 5028 {"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}}, 5029 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}}, 5030 5031 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, 5032 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 5033 5034 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}}, 5035 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}}, 5036 5037 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, 5038 5039 {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, 5040 5041 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, 5042 5043 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5044 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5045 5046 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5047 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5048 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5049 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5050 5051 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5052 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5053 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5054 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5055 5056 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, 5057 5058 {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, 5059 5060 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5061 {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, 5062 {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 5063 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}}, 5064 5065 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 5066 5067 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, 5068 5069 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, 5070 5071 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, 5072 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, 5073 5074 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, 5075 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, 5076 5077 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5078 5079 {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, 5080 5081 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5082 5083 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5084 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5085 5086 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5087 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5088 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5089 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5090 5091 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5092 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5093 5094 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5095 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5096 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5097 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5098 5099 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5100 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5101 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5102 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5103 5104 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, 5105 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, 5106 {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, 5107 {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, 5108 5109 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5110 {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, 5111 {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 5112 5113 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, 5114 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, 5115 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, 5116 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, 5117 5118 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}}, 5119 5120 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}}, 5121 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}}, 5122 5123 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, 5124 5125 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5126 5127 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, 5128 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, 5129 5130 {"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5131 5132 {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, 5133 5134 {"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5135 5136 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5137 {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5138 {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5139 5140 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, 5141 5142 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5143 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5144 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5145 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5146 5147 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, 5148 5149 {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}}, 5150 {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 5151 5152 {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}}, 5153 5154 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}}, 5155 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}}, 5156 5157 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, 5158 5159 {"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}}, 5160 5161 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, 5162 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, 5163 5164 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, 5165 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, 5166 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, 5167 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, 5168 5169 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, 5170 5171 {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}}, 5172 5173 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, 5174 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, 5175 5176 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5177 5178 {"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}}, 5179 5180 {"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5181 {"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5182 5183 {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 5184 5185 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}}, 5186 5187 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, 5188 {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, 5189 {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}}, 5190 {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}}, 5191 5192 {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}}, 5193 5194 {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}}, 5195 5196 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, 5197 5198 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}}, 5199 5200 {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}}, 5201 5202 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, 5203 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, 5204 5205 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5206 5207 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}}, 5208 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}}, 5209 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}}, 5210 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}}, 5211 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}}, 5212 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}}, 5213 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}}, 5214 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}}, 5215 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}}, 5216 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}}, 5217 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}}, 5218 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}}, 5219 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}}, 5220 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}}, 5221 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}}, 5222 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}}, 5223 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}}, 5224 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}}, 5225 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}}, 5226 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}}, 5227 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}}, 5228 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}}, 5229 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}}, 5230 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}}, 5231 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}}, 5232 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}}, 5233 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}}, 5234 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}}, 5235 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}}, 5236 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}}, 5237 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}}, 5238 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}}, 5239 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}}, 5240 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}}, 5241 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}}, 5242 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}}, 5243 5244 {"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5245 5246 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, 5247 5248 {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5249 {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5250 5251 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 5252 5253 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}}, 5254 {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}}, 5255 5256 {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}}, 5257 5258 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}}, 5259 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}}, 5260 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, 5261 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, 5262 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}}, 5263 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}}, 5264 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}}, 5265 {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}}, 5266 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}}, 5267 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, 5268 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, 5269 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}}, 5270 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}}, 5271 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, 5272 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}}, 5273 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}}, 5274 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}}, 5275 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}}, 5276 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}}, 5277 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}}, 5278 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}}, 5279 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}}, 5280 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}}, 5281 {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}}, 5282 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}}, 5283 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}}, 5284 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}}, 5285 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}}, 5286 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}}, 5287 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}}, 5288 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}}, 5289 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}}, 5290 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}}, 5291 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}}, 5292 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}}, 5293 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}}, 5294 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}}, 5295 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}}, 5296 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}}, 5297 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}}, 5298 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}}, 5299 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}}, 5300 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}}, 5301 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5302 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5303 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5304 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5305 {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, 5306 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}}, 5307 {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, 5308 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}}, 5309 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}}, 5310 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}}, 5311 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}}, 5312 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}}, 5313 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, 5314 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}}, 5315 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}}, 5316 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}}, 5317 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}}, 5318 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}}, 5319 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}}, 5320 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}}, 5321 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}}, 5322 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}}, 5323 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}}, 5324 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}}, 5325 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}}, 5326 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}}, 5327 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}}, 5328 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}}, 5329 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}}, 5330 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}}, 5331 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}}, 5332 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}}, 5333 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}}, 5334 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}}, 5335 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}}, 5336 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}}, 5337 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}}, 5338 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}}, 5339 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}}, 5340 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}}, 5341 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}}, 5342 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}}, 5343 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}}, 5344 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}}, 5345 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}}, 5346 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, 5347 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}}, 5348 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}}, 5349 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}}, 5350 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5351 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}}, 5352 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5353 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}}, 5354 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}}, 5355 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5356 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5357 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}}, 5358 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}}, 5359 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}}, 5360 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}}, 5361 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}}, 5362 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}}, 5363 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5364 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5365 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5366 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, 5367 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}}, 5368 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}}, 5369 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}}, 5370 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}}, 5371 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}}, 5372 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}}, 5373 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}}, 5374 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}}, 5375 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}}, 5376 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}}, 5377 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}}, 5378 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}}, 5379 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}}, 5380 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}}, 5381 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}}, 5382 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}}, 5383 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}}, 5384 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}}, 5385 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}}, 5386 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}}, 5387 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}}, 5388 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}}, 5389 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}}, 5390 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}}, 5391 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}}, 5392 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}}, 5393 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}}, 5394 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}}, 5395 {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}}, 5396 {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}}, 5397 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}}, 5398 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}}, 5399 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}}, 5400 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}}, 5401 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}}, 5402 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}}, 5403 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}}, 5404 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}}, 5405 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}}, 5406 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}}, 5407 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}}, 5408 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}}, 5409 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}}, 5410 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}}, 5411 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}}, 5412 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}}, 5413 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}}, 5414 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}}, 5415 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}}, 5416 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}}, 5417 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}}, 5418 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}}, 5419 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}}, 5420 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}}, 5421 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}}, 5422 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}}, 5423 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}}, 5424 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}}, 5425 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}}, 5426 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}}, 5427 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}}, 5428 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}}, 5429 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}}, 5430 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}}, 5431 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}}, 5432 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}}, 5433 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}}, 5434 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}}, 5435 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}}, 5436 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}}, 5437 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}}, 5438 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}}, 5439 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}}, 5440 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}}, 5441 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}}, 5442 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}}, 5443 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}}, 5444 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}}, 5445 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}}, 5446 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}}, 5447 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}}, 5448 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}}, 5449 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}}, 5450 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}}, 5451 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}}, 5452 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}}, 5453 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}}, 5454 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}}, 5455 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}}, 5456 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}}, 5457 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}}, 5458 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}}, 5459 5460 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, 5461 5462 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 5463 5464 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, 5465 5466 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 5467 5468 {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}}, 5469 {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}}, 5470 5471 {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5472 {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5473 5474 {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 5475 5476 {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}}, 5477 5478 {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}}, 5479 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}}, 5480 {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}}, 5481 5482 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}}, 5483 5484 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 5485 5486 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}}, 5487 5488 {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, 5489 5490 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, 5491 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, 5492 5493 {"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 5494 5495 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5496 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5497 5498 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5499 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5500 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5501 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5502 5503 {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 5504 {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 5505 5506 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, 5507 5508 {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}}, 5509 5510 {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}}, 5511 5512 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, 5513 5514 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, 5515 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, 5516 5517 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, 5518 5519 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, 5520 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, 5521 5522 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5523 5524 {"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}}, 5525 5526 {"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 5527 5528 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, 5529 5530 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5531 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5532 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5533 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5534 5535 {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 5536 5537 {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}}, 5538 5539 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, 5540 5541 {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 5542 5543 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, 5544 5545 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, 5546 5547 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}}, 5548 5549 {"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}}, 5550 5551 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for 5552 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */ 5553 {"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}}, 5554 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}}, 5555 {"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}}, 5556 {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}}, 5557 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, 5558 {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}}, 5559 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, 5560 5561 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}}, 5562 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}}, 5563 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}}, 5564 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}}, 5565 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}}, 5566 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}}, 5567 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}}, 5568 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}}, 5569 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}}, 5570 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}}, 5571 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}}, 5572 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}}, 5573 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}}, 5574 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}}, 5575 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}}, 5576 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}}, 5577 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}}, 5578 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}}, 5579 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}}, 5580 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}}, 5581 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}}, 5582 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}}, 5583 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}}, 5584 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}}, 5585 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}}, 5586 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}}, 5587 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}}, 5588 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}}, 5589 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}}, 5590 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}}, 5591 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}}, 5592 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}}, 5593 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}}, 5594 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}}, 5595 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}}, 5596 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}}, 5597 5598 {"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 5599 5600 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, 5601 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, 5602 5603 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5604 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5605 5606 {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 5607 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 5608 5609 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}}, 5610 {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}}, 5611 5612 {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}}, 5613 5614 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}}, 5615 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}}, 5616 {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}}, 5617 {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}}, 5618 {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}}, 5619 {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}}, 5620 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, 5621 {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, 5622 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}}, 5623 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}}, 5624 {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}}, 5625 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}}, 5626 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, 5627 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}}, 5628 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}}, 5629 {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}}, 5630 {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}}, 5631 {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}}, 5632 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}}, 5633 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}}, 5634 {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}}, 5635 {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}}, 5636 {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}}, 5637 {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}}, 5638 {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}}, 5639 {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}}, 5640 {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}}, 5641 {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}}, 5642 {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}}, 5643 {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}}, 5644 {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}}, 5645 {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}}, 5646 {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}}, 5647 {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}}, 5648 {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}}, 5649 {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}}, 5650 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}}, 5651 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}}, 5652 {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}}, 5653 {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}}, 5654 {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}}, 5655 {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}}, 5656 {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}}, 5657 {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}}, 5658 {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}}, 5659 {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}}, 5660 {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}}, 5661 {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 5662 {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 5663 {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 5664 {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 5665 {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}}, 5666 {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, 5667 {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}}, 5668 {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}}, 5669 {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}}, 5670 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}}, 5671 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}}, 5672 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}}, 5673 {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}}, 5674 {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}}, 5675 {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}}, 5676 {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}}, 5677 {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}}, 5678 {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}}, 5679 {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}}, 5680 {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}}, 5681 {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}}, 5682 {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}}, 5683 {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}}, 5684 {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}}, 5685 {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}}, 5686 {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}}, 5687 {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}}, 5688 {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}}, 5689 {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}}, 5690 {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}}, 5691 {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}}, 5692 {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}}, 5693 {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}}, 5694 {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}}, 5695 {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}}, 5696 {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}}, 5697 {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}}, 5698 {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}}, 5699 {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, 5700 {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}}, 5701 {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}}, 5702 {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}}, 5703 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 5704 {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}}, 5705 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 5706 {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}}, 5707 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}}, 5708 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 5709 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 5710 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5711 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5712 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5713 {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}}, 5714 {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}}, 5715 {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}}, 5716 {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}}, 5717 {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}}, 5718 {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}}, 5719 {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}}, 5720 {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}}, 5721 {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}}, 5722 {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}}, 5723 {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}}, 5724 {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}}, 5725 {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}}, 5726 {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}}, 5727 {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}}, 5728 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}}, 5729 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}}, 5730 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}}, 5731 {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}}, 5732 {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}}, 5733 {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}}, 5734 {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}}, 5735 {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}}, 5736 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}}, 5737 {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}}, 5738 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}}, 5739 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}}, 5740 {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}}, 5741 {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}}, 5742 {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}}, 5743 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}}, 5744 {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}}, 5745 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}}, 5746 {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}}, 5747 {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}}, 5748 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}}, 5749 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}}, 5750 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}}, 5751 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}}, 5752 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}}, 5753 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}}, 5754 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}}, 5755 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}}, 5756 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}}, 5757 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}}, 5758 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}}, 5759 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}}, 5760 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}}, 5761 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, 5762 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}}, 5763 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}}, 5764 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}}, 5765 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}}, 5766 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}}, 5767 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}}, 5768 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}}, 5769 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}}, 5770 {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}}, 5771 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}}, 5772 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}}, 5773 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}}, 5774 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}}, 5775 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}}, 5776 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}}, 5777 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}}, 5778 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}}, 5779 5780 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, 5781 5782 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, 5783 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, 5784 5785 {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}}, 5786 5787 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}}, 5788 5789 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5790 5791 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5792 5793 {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}}, 5794 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}}, 5795 5796 {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5797 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5798 5799 {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 5800 {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 5801 5802 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, 5803 5804 {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}}, 5805 {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}}, 5806 5807 {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}}, 5808 5809 {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, 5810 5811 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, 5812 5813 {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}}, 5814 5815 {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}}, 5816 5817 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}}, 5818 5819 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}}, 5820 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5821 5822 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5823 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5824 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 5825 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5826 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5827 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 5828 5829 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5830 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5831 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5832 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5833 5834 {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 5835 5836 {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}}, 5837 5838 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, 5839 5840 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}}, 5841 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 5842 5843 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, 5844 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 5845 5846 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, 5847 5848 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 5849 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 5850 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 5851 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 5852 5853 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, 5854 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, 5855 5856 {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}}, 5857 {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}}, 5858 5859 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 5860 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 5861 5862 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, 5863 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, 5864 5865 {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}}, 5866 5867 {"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5868 5869 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}}, 5870 5871 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}}, 5872 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5873 5874 {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 5875 {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}}, 5876 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 5877 {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}}, 5878 5879 {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}}, 5880 5881 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, 5882 5883 {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, 5884 {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, 5885 5886 {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}}, 5887 5888 {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}}, 5889 5890 {"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5891 5892 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, 5893 5894 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5895 5896 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 5897 5898 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, 5899 5900 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}}, 5901 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}}, 5902 5903 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, 5904 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, 5905 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}}, 5906 {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}}, 5907 {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, 5908 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}}, 5909 {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, 5910 {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}}, 5911 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}}, 5912 5913 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, 5914 5915 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, 5916 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}}, 5917 5918 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, 5919 5920 {"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5921 5922 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, 5923 5924 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5925 5926 {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}}, 5927 {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}}, 5928 5929 {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5930 {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5931 5932 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, 5933 5934 {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}}, 5935 5936 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, 5937 5938 {"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}}, 5939 5940 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}}, 5941 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5942 5943 {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, 5944 5945 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}}, 5946 5947 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5948 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5949 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5950 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5951 5952 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5953 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5954 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5955 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5956 5957 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, 5958 5959 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, 5960 5961 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, 5962 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 5963 5964 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, 5965 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 5966 5967 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, 5968 5969 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, 5970 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, 5971 5972 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, 5973 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, 5974 5975 {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}}, 5976 5977 {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 5978 5979 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, 5980 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5981 5982 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}}, 5983 {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}}, 5984 5985 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, 5986 5987 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, 5988 5989 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}}, 5990 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}}, 5991 5992 {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}}, 5993 5994 {"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 5995 5996 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, 5997 5998 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5999 6000 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 6001 6002 {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}}, 6003 6004 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6005 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6006 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6007 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6008 6009 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6010 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6011 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6012 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6013 6014 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, 6015 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, 6016 6017 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, 6018 6019 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, 6020 6021 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, 6022 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, 6023 6024 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, 6025 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, 6026 6027 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, 6028 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}}, 6029 6030 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, 6031 6032 {"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6033 6034 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, 6035 6036 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6037 6038 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6039 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6040 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6041 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6042 6043 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6044 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6045 6046 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6047 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6048 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6049 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6050 6051 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6052 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6053 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6054 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6055 6056 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}}, 6057 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}}, 6058 {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}}, 6059 6060 {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}}, 6061 6062 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, 6063 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}}, 6064 6065 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, 6066 6067 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, 6068 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, 6069 6070 {"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 6071 6072 {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, 6073 6074 {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6075 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, 6076 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6077 6078 {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6079 {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6080 6081 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6082 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6083 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6084 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6085 6086 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, 6087 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, 6088 6089 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 6090 {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6091 6092 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, 6093 6094 {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, 6095 6096 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6097 6098 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, 6099 6100 {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, 6101 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, 6102 6103 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 6104 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 6105 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 6106 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 6107 6108 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 6109 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 6110 6111 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, 6112 6113 {"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 6114 {"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6115 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, 6116 6117 {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6118 {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6119 6120 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, 6121 6122 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, 6123 6124 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, 6125 6126 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6127 6128 {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}}, 6129 6130 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}}, 6131 6132 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}}, 6133 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}}, 6134 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}}, 6135 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}}, 6136 6137 {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, 6138 {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, 6139 6140 {"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 6141 6142 {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, 6143 6144 {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6145 {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6146 6147 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 6148 {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, 6149 6150 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, 6151 6152 {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, 6153 6154 {"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}}, 6155 {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, 6156 {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, 6157 6158 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6159 6160 {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, 6161 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}}, 6162 {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}}, 6163 {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}}, 6164 6165 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, 6166 6167 {"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 6168 6169 {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, 6170 {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, 6171 6172 {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6173 {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6174 6175 {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6176 6177 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, 6178 6179 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, 6180 6181 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6182 6183 {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}}, 6184 6185 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}}, 6186 6187 {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, 6188 {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, 6189 6190 {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}}, 6191 6192 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, 6193 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6194 6195 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6196 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6197 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6198 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6199 6200 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 6201 {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6202 6203 {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}}, 6204 6205 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, 6206 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, 6207 6208 {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, 6209 {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, 6210 6211 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6212 6213 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, 6214 6215 {"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, 6216 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, 6217 6218 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, 6219 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, 6220 6221 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, 6222 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, 6223 6224 {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, 6225 {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, 6226 {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, 6227 {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, 6228 6229 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, 6230 6231 {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6232 6233 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}}, 6234 {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L}}, 6235 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L, RA0, RB}}, 6236 6237 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}}, 6238 6239 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6240 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6241 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6242 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6243 6244 {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6245 {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6246 6247 {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}}, 6248 6249 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, 6250 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, 6251 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, 6252 6253 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6254 6255 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, 6256 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, 6257 6258 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}}, 6259 6260 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}}, 6261 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}}, 6262 6263 {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, 6264 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, 6265 6266 {"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6267 6268 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, 6269 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, 6270 6271 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6272 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6273 6274 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6275 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6276 6277 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 6278 {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, 6279 6280 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, 6281 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}}, 6282 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}}, 6283 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, 6284 6285 {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}}, 6286 6287 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6288 6289 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, 6290 6291 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, 6292 6293 {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}}, 6294 {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}}, 6295 6296 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 6297 6298 {"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6299 6300 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, 6301 6302 {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}}, 6303 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}}, 6304 6305 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6306 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6307 6308 {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6309 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6310 6311 {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6312 6313 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}}, 6314 6315 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, 6316 6317 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6318 6319 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, 6320 {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, 6321 6322 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 6323 6324 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, 6325 6326 {"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}}, 6327 {"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}}, 6328 {"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}}, 6329 6330 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 6331 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 6332 {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}}, 6333 6334 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}}, 6335 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}}, 6336 {"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}}, 6337 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}}, 6338 6339 {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, 6340 {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 6341 6342 {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}}, 6343 {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 6344 6345 {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 6346 6347 {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 6348 6349 {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, 6350 {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 6351 6352 {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}}, 6353 {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 6354 6355 {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, 6356 6357 {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, 6358 6359 {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 6360 6361 {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 6362 6363 {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 6364 6365 {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 6366 6367 {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, 6368 6369 {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, 6370 6371 {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}}, 6372 {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 6373 6374 {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, 6375 {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 6376 6377 {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, 6378 6379 {"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, 6380 6381 {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, 6382 6383 {"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, 6384 6385 {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, 6386 6387 {"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, 6388 6389 {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, 6390 6391 {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, 6392 6393 {"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}}, 6394 {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, 6395 {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, 6396 6397 {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, 6398 {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, 6399 {"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}}, 6400 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, 6401 {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, 6402 6403 {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, 6404 {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}}, 6405 {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, 6406 6407 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6408 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6409 6410 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, 6411 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, 6412 6413 {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6414 {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6415 6416 {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6417 {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6418 6419 {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6420 {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6421 6422 {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, 6423 {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, 6424 6425 {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6426 {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6427 {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6428 {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6429 6430 {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 6431 {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 6432 6433 {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6434 {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6435 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6436 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6437 6438 {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6439 {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6440 6441 {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6442 {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6443 6444 {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6445 {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6446 6447 {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6448 {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6449 6450 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6451 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6452 6453 {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, 6454 {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, 6455 6456 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 6457 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 6458 6459 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, 6460 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, 6461 6462 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 6463 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 6464 6465 {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 6466 {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 6467 6468 {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 6469 6470 {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 6471 {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}}, 6472 {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}}, 6473 6474 {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 6475 {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 6476 6477 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6478 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6479 6480 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6481 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6482 6483 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, 6484 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, 6485 6486 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6487 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6488 6489 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6490 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6491 6492 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6493 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6494 6495 {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 6496 6497 {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 6498 {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}}, 6499 6500 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6501 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6502 6503 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6504 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6505 6506 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, 6507 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, 6508 6509 {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 6510 {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 6511 6512 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6513 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6514 6515 {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 6516 {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 6517 6518 {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6519 {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6520 {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}}, 6521 {"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6522 {"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6523 {"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6524 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}}, 6525 {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6526 {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6527 {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}}, 6528 {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6529 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}}, 6530 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6531 {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}}, 6532 {"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6533 {"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6534 {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6535 {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6536 {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6537 {"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6538 {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6539 {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6540 {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6541 {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6542 {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6543 {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 6544 {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6545 {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6546 {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6547 {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6548 {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6549 {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6550 {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 6551 {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6552 {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6553 {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6554 {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6555 {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6556 {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6557 {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6558 {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 6559 {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6560 {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6561 {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6562 {"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6563 {"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}}, 6564 {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6565 {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 6566 {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6567 {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6568 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6569 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6570 {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6571 {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6572 {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6573 {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6574 {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6575 {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6576 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6577 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6578 {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6579 {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6580 {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6581 {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6582 {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6583 {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}}, 6584 {"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, 6585 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6586 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6587 {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6588 {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6589 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 6590 {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6591 {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6592 {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6593 {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}}, 6594 {"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, 6595 {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6596 {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6597 {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 6598 {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6599 {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6600 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6601 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6602 {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6603 {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6604 {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6605 {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6606 {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6607 {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6608 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6609 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6610 {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6611 {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6612 {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6613 {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6614 {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6615 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6616 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6617 {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6618 {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6619 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 6620 {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6621 {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6622 {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6623 {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6624 {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6625 {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 6626 {"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6627 {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6628 {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6629 {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6630 {"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6631 {"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6632 {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6633 {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6634 {"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6635 {"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6636 {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6637 {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6638 {"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6639 {"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, 6640 {"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6641 {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6642 {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6643 {"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6644 {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6645 {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6646 {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6647 {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6648 {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6649 {"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6650 {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6651 {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6652 {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6653 {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6654 {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6655 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, 6656 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, 6657 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6658 {"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6659 {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6660 {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6661 {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6662 {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6663 {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6664 {"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, 6665 {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6666 {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6667 {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6668 {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6669 {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6670 {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6671 {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6672 {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6673 {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6674 {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6675 {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6676 {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6677 {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}}, 6678 {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6679 {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6680 {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6681 {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6682 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, 6683 {"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6684 {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6685 {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6686 {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6687 {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6688 {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6689 {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6690 {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6691 {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, 6692 {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6693 {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6694 {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6695 {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6696 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6697 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6698 {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6699 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6700 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6701 {"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6702 {"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6703 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6704 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6705 {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6706 {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}}, 6707 {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6708 {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6709 {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6710 {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6711 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, 6712 {"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6713 {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6714 {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6715 {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6716 6717 {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, 6718 {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, 6719 6720 {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}}, 6721 {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}}, 6722 {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, 6723 {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, 6724 {"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}}, 6725 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, 6726 {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, 6727 6728 {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}}, 6729 {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}}, 6730 {"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, 6731 6732 {"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, 6733 6734 {"daddq", XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6735 {"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6736 6737 {"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, 6738 {"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, 6739 6740 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6741 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6742 6743 {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 6744 {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 6745 6746 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, 6747 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, 6748 6749 {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6750 {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6751 6752 {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 6753 {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 6754 {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 6755 {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 6756 6757 {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 6758 {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 6759 {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 6760 {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 6761 6762 {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6763 {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6764 {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6765 {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6766 6767 {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6768 {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6769 {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6770 {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6771 6772 {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6773 {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6774 {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6775 {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6776 6777 {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, 6778 {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, 6779 6780 {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6781 {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6782 6783 {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6784 {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6785 {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6786 {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6787 6788 {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 6789 {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, 6790 {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 6791 {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, 6792 6793 {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6794 {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6795 {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6796 {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6797 6798 {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6799 {"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6800 {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6801 {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6802 6803 {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6804 {"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6805 {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6806 {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6807 6808 {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6809 {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6810 {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6811 {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6812 6813 {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6814 {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6815 {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6816 {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6817 6818 {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, 6819 6820 {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6821 {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6822 6823 {"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, 6824 {"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, 6825 6826 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6827 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6828 6829 {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 6830 6831 {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}}, 6832 {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}}, 6833 6834 {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6835 {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6836 6837 {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, 6838 6839 {"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 6840 {"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 6841 6842 {"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, 6843 {"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, 6844 6845 {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}}, 6846 {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}}, 6847 6848 {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6849 {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6850 6851 {"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 6852 {"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 6853 6854 {"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 6855 {"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 6856 6857 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6858 6859 {"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}}, 6860 6861 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 6862 6863 {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 6864 6865 {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, 6866 {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, 6867 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, 6868 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, 6869 6870 {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6871 {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6872 6873 {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6874 {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6875 {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6876 {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6877 6878 {"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}}, 6879 6880 {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 6881 6882 {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 6883 6884 {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}}, 6885 {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}}, 6886 6887 {"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 6888 {"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 6889 6890 {"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 6891 {"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 6892 6893 {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6894 {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6895 6896 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 6897 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 6898 6899 {"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, 6900 {"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, 6901 6902 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 6903 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 6904 6905 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6906 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6907 6908 {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6909 {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6910 6911 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6912 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6913 6914 {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6915 {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6916 6917 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6918 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6919 6920 {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6921 {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6922 6923 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6924 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6925 6926 {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6927 {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6928 6929 {"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6930 {"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6931 6932 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6933 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6934 6935 {"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6936 {"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6937 6938 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6939 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6940 6941 {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, 6942 {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, 6943 6944 {"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, 6945 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, 6946 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}}, 6947 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, 6948 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}}, 6949 {"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, 6950 6951 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 6952 6953 {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 6954 6955 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}}, 6956 {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}}, 6957 6958 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}}, 6959 6960 {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, 6961 {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, 6962 {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, 6963 {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, 6964 6965 {"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, 6966 {"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, 6967 6968 {"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 6969 {"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 6970 6971 {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6972 {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6973 {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6974 {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6975 {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6976 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6977 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6978 6979 {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 6980 {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 6981 {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 6982 {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 6983 6984 {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 6985 {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 6986 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 6987 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 6988 6989 {"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, 6990 {"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, 6991 6992 {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6993 {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6994 {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6995 {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6996 {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6997 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6998 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 6999 {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7000 {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7001 7002 {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, 7003 7004 {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7005 {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7006 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7007 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7008 7009 {"diexq", XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, 7010 {"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, 7011 7012 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7013 7014 {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7015 {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7016 7017 {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7018 {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7019 7020 {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, 7021 7022 {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7023 {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7024 }; 7025 7026 const int powerpc_num_opcodes = 7027 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); 7028 7029 /* The VLE opcode table. 7031 7032 The format of this opcode table is the same as the main opcode table. */ 7033 7034 const struct powerpc_opcode vle_opcodes[] = { 7035 {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}}, 7036 {"se_isync", C(1), C_MASK, PPCVLE, 0, {}}, 7037 {"se_sc", C(2), C_MASK, PPCVLE, 0, {}}, 7038 {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}}, 7039 {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}}, 7040 {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}}, 7041 {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}}, 7042 {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}}, 7043 {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}}, 7044 {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}}, 7045 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, 7046 {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}}, 7047 {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}}, 7048 {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}}, 7049 {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}}, 7050 {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}}, 7051 {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}}, 7052 {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}}, 7053 {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}}, 7054 {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}}, 7055 {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}}, 7056 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7057 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}}, 7058 {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}}, 7059 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7060 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7061 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7062 {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7063 {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7064 {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7065 {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7066 {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7067 7068 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 7069 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 7070 {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7071 {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, 7072 {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7073 {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7074 {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, 7075 {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7076 {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, 7077 {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7078 {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7079 {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7080 {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7081 {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7082 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}}, 7083 {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7084 {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7085 {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7086 {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7087 {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7088 {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7089 {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7090 {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7091 {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7092 {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7093 {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7094 {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7095 {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7096 {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, 7097 {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7098 {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}}, 7099 7100 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 7101 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 7102 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 7103 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 7104 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7105 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7106 {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7107 7108 {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7109 {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7110 {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7111 7112 {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7113 {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7114 {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7115 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}}, 7116 {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7117 {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7118 {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7119 {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7120 {"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}}, 7121 7122 {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7123 {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7124 {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7125 {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7126 7127 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7128 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7129 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7130 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7131 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7132 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7133 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7134 7135 {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 7136 {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 7137 {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 7138 {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 7139 {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 7140 {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}}, 7141 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7142 {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}}, 7143 {"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7144 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7145 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7146 {"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7147 {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, 7148 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7149 {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, 7150 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7151 {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}}, 7152 {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}}, 7153 {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}}, 7154 {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}}, 7155 {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}}, 7156 {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, 7157 {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, 7158 {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, 7159 {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, 7160 {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7161 {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7162 {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7163 {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7164 {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7165 {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7166 {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7167 {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7168 {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7169 {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7170 {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7171 {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7172 {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7173 {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7174 {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7175 {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7176 {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7177 {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7178 {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7179 {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7180 {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7181 {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7182 {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7183 {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7184 {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, 7185 {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, 7186 7187 {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 7188 {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 7189 {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 7190 {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 7191 7192 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, 7193 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, 7194 {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7195 {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7196 {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}}, 7197 {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7198 {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}}, 7199 {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7200 {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}}, 7201 {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7202 {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7203 7204 {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7205 7206 {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, 7207 {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, 7208 7209 {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}}, 7210 {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7211 7212 {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7213 {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7214 7215 {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7216 7217 {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}}, 7218 {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7219 7220 {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}}, 7221 7222 {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7223 {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7224 7225 {"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, 7226 7227 {"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, 7228 7229 {"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, 7230 7231 {"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, 7232 7233 {"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, 7234 7235 {"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, 7236 7237 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7238 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7239 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7240 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7241 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7242 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7243 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7244 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, 7245 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7246 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7247 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7248 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7249 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7250 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, 7251 {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}}, 7252 {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}}, 7253 {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}}, 7254 }; 7255 7256 const int vle_num_opcodes = 7257 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]); 7258 7259 /* The macro table. This is only used by the assembler. */ 7261 7262 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 7263 when x=0; 32-x when x is between 1 and 31; are negative if x is 7264 negative; and are 32 or more otherwise. This is what you want 7265 when, for instance, you are emulating a right shift by a 7266 rotate-left-and-mask, because the underlying instructions support 7267 shifts of size 0 but not shifts of size 32. By comparison, when 7268 extracting x bits from some word you want to use just 32-x, because 7269 the underlying instructions don't support extracting 0 bits but do 7270 support extracting the whole word (32 bits in this case). */ 7271 7272 const struct powerpc_macro powerpc_macros[] = { 7273 {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, 7274 {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, 7275 {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, 7276 {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, 7277 {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, 7278 {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, 7279 {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, 7280 {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, 7281 {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, 7282 {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, 7283 {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, 7284 {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, 7285 {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, 7286 {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, 7287 {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, 7288 {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, 7289 7290 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 7291 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 7292 {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 7293 {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 7294 {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 7295 {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 7296 {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 7297 {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 7298 {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 7299 {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 7300 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 7301 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"}, 7302 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 7303 {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"}, 7304 {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 7305 {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 7306 {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 7307 {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 7308 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, 7309 {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, 7310 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, 7311 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, 7312 7313 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"}, 7314 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 7315 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 7316 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 7317 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"}, 7318 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 7319 {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"}, 7320 {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 7321 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"}, 7322 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"}, 7323 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, 7324 }; 7325 7326 const int powerpc_num_macros = 7327 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); 7328
